JPH07281915A - Information processor for integrated circuit module synchrinizing duplex system - Google Patents

Abstract

PURPOSE:To provide an IC(integrated circuit) module synchronizing duplex system which contains a failure processing function necessary enough for a normal data processing function. CONSTITUTION:When each duplex IC is checked (compared/monitored state) by a module 1 by a mode command 105, a comparison processing means 3 compares the data and addresses received form each duplex CPU 2 with the control signals 90, 91 and 92 via the path switching means 6, 7 and 8 respectively. Each duplex error detection processing means 4 issues the commands 101, 102 and 103 based on a non-coincidence detecting signal 100 to stop the operation, to record the log information and the reset a normal state. In accordance with the reset command 103 a restarting means 4 issues a restart command 104 which initializes the CPU 2. A state storage means 9 previously sets each duplex IC module 1 in a main mode (normal processing state) or a checker mode and issues the mode command 105. Thus an external interruption control function can be distribated and an application mode can be selected in the same type of completed products. As a result, a highly flexible and reliable system is obtained together with improvement of the developing efficiency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit module synchronous dual system information processing apparatus which incorporates a failure processing function necessary and sufficient for a normal data processing function to form a synchronous dual system.

[0002]

2. Description of the Related Art A conventional integrated circuit module synchronous dual system information processing apparatus disclosed in, for example, Japanese Patent Application Laid-Open No. 59-45558, has integrated circuit modules 1a and 1b as shown in FIG.
Is composed of a single semiconductor circuit chip, and the same external input / output terminals are connected to each other to form a synchronous double system. The logic circuits 22a and 22b are configured so that the output signals 95a and 95b are not conductively connected to the same input signals 94a and 94b of a plurality of parallel n bits, on a bidirectional signal 96 line.
Logical sum of output signals 95a and 95b (in ECL logic)
Alternatively, a logical product (when using TTL logic) is applied. Comparator 33
a and 33b are logic circuits 22a and 22b and 22.
Output signals 95a, 95b and 95b from b and 22a
And 95a are compared with each other, and if they do not match, the mismatch detection signals 114a and 114b are generated. OR gate 44
a and 44b are comparators 33a and 33b and 33b.
And 33a from the disagreement detection signals 114a and 114b and 114b and 114a respectively, and when the output signals 95a and 95b do not coincide, the operation stop command 115a
And 115b are output to the logic circuits 22a and 22b.

In the conventional integrated circuit module synchronous dual system information processing apparatus of the above-mentioned conventional example, the comparison target signal group of the dual system logic is wired outside the integrated circuit module through the bidirectional terminal group and erroneous due to mutual interpolation. A method of detecting and configuring a synchronous double system (a synchronous double system with a false detection function) is adopted.

In the conventional integrated circuit module synchronous dual system information processing apparatus as described above, the synchronous dual system system is adopted because it gives a trigger for exception / abnormal processing by the built-in false detection function of the integrated circuit module. There is a problem that a series of sophisticated control is required from the outside in order to stabilize and continuously operate.

[0005]

SUMMARY OF THE INVENTION The problem to be solved by the present invention is to efficiently realize a logic circuit in an integrated circuit module synchronous dual system information processing apparatus in consideration of the cost-effectiveness ratio of the integrated circuit module built-in logic circuit scale. It is to provide a method (a synchronous double system method with a built-in failure processing function) in which resources are distributed and a failure processing function necessary and sufficient for a normal data processing function is built in an integrated circuit module to form a synchronous dual system.

[0006]

An integrated circuit module synchronous dual system information processing apparatus of the present invention is a synchronous dual system in which the same external input / output terminals of an integrated circuit module composed of a single semiconductor circuit chip are connected to each other. In order to solve the above problems, the following means are provided, and a synchronous double system system with a built-in fault handling function is adopted.

The CPU executes a general computer basic function by an integrated circuit module and is constructed in a general-purpose system. Alternatively, instead of stopping the operation by wired logic, the firmware (microprogram) or software (machine language program) does not wait until the initialization process (check reset) after erroneous detection process does not confuse external operations. Continue infinite loop processing of operation (NOP) instruction,
Alternatively, a separately provided bus interface unit suppresses an access request to the external bus so that only an operation related to external access waits. Or, at the time of check reset, set the contents of internal resources (registers and cache memory) to a state where there is no initial data or valid entries, and restart, or restart the normal log from the reload processing means separately provided in the restart processing means. Reload only information into internal resource and restart.

The comparison processing means compares each data, address, and control signal from each CPU of the dual system only when the integrated circuit module is in the comparison monitoring state (checker mode) in accordance with the mode command from the state storage means. To detect. Or, the exclusive OR of each corresponding bit with respect to the input signal (data, address and control signal) to be compared and the OR output signal to be applied to each output signal and the comparison control of each corresponding bit collectively from the comparison control means provided separately An AND output signal with the signal is generated as a mismatch detection signal. Or the logical product of the exclusive OR output signal for each corresponding bit and the comparison control signal individually provided for each corresponding bit from the comparison control means separately provided to the input signal to be compared It is generated as a mismatch detection signal.

In the integrated circuit module, the erroneous detection processing means operates in accordance with the mismatch detection signal from any one of the dual-system comparison processing means or the abnormal interrupt signal from the abnormal interrupt control means, so that the normal processing state (main Mode) Stop the operation, record each internal log information, and give an instruction to return to the normal state after the logout process is completed.

The restart processing means instructs the integrated circuit module to restart the CPU in accordance with the return instruction from the erroneous detection processing means. Alternatively, the log information of the integrated circuit module in which the failure is not detected is reloaded to the CPU internal resource at the timing of the return command by the reload processing means provided separately.

The data, address and control route switching means compares the data from each CPU of the dual system with the address and control signal only in the checker mode in accordance with the mode command from the state storage means in the integrated circuit module. Switch the route so as to lead to.

The state storage means writes in advance either the checker mode or the main mode in the integrated circuit module and issues a command for the mode.

The abnormal interrupt control means is a synchronous communication for logout processing together with a hardware failure detection signal from the outside, instead of the mismatch detection signal from any of the dual system comparison processing means outside the integrated circuit module. Control and generate an abnormal interrupt signal. Alternatively, a separate logout timer means resets the timer counter when a mismatch is detected and operates during erroneous detection processing, and sets each integrated circuit of the duplex system in advance for each module so as to avoid bus access conflict. Write out the information. Alternatively, separately provided write address designating means sequentially supplies the log information storage area addresses to the address bus.

The state designation terminal defines a checker mode or a main mode as either a high potential state or a low potential state in place of the state storage means in the integrated circuit module, and issues a mode command.

The state designating means issues a mode command to the state designating terminal so as to dynamically convert the checker mode and the main mode outside the integrated circuit module.

The comparison control means holds, in a control register, single or plural bit switching information for setting comparison functions collectively or individually for all bit signals to be compared in accordance with a switching command separately set in the integrated circuit module. , Generate a comparison control signal for each corresponding bit collectively or individually.

The log information recording means identifies either the checker mode or the main mode for each log information of each integrated circuit module outside the integrated circuit module, and allocates the storage area. Alternatively, the word log is matched with the upper and lower halfword areas of the word-structured external data bus and the register log information is stored separately.

The bus arbitration means arbitrates the logout process between the respective integrated circuit modules of the dual system outside the integrated circuit module and gives the bus use right to only one of them and puts the others on standby.

The logout timer means resets the timer counter when an inconsistency is detected in the integrated circuit module and operates during an erroneous detection process to set a logout start time preset for each dual system integrated circuit module so as to avoid bus access conflict. Write out each log information at the timing.

The address monitoring means refers to the log information storage area address on the address bus from the write address designating means separately provided in the abnormal interrupt control means in the integrated circuit module.

The log information writing control means writes the log information to the data bus when the address monitoring means refers to the write address so as to avoid bus access conflict in the integrated circuit module.

The connection separating means disconnects the connection with the external bus so that only the internal operation continues outside the integrated circuit module.

[0023]

In the integrated circuit module synchronous dual system information processing apparatus of the present invention, each CPU is first operated in the checker mode in accordance with a fixed or external dynamic mode command inside or outside each integrated circuit module of the dual system. The address, data, and control signals from are compared with each other, or collectively or individually controlled for comparison, and if they do not match, they are detected. Next, erroneous detection processing is performed in both the main and checker modes in accordance with the mismatch detection signal or the abnormal interrupt signal, and each CPU is instructed to stop operation, logout processing, and each return command after completion of logout. Further, the check reset of each integrated circuit module is performed according to the return instruction. At the time of logout processing, each integrated circuit identifies either the main mode or the checker mode for each log information of the module or allocates and stores the area to the word address corresponding to the upper and lower halfword areas of the external data bus. Also, logout processing is arbitrated between the integrated circuit modules, or a logout start time is preset for each integrated circuit module, or the log information is written when the write address on the address bus is referred to avoid bus access conflict. During standby, the stored logic (micro program or machine language program) stops the internal operation or suppresses the access request to the external bus only for the operation related to the external access, or connects with the external bus so that only the internal operation continues. Separate. When the check is reset, the contents of the internal resource are set to a state where there is no valid entry of initial data, or only the normal log information is reloaded to the internal resource and restarted.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, an integrated circuit module synchronous dual system information processing apparatus according to an embodiment of the present invention is such that integrated circuit modules 1a and 1b are composed of a single semiconductor circuit chip and have the same external input. The output terminals are connected together to form a synchronous dual system. CPUs (Central Processing Units) 2a and 2b execute normal computer basic functions and perform ALU (arithmetic logic operation unit).
And general registers such as work registers and control registers, cache memory, instruction decoder, execution control sequencer. Comparison processing means 3a and 3b
Is the mode command 10 from the state storage means 9a and 9b.
5a and 105b only in the checker mode (comparison monitoring state), data signals 90a and 90b and 90b and 90a from CPUs 2a and 2b and 2b and 2a, address signals 91a and 91b and 91b and 91a, and output control signals 92a and 92b and When 92b and 92a are compared with each other and they do not match, the mismatch detection signals 100a and 100b are generated. The false detection processing means 4a and 4b are
According to the mismatch detection signals 100a or 100b and 100b or 100a from the comparison processing means 3a or 3b and 3b or 3a, the operation is stopped so as to stop the operation of the integrated circuit modules 1a and 1b in the main mode (normal processing state) or the checker mode. It issues commands 101a and 101b. Further, logout commands 102a and 102b are issued so as to record log information (information relating to hardware failure detection) of each part in the integrated circuit modules 1a and 1b. When the logout process is completed, the restore commands 103a and 103b are issued to restore the normal state. The restart processing means 5a and 5b use the return command 10 from the erroneous detection processing means 4a and 4b.
In accordance with 3a and 103b, restart instructions 104a and 104b are issued so as to perform a check reset of the CPUs 2a and 2b (initialization processing after erroneous detection processing). Data, address and control path switching means 6a and 6b, 7a and 7b and 8
a and 8b are CP only in the checker mode according to the mode commands 105a and 105b from the state storage means 9a and 9b.
Data signals 90a from U2a and 2b and 2b and 2a
And 90b and 90b and 90a, address signals 91a and 91b and 91b and 91a, and output control signal 9
The paths are switched so as to lead 2a and 92b and 92b and 92a to the comparison processing means 3a and 3b, respectively. The state storage means 9a and 9b have a PROM (programmable read-only memory) or an EPROM (erasable PR) which is set in advance in either a main mode or a checker mode in advance, for example, when incorporated.
OM) and the integrated circuit modules 1a and 1b
Mode commands 105a and 105 to change the mode
Do b.

In the integrated circuit module synchronous dual system information processing apparatus of the above embodiment, a method of constructing a synchronous dual system by incorporating a failure processing function necessary and sufficient for a normal data processing function in the integrated circuit modules 1a and 1b ( Synchronous dual system with built-in fault handling function) is adopted.

The erroneous detection processing means 4a and 4b are provided by the comparison processing means 3a or 3b.
00b, the erroneous detection process is performed in synchronization with the main mode of the integrated circuit module 1a or 1b in the same manner as in the checker mode while communicating with each other.

In the above embodiment, the erroneous detection processing means 4a and 4
Although b has been described as directly receiving the mismatch detection signal 100a or 100b from the comparison processing means 3a or 3b, the abnormal interrupt control means 10 separately provided externally as shown in FIG. 2 causes the mismatch processing from the comparison processing means 3a or 3b. An abnormal interrupt signal 10 generated by performing synchronous communication control for logout processing together with an external hardware failure detection signal 106 instead of the detection signal 100a or 100b.
7a and 107b may be received. The fault handling function can be shared.

In addition, the above-mentioned embodiment uses the state storage means 9a and 9b.
In the above description, the predetermined mode is set at the time of incorporation. However, the high potential state and the low potential state are defined as either the main mode or the checker mode by the state designation terminal separately provided as shown in FIG. It may be 105b.

In the above embodiment, the state designating terminal fixedly designates the role of the mode function in reverse. However, as shown in FIG. 4, the state designating means 11 provided outside is used to change the role of the mode function. Alternatively, for example, the state may be designated so as to be alternately and periodically converted. Since both of the double comparison processing means 3a and 3b are used, the symmetry is good in the use of the circuit parts and the resources can be effectively used. Further, if the failure of the integrated circuit module 1a or 1b is limited to the main mode and the normal one is used as the checker mode, such as when either one of the comparison processing means 3a and 3b fails, the checker mode is provisionally used. The system can be operated continuously.

In the above embodiment, the comparison processing means 3a and 3b are used.
Are comparison control means 12a and 12 provided separately as shown in FIG.
In b, according to the switching commands 108a and 108b from the CPUs 2a and 2b (or external), single bit switching information for collectively setting the comparison function for all bit signals to be compared is held in the control register, and each corresponding bit batch is stored. It is also possible to generate the comparison control signals 109a and 109b, and suppress the subsequent mismatch detection once they are detected, for example. The false detection process can be continued smoothly. The comparison processing means 3a and 3
6b, as shown in FIG. 6 (a), an OR signal output signal to be applied to each output signal of exclusive OR for each corresponding bit with respect to an input signal to be compared, for example, A and B, and comparison control means 12a and 12b.
Of the corresponding control signals 109a and 10
9b is a logical product output signal and a mismatch detection signal 100a and 1
It is generated as 00b. For example, the comparison control signal 109a
And the logic of 109b is "1", the comparison function operates,
If it is "0", the logic of the mismatch detection signals 100a and 100b is always set to "0" to suppress the comparison function operation. Even in the circuit configuration of FIG. 6B, the comparison function operation is switched in exactly the same manner.

Further, in the above embodiment, the comparison control means 12a and 1
It has been described that 2b holds single bit switching information for collectively setting the comparison function for all bit signals to be compared and generates the comparison control signals 109a and 109b for each corresponding bit collectively, but FIG. As described above, the plural bits switching information for individually setting the comparison function may be held and the comparison control signals 109a-1 to 109x and 109b-1 to x individually for each corresponding bit may be generated. The comparison function operation can be switched individually for each corresponding bit. Comparison processing means 3a and 3 according to the above
As shown in FIG. 7B, b is an exclusive OR output signal for each corresponding bit with respect to an input signal to be compared, for example, A and B, and individual comparison control for each corresponding bit from the comparison control means 12a and 12b. Signals 109a-1 to x and 109b-1 to x
AND output signals which are applied to the respective output signals are generated as the mismatch detection signals 100a and 100b. The comparison control means 12a and 12b have been described as holding the multi-bit switching information for setting the comparison function individually for each corresponding bit, but the comparison function is set for every two groups for data, address and control signals. Needless to say, for example, 6-bit switching information may be held.
The comparison function operation can be switched for each group.

In the above embodiment, the integrated circuit module 1a
8 and 1b are separately provided log information storage means 13 as shown in FIG. 8 for identifying either the main mode or the checker mode for each integrated circuit module 1a and 1b, and allocating the log information storage area. May be. Instead of individually exchanging the integrated circuit modules with each other, for example, the external abnormal interrupt control means 10 may perform sequential writing control such as writing log information in the checker mode after the main mode. Each integrated circuit module 1
Since a and 1b self-recognize the mode, an identifier can be added to the log information at the time of collection, and continuous or discrete areas of different addresses can be designated in advance as storage locations.
The log information recording means 13 is a general storage method having a configuration in which log information collected during and after erroneous detection processing is not lost in order to deal with the possibility of sudden stoppage of the system due to erroneous detection processing. It may be a main storage device or a magnetic disk device.

Further, in the above embodiment, the log information recording means 13 is, for example, as shown in FIG. 9, each of the CPUs 2a in the main mode and the checker mode in the bits 0 to 15 and the bits 16 to 31 of the 32-bit external data bus. The register log information in 2b may be synchronized to match the word addresses in the register log area, and the main mode and checker mode may be separately stored in the upper and lower halfword areas. Multiple drive can be avoided. As a drive signal for synchronizing the logout commands 102a and 102b, there are a method of directly obtaining the mismatch detection signal 100a or 100b and a method of obtaining the abnormal interrupt signals 107a and 107b via the abnormal interrupt control means 10.

In the above embodiment, the integrated circuit module 1a is also used.
And 1b are write signals 112a and 112 as shown in FIG.
When trying to access each log information individually to the log information recording means 13 in b, the bus arbitration means 1 separately provided outside
In step 4, the integrated circuit modules 1a and 1b may be arbitrated so that only one of them is given the bus use right and the other is put on standby. The bus arbitration means 14 first receives the bus use request signal 11 from either the integrated circuit module 1a or 1b.
0a or 110b is received, and the bus use approval signal 111 is received.
Reply a or 111b. Only the respondent occupies the bus and connects to write the log information. After the end, the bus use request signal 110a or 110b is withdrawn and the connection with the bus is cut off. Next, the bus arbitration means 14 side also withdraws the bus use approval signal 111a or 111b, and repeats the same reply processing as the integrated circuit module 1b or 1a which is transmitting the subsequent bus use request signal 110b or 110a. Furthermore, bus use request signals 110a and 110
When b is received at the same time, the bus use approval signal 111a or 110b is returned to only one of the integrated circuit modules 1a and 1b in a predetermined priority order. FIG. 11 shows the timing relationship between the bus use request signals 110a and 110b, the bus use approval signals 111a and 111b, and the write signals 112a and 112b.

In the above embodiment, the integrated circuit module 1a
1 and 1b have been described as performing logout processing according to the bus arbitration means 14 separately provided outside, but with the logout timer means 15a and 15b separately provided as shown in FIG. 12, the timer counter is reset at the time of mismatch detection to operate during erroneous detection processing. The logic circuit may generate the log information write-out timing signals 113a and 113b at a preset logout start time for each integrated circuit module 1a and 1b to avoid the bus access conflict. If the log information writing time zone of each integrated circuit module 1a and 1b is determined in advance, the buses can be used properly without disturbing each other.
The logout timer means 15a and 15b are provided in, for example, the external abnormal interrupt control means 10 instead of being provided in the integrated circuit modules 1a and 1b, and the log information writing timing signals 113a and 113b are provided in the integrated circuit modules 1a. And 1b, or may be fixed to either the main mode or the checker mode in advance and output to either of the integrated circuit modules 1a and 1b. Since the output timings of the integrated circuit modules 1a and 1b are individually instructed, bus access does not conflict in the logout process.

In the above embodiment, the integrated circuit module 1a
And 1b are separately provided logout timer means 15a and 15
Although it has been described that the logout process is performed according to step b, FIG.
Address monitoring means 16a and 16b separately provided as shown in FIG.
Further, the log information writing control means 17a and 17b refer to the log information storage area address supplied to the address bus in order from the write address designating means separately provided in the external abnormal interrupt control means 10, and when the writing address is concerned, The log information may be written to the data bus to avoid bus access conflict. Since each integrated circuit module 1a and 1b individually determines its own output timing, the bus access does not collide in the logout process. The address monitoring means 16a and 16b are
Each log information writing timing signal 11 is output from the logout timer means provided separately in the external abnormal interrupt control means 10.
If the log information storage area address is directly supplied from the write address designating means to the address bus without reference when 3a or 113b is input, the log information writing control means 17a and 17b output the log information to the data bus. You may do it.

In the above embodiment, the integrated circuit module 1a
1 and 1b are, for example, the CPUs 2a and 2b of the micro program control system as shown in FIG. 14 in a standby state in which external operations are not confused until a check reset, and a path from the micro program control storage unit is fixedly inactive. (N
OP) The restart command 10 is supplied from the ROM storing the instruction code to the microprogram instruction register.
The infinite loop processing of the NOP instruction may be continued until the timing of 4a and 104b, and the operation in each integrated circuit module 1a and 1b may be stopped at all. In the above embodiment, the operation in each of the integrated circuit modules 1a and 1b is stopped at the time of standby. However, as shown in FIG.
In the bus interface section separately provided in a and 2b, the access request to the external bus is suppressed without returning the bus use approval signals 111a and 111b to the bus use request signals 110a and 110b from the control processing section. You may make it wait only for the operation relevant to access. It is possible to continuously execute access processing only for internal registers and cache memory that are unrelated to external access. Further, in the above embodiment, when the integrated circuits are in standby for the modules 1a and 1b, connection separating means 18a and 18b are separately provided outside as shown in FIG.
Then, the connection with the external bus may be disconnected and only the internal operation may be continued.

In the above embodiment, the integrated circuit module 1a
At the time of check reset, 1 and 2b set a zero value to the effective bit of the work register and the cache memory by the control signal from the control processing unit as shown in FIG. 14, and an appropriate initial value and an effective entry to the special control register. You may make it set the state which does not exist. If each of the integrated circuit modules 1a and 1b is in the reset state, that is, in the clear state when the system is started up, the operation of the initialization software can be started. In the above embodiment, at the time of check reset, for example, the reload processing means separately provided in the restart processing means 5a and 5b,
Reloading the log information of the integrated circuit module 1a or 1b in which a failure is not detected at the timing of the return commands 103a and 103b into an internal resource such as a work register or cache memory to eliminate the cause of the mismatch detection The operation may be continuously executed as it is.
If you check the correct log information and reload each internal resource,
The processing can be continued by returning to the stop point, and it is not necessary to operate the initialization software or the like. Further, in the above embodiment, at the time of reloading, the log information storage area address may be supplied to the address bus from the write address designating means separately provided in the abnormal interrupt control means 10 and the log information may be reloaded at the same time. Each integrated circuit module 1
The values written to the internal resources of a and 1b are exactly the same and need not be reloaded separately.

[0039]

In the integrated circuit module synchronous dual system information processing apparatus of the present invention as described above, a failure processing function necessary and sufficient for a normal data processing function is built in the integrated circuit module to form a synchronous dual system. Since the system is adopted, there are the following effects as compared with the conventional synchronous double system system with a false detection function. (1) Built-in comparison processing and erroneous detection processing functions,
The functions of external interrupt control can be distributed, and work efficiency in design / verification and manufacturing cost can be improved. (2) The same product type can be used in both the normal processing state and the comparative monitoring state, and can be selected according to the required reliability level, and the development cost can be reduced. (3) The role can be changed for the completed hardware, and a flexible and highly reliable system can be constructed. (4) The built-in logout processing function can improve work efficiency during error analysis. (5) The dual system can perform high-speed logout processing at the same time or alternately in synchronization with the identification state.

[Brief description of drawings]

FIG. 1 is a functional block diagram of an integrated circuit module synchronous dual system information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a functional block diagram of another embodiment showing the present invention.

FIG. 3 is a functional block diagram of another embodiment showing the present invention.

FIG. 4 is a diagram for explaining the function of another embodiment showing the present invention.

FIG. 5 is a functional block diagram of another embodiment showing the present invention.

6 is a functional block diagram of an embodiment of the comparison processing means shown in FIG.

7 is a diagram for explaining a plurality of bits of switching information held in a control register of the comparison control means shown in FIG. 5 and a functional block diagram of another embodiment of the comparison processing means shown in FIG.

FIG. 8 is a functional block diagram of another embodiment showing the present invention.

9 is a diagram for explaining the function of an embodiment of the log information recording means shown in FIG.

FIG. 10 is a functional block diagram of another embodiment showing the present invention.

FIG. 11 is a timing chart for explaining the relationship between related signals of the bus arbitration means shown in FIG.

FIG. 12 is a functional block diagram of another embodiment showing the present invention.

FIG. 13 is a functional block diagram of another embodiment showing the present invention.

FIG. 14 is a diagram for explaining the operation during standby and during check reset in each CPU according to the embodiment of the present invention.

FIG. 15 is a functional block diagram of another embodiment showing the present invention.

FIG. 16 is a functional block diagram of an integrated circuit module synchronous dual system information processing apparatus of a conventional example.

[Explanation of symbols]

 1 integrated circuit module 2 CPU 3 comparison processing means 4 erroneous detection processing means 5 restart processing means 6 data path switching means 7 address path switching means 8 control path switching means 9 state storage means 10 abnormal interrupt control means 11 state designation means 12 comparison Control means 13 Log information recording means 14 Bus arbitration means 15 Logout timer means 16 Address bus monitoring means 17 Log information writing control means 18 Connection separation means 90 Data signal 91 Address signal 92 Output control signal 93 Input control signal 100 Mismatch detection signal 101 Operation Stop command 102 Logout command 103 Return command 104 Restart command 105 Mode command 106 Hardware error detection signal 107 Abnormal interrupt signal 108 Switching command 109 Comparison control signal 110 Bus use request signal 111 Bus use approval signal During 12 write signal 113 log information write timing signal noted figures, same reference numerals designate the same or corresponding parts.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takao Sakuma 5-1-1, Ofuna, Kamakura-shi Information Systems Research Center, Mitsubishi Electric Corporation

Claims (14)

[Claims] 1. An integrated circuit module synchronous dual system information processing apparatus in which the same external input / output terminals of an integrated circuit module composed of a single semiconductor circuit chip are connected to each other to form a synchronous dual system. With a CPU that executes normal computer basic functions and configures in a general-purpose system,
According to the mode command from the state storage means, the comparison processing means for comparing each data, the address and the control signal from each CPU of the dual system and detecting if they do not match only in the comparative monitoring state, and the comparison processing means for each of the dual system Error detection processing means for stopping the normal processing state operation inside the integrated circuit module according to any one of the mismatch detection signals, recording each internal log information, and instructing to return to the normal state after the logout processing is completed; A restart processing means for instructing to restart the CPU according to a return command from the detection processing means, and data from each CPU of the dual system only in the comparative monitoring state according to the mode command from the state storage means. Data for switching paths so that an address and a control signal are respectively guided to the comparison processing means, address and control path switching means, and較監 vision state and the normal integrated circuit module synchronous duplex system information processing apparatus including a said status storage means for the advance command mode write the one of the modes of processing state. 2. An abnormal interrupt signal for performing a synchronous communication control for logout processing together with a hardware failure signal from the outside instead of the mismatch detection signal from any of the dual system comparison processing means outside the integrated circuit module. 2. The integrated circuit module synchronous dual system information processing apparatus according to claim 1, further comprising: an abnormal interrupt control means for generating and transmitting to the erroneous detection processing means. 3. An integrated circuit module is provided with a state designation terminal instead of a state storage means, and one of a comparison monitoring state and a normal processing state is defined as a high potential state or a low potential state, and a mode command is issued. The integrated circuit module synchronous dual system information processing apparatus according to claim 1 or 2, wherein: 4. A state designating means for designating a mode to a state designating terminal so as to dynamically convert each mode of a comparison monitoring state and a normal processing state is provided outside the integrated circuit module. 3. The integrated circuit module synchronous dual system information processing device according to 3. 5. A single-bit switching information for collectively setting a comparison function for all bit signals to be compared according to a switching command separately set in the integrated circuit module is held in a control register, and a comparison control signal for each corresponding bit is stored. Logic of the comparison control means for generating, the logical sum output signal applied to each output signal of the exclusive OR for each corresponding bit with respect to the input signal to be compared, and the comparison control signal of the corresponding bits collectively from the comparison control means Comparison processing means for generating a product output signal as a mismatch detection signal is provided.
Alternatively, the integrated circuit module synchronous dual system information processing device according to item 4. 6. The comparison control means holds a plurality of bits of switching information for individually setting comparison functions for all bit signals to be compared in a control register, generates a comparison control signal for each corresponding bit, and compares them by comparison processing means. A logical product of the exclusive OR output signal for each corresponding bit and the comparison control signal for each corresponding bit from the comparison control means with respect to the input signal of interest. 6. The integrated circuit module synchronous dual system information processing device according to claim 5, wherein 7. A log information storage means is provided outside the integrated circuit module, which identifies one of a comparison monitoring state and a normal processing state for each log information of each integrated circuit module and allocates a storage area. Claim 1
2. An integrated circuit module synchronous dual system information processing device according to 2, 3, 4, 5 or 6. 8. The integrated circuit module according to claim 7, wherein the log information recording means stores the register log information separately by matching the word addresses in the upper and lower halfword areas of the word-structured external data bus. Synchronous dual system information processing device. 9. A bus arbitration means is provided outside the integrated circuit module for arbitrating a logout process between the respective dual integrated circuit modules and giving a bus use right to only one of them and waiting the other. Claims 1, 2, 3, 4,
5. An integrated circuit module synchronous dual system information processing device according to 5, 6, 7 or 8. 10. The integrated circuit module resets a timer counter when a mismatch is detected and operates during erroneous detection processing, and at each timing of a logout start time preset for each duplicated integrated circuit module so as to avoid bus access conflict. 9. The integrated circuit module synchronous dual system information processing device according to claim 1, 2, 3, 4, 5, 6, 7 or 8, further comprising logout timer means for writing out log information. 11. The integrated circuit module synchronous dual system information processing apparatus according to claim 10, wherein a logout timer means is provided in an abnormal interrupt control means separately provided outside the integrated circuit module. 12. An abnormal interrupt control means separately provided outside the integrated circuit module is provided with write address specifying means for sequentially supplying the log information storage area address to the address bus, and the integrated circuit module is provided with the write address specifying means. An address monitoring unit that refers to the log information storage area address on the address bus and a log information writing control unit that writes the log information to the data bus when the writing address is referenced by the address monitoring unit are provided so as to avoid bus access conflict. Claims 2, 3, 4, characterized in that
5. An integrated circuit module synchronous dual system information processing device according to 5, 6, 7 or 8. 13. A non-operation (NOP) instruction by firmware or software instead of stopping the operation by the wired logic in a waiting time to prevent the external operation from being confused until the initialization function after erroneous detection processing in the integrated circuit module. Endless loop processing is maintained, or a bus interface unit for suppressing an access request to an external bus is provided in the CPU so as to wait only for an operation related to external access, or an integrated circuit so as to continue only internal operation. 5. A connection separating means for disconnecting a connection with an external bus is provided outside the module.
4, 5, 6, 7, 8, 9, 10, 11 or 12, wherein the integrated circuit module synchronous dual system information processing device. 14. The integrated circuit module sets the content of the CPU internal resource to a state where there is no valid entry of initial data and restarts at the time of the initialization function after erroneous detection processing, or a restart command in the restart processing means. 2. The reloading processing means for reloading only the normal log information of the integrated circuit module whose failure is not detected at the timing of 1) to the CPU internal resource and restarting.
2. The integrated circuit module synchronous dual system information processing device according to 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 or 13.