JPH07273823A - Automatic frequency controller - Google Patents

Abstract

PURPOSE:To compose an automatic frequency control circuit which is capable of operating even under a frequency selectivity phasing. CONSTITUTION:This device is provided with a frequency conversion part 103, a quasi- synchronous detection part 100, an A/D converter 6, a complex-angle converter 7 and a delay detection circuit 101. The output of the delay detection circuit is branched into two outputs, one of the outputs is inputted in a deciding device 11 performing a hardness decision and the other is inputted in a subtracter 12 extracting frequency deviation information by the subtraction with the output of the deciding device. In addition to this constitution, the device is composed of a known data detection part 16 detecting known data in a reception signal by using the output of the deciding device and outputting a detection signal, a moving average circuit 17 storing the frequency deviation information of the output of a subtracter by the part corresponding to known data length or further by the part corresponding to the symbols of the some numbers and outputting the average value, a gate circuit 19 outputting the output value of the moving average circuit only when the known data detection part 16 outputs the detection signal, an average circuit 20 averaging and integrating the output value of the gate circuit and a D/A converter 13 performing a D/A conversion for the output of the average circuit and controlling a VCO output frequency by the output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic frequency control device for a demodulator used in mobile communication and mobile satellite communication.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a conventional automatic frequency control device shown in "Structure and characteristics of PSK base hand differential detection demodulator", 1991 Spring National Convention of the Institute of Electronics, Information and Communication Engineers, B-360. Is. In FIG. 4, the differential phase-modulated PSK signal is band-limited at the intermediate frequency and input from the input terminal 1. The oscillator 2 generates a reference signal for quasi-synchronous detection, and the phase shifter 3 outputs the reference signal and a signal having a 90 ° phase difference from the reference signal. The mixers 4 and 5 use this signal to convert the PSK signal into a complex baseband signal. The oscillator 2, the phase shifter 3, and the mixers 4 and 5 constitute a quasi-synchronous detection unit 100. A /
The D converter 6 A / D-converts the quasi-coherently detected complex base hand signal. The complex-angle converter 7 converts the A / D-converted complex digital signal into an angle signal. The delay circuit 8 delays the angle signal by one symbol. The subtractor 9 subtracts the angle signal from the complex-angle converter 7 and the angle signal one symbol before from the delay circuit 8. Then, the delay circuit 8 and the adder 9 constitute a delay detection circuit 101. The adder 10 adds the differential detection result and the angle information for correcting the frequency deviation from the averaging circuit 13. The determiner 11 makes a hard decision on the demodulation result and outputs the ideal angle of the hard decision result. The subtracter 12 outputs frequency deviation information by subtracting the ideal angle from the input of the determiner 11. The averaging circuit 13 averages and integrates the frequency deviation information obtained by the subtractor 12, and outputs it to the adder 10 as angle information for correcting the frequency deviation. Adder 10 and determiner 1
1, the subtractor 12, and the averaging circuit 13 constitute an automatic frequency control device 102 by a feedback loop.

Next, the operation will be described. The differential phase-modulated PSK signal is band-limited at the intermediate frequency and is input to the quasi-coherent detection unit 100 through the input terminal 1. The quasi-coherent detection unit 100 converts the input PSK signal into a complex baseband signal. The A / D converter 6 converts the complex baseband signal into a complex digital signal. Now, when expressing the output signal of the A / D converter by a complex number, for example, QPSK
In the case of modulation, S (nT) = {I (nT) + jQ (nT)} × {cos (ΔωnT + θi) + jsin (ΔωnT + θi)} (1). In the above equation, I (nT) is the modulation component of the real part,
Q (nT) is a modulation component of the imaginary part, and shows ± 1 at the Nyquist point. For simplicity, the Nyquist point will be used for the description below.
Δω is the residual frequency deviation in the quasi-coherent detection, θi
Represents the initial phase difference. If this is converted to polar coordinates

[0004]

[Equation 1]

In the above equation, A (nT) is an envelope component, which is 1 at the Nyquist point, and θ _M (nT) represents a phase modulation component. The differential phase modulated signal carries information on the phase difference from the previous symbol, and this phase difference is extracted by differential detection. It is assumed that the output of the complex-angle converter 7 at time nT is represented by the following equation. However, the amplitude is 1.

[0006]

[Equation 2]

If Δω = 0

[0008]

[Equation 3]

[0009] Delay detection is the received signal Sd (nT)
And the complex conjugate signal Sd ^* ((n-1) T) of the signal Sd ((n-1) T) one symbol before are obtained.
Let the differential detection result be D (nT)

[0010]

[Equation 4]

Therefore, the phase difference θ _M (nT) −θ _M ((n
-1) T) is obtained. This is the operating principle of differential detection. Therefore, the phase θ _M (n of the output of the complex-angle converter 7 is
T) + θi is subtracted from the output phase θ _M ((n−1) T) + θi of the delay circuit 8 in the subtractor 9, and the subtraction result θ _M
(NT) −θ _M ((n−1) T) is obtained and differential detection is performed. Next, when Δω ≠ 0, the complex-angle converter 7
The output is

[0012]

[Equation 5]

The differential detection output at that time is

[0014]

[Equation 6]

Therefore, deterioration occurs due to the phase rotation amount ΔωT. As can be seen from the above equation, the frequency deviation of Δω is detected as a phase error of ΔωT after the differential detection. Therefore, the output phase of the subtractor 9 when the frequency deviation Δω exists is θ _M (nT) −θ _M ((n−1)
T) + ΔωT. Next, when the output of the averaging circuit 13 is set to "0", the decision unit 11 determines the hard decision result θ _M (n
T) −θ _M ((n−1) T) is output. Then, the subtractor 12 subtracts the output of the adder 10 from the output of the determiner 11 to obtain the phase rotation amount −corresponding to the frequency deviation Δω.
ΔωT is output. Then, the averaging circuit 13 performs averaging and integration in order to remove the noise component of the phase rotation amount data −ΔωT of the output value of the subtractor 12. Thus, when feedback is applied, the output value of the averaging circuit 13 is -ΔωT
The output of the adder 10 is Da (nT) = θ _M (nT) −θ _M ((n−1) T) + ΔωT−ΔωT = θ _M (nT) −θ _M ((n−1) T) (8), and the frequency deviation is compensated. The above is the operation principle of the automatic frequency control circuit.

FIG. 5 shows an example of a circuit which has a similar function but performs error correction at an intermediate frequency unlike the above circuit.
In FIG. 5, the reception IF signal received from the input terminal 1 is input to the multiplier 14 and converted into a baseband signal by being multiplied by the output of the VCO 15. Now, assume that the signal at the input terminal 1 is represented by the following equation. C (t) = cos (θ M (T) + ω c t + Δωt + θ o) (9) In the above equation omega _c regular center frequency, theta _o represents the initial phase. Then the VCO15 output Cv (t) = 2cos (ω v t + θ v) When (10), the multiplication result of the C (t) and Cv (t) M (t) = C (t) × Cv (t ) = a _{cos ((ω c + ω v} ) t + Δωt + θ o -θ v) + cos ((ω c + ω v) t + Δωt + θ o + θ v) (11). Then, when the high-frequency component is removed by the _BPF 18, M _BPF (t) = cos ((ω _c −ω _v ) t + Δωt + θ _o −θ _v ) (12). The multiplier 14, the VCO 15, and the BPF 18 form a frequency conversion unit 103. Then, as in the case of the circuit of FIG. 4, frequency deviation information is detected from the differential detection result, and the averaging circuit 13 outputs ΔωT. D /
The A converter 13 receives ΔωT of the output of the averaging circuit 13 as an input and changes the oscillation frequency of the VCO 15 by Δω.
Therefore, the output signal of the VCO15 undergoing controlled by the D / A converter 13 output becomes Cv (t) = 2cos (ω v t + Δωt + θ v) (13). Then, the output of the _BPF 18 becomes M _BPF (t) = cos ((ω _c −ω _v ) t + θ _o −θ _v ) (14), and the frequency deviation Δω is compensated. This is the operating principle of this automatic frequency circuit. However, the conventional automatic frequency control device detects frequency information by using the result of delay detection of all received data as described above. Therefore, under the frequency selective fading transmission line in which the delay amount of the delayed wave cannot be ignored in comparison with the symbol period, the hard decision error of the differential detection (the error of the output of the decision device 11) increases, resulting in incorrect data. Frequency control using
There is a problem that the error of the frequency deviation information of the output of the subtracter 12 becomes large, and it is not practical because convergence and stable operation are difficult.

[0017]

Since the conventional automatic frequency control device is configured as described above, it is not possible to use the frequency selective fading transmission line in which the delay amount of the delayed wave is not negligible as compared with the symbol period. However, since the frequency control is performed using the erroneous differential detection result, the error of the frequency deviation information to be transmitted is large, and the convergence and the stable operation are difficult.

The present invention has been made to solve the above problems, and an object thereof is to perform high-speed and highly stable automatic frequency control under a frequency selective fading transmission line.

[0019]

In order to solve the above-mentioned problems, the means for claim 1 is a delay detection means for delay-detecting a received signal, and a frequency deviation detection means for detecting a frequency deviation from the delay detection result. The automatic frequency control device is composed of frequency deviation compensating means for compensating the frequency deviation of the signal using the data only when the detected frequency deviation is detected as correct by the means for judging.

The means for claim 2 is a known data detecting means for detecting a known data sequence from a received signal, a frequency deviation detecting means for detecting a frequency deviation from a differential detection result including the known data, and the known data detecting means. 2. The automatic frequency control device according to claim 1, further comprising frequency deviation compensating means for compensating the frequency deviation of the signal by using the frequency deviation information when known data is detected.

The means for claim 3 extracts the sample point where the most probable frequency deviation is detected from the known data detection result for the oversampled received signal,
3. The automatic frequency control device according to claim 2, further comprising frequency deviation compensating means for compensating the frequency deviation of the signal using the frequency deviation information.

The means for claim 4 comprises a loop coefficient setting means for setting a feedback loop coefficient according to the number of error bits at the time of detecting known data, and a loop coefficient multiplying means for multiplying the frequency deviation by the loop coefficient. The automatic frequency control device according to claim 2 or claim 3.

According to a fifth aspect of the present invention, in the loop coefficient setting means, the loop coefficient setting means sets the loop coefficient multiplying means for multiplying the loop coefficient and the frequency deviation by the loop coefficient according to the number of times of known data detection. The automatic frequency control device according to claim 2, claim 3 or claim 4, wherein:

According to a second aspect of the present invention, the known data detecting means comprises an allowable error bit number setting means for setting the allowable error bit number at the time of known data detection in the known data detecting means. The automatic frequency control device according to claim 3, claim 4, and claim 5.

[0025]

According to the first aspect of the present invention, the frequency control is performed by using the data which is considered to be correct in the detected frequency deviation information because the influence of the frequency selective fading is relatively small by using the differential detection result.

According to a second aspect of the present invention, the demodulator including the differential detection circuit includes the known data detection circuit to detect the known data from the differential detection result, and only when the known data is detected, the influence of the frequency selective fading is exerted. It is determined that the frequency deviation is relatively small, and the frequency control is performed using the data that the detected frequency deviation information seems to be correct.

According to a third aspect of the present invention, the sample point where the most probable frequency deviation is detected is extracted using the known data detection result for the oversampled received signal, and the frequency deviation information detected using the sample point is used. Control the frequency of the signal.

According to a fourth aspect, the feedback loop coefficient of the automatic frequency control circuit is set according to the number of error bits at the time of detecting the known data.

According to a fifth aspect of the present invention, the loop coefficient of the feedback is set according to the number of times of detection of known data, that is, the number of times of frequency control.

According to a sixth aspect of the present invention, the allowable error bit number at the time of known data detection is set according to the number of known data detections, that is, the frequency control frequency.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of claim 2 in which the same functions as those of the conventional example are indicated by the same symbols. As described above, in the past, under the frequency selective fading transmission path, that is, under the transmission path where the delayed wave exists as shown in FIG. 14 (this figure shows the case of two waves, the delay is the same for N waves). The detection result was erroneous, the frequency deviation was not correctly detected, and the operation was difficult. According to the present invention, as shown in FIGS. 15 (a) and 15 (b), only the frequency deviation information detected instantaneously in the state of only one wave, that is, in the state suitable for the differential detection is used as the control signal to achieve high speed. It is intended to realize an automatic frequency control circuit which operates stably with high pull-in. Then, as a means for judging the states of FIGS. 15A and 15B, a detection signal of known data inserted in the signal is used. Generally, known data is periodically inserted in a signal as shown in FIG. 16 and is used for frame synchronization and the like. The circuit shown in FIG. 1 is configured as follows. The received signal is the frequency conversion unit 10
3, the quasi-synchronous detection unit 100, the A / D converter 6, and the complex-angle converter 7, and the delay detection circuit 101 performs delay detection. Further, the output of the differential detection circuit 101 is branched into two,
One is a hard decision by the decision unit 11, and the other is a subtracter 12 which extracts frequency deviation information by subtraction from the output of the decision unit 11. In addition to the above configuration, the known data detection unit 16 that detects the known data in the received signal using the output of the determiner 11 and outputs the detected signal, and the frequency deviation information of the output of the subtracter 12 for the known data length Alternatively, a moving average circuit 17 that stores several symbols before and after that and outputs the average value thereof, and a gate circuit 19 that outputs the output value of the moving average circuit 17 only when the known data detection unit 16 outputs a detection signal. An averaging circuit 20 for averaging and integrating the output values of the gate circuit 19, and a D / A output of the averaging circuit 20.
It is composed of a D / A converter 13 which converts and controls the output frequency of the VCO 15 by its output. Next, FIG. 6 shows the internal structure of the known data detector 16. FIG. 6 shows an input terminal 25 to which the output data of the determiner 11 is input, a memory 26 for storing a known data pattern, the input terminal 2
5, a shift register 27 for storing the data input from 5 for a certain period of time, an exclusive OR unit 29 for comparing a known data pattern of the memory 26 with each bit of the shift register 27, and an output of the exclusive OR unit 29. The adder 28 that adds and outputs the number of mismatch bits, the output of the adder 28, and the preset allowable error bit number ε are compared, and if the number of mismatch bits is ε or less, it is determined that known data has been detected. The judging device 30 and the output terminal 31 for outputting the known data detection signal output from the judging device 30.

Next, the operation of the first embodiment will be described. The automatic frequency control device having the above configuration operates as follows. The received signal is subjected to frequency conversion, quasi-synchronous detection, A / D conversion, complex-angle conversion, differential detection, and hard decision as in the conventional example, and the subtracter 12 outputs frequency deviation information. Then, the moving average circuit 17 accumulates the output value of the subtracter 12 for the known data length or for several symbols before and after the known data length and outputs the average value. Further, the known data detector 16 receives the hard decision result after differential detection of the output of the decision device 11 as an input,
The value is held in the shift register 27 of known data length. The exclusive OR unit 29 obtains an exclusive OR of the contents of the shift register 27 and the known data for each bit. At this time, 0 is output for the matched bits and 1 is output for the unmatched bits. Therefore, by inputting this value to the adder 28, the number of unmatched bits can be obtained. The determiner 30 compares the number of mismatch bits with a preset allowable error bit number ε, and outputs a known data detection signal to the gate circuit 19 when the number of mismatch bits is less than the allowable error bit number ε. The gate circuit 19 outputs the frequency deviation information from the moving average circuit 17 only when there is a detection signal from the known data detection unit 16. Accordingly, the gate circuit 19
From, the moving average value of the frequency deviation information is output only when the known data detection signal is obtained, only by the known data length, or by using several symbols before and after the known data length. In other words, the fact that the known data detection signal is output means that the differential detection result is correct in the known data part, and the frequency deviation information detected using the data in that part can be interpreted as being correct, so it is equivalent. Only the frequency deviation information that is likely to be output is output from the gate circuit 19. The averaging circuit 20 averages and integrates likely frequency deviation information by the known data detection signal output from the gate circuit 19, and the output result controls the oscillation frequency of the VCO 15 through the D / A converter 13. In this way, the oscillation frequency of the VCO 15 changes according to the frequency deviation of the received signal, and the frequency deviation is compensated at the output of the frequency conversion unit 103.

As described above, according to the first embodiment, the frequency control is performed only when the known data is detected. Therefore, the influence of the frequency selective fading is small even under the frequency selective fading transmission line, and more probable frequency deviation information is obtained. Can be taken out, and the frequency control operation using only correct frequency deviation information becomes possible.

FIG. 11 shows the third embodiment of the present invention, and the present invention enables correct frequency control operation even when the received signal is oversampled instead of Nyquist point sampling, that is, one symbol is sampled a plurality of times. It is a thing. A configuration example of this embodiment will be shown below with reference to FIG. This embodiment is premised on oversampling 4. As in the conventional example and the first embodiment, the frequency conversion unit 103,
Quasi-coherent detection unit 100, A / D converter 6, complex-angle converter 7, differential detection circuit 101, decision unit 11, subtractor 12,
It is composed of a gate circuit 19, an averaging circuit 20, and a D / A converter 13. In the present embodiment, the A / D converter 6 and subsequent ones perform oversampling operation. In addition to the above configuration, FIG.
Known data detection unit 61 that performs known data detection using the oversampled reception signal and outputs a known data detection signal and a sample point selection signal for automatic frequency control, and known data detection by inputting oversampled frequency deviation information Of the average frequency deviation selected according to the sample point selection signal for automatic frequency control of the gate section 1
It is composed of a moving average unit 60 for outputting to 9. Next, the detailed configuration of the known data detection unit 61 will be described with reference to FIG. FIG. 12 shows an input terminal 510 for inputting the output of the decision unit 11 that makes a hard decision on an oversampled signal, a selection circuit 511 that operates with an oversampling clock and that makes one round of the output selected during one symbol, and the selection circuit 511. Shift register 513 for storing the selected terminal output signal of the known data length, memory 512 for storing the known data pattern in advance, the memory 512 and the shift register 513
Exclusive OR unit 5 for calculating the exclusive OR of each bit of
14, an adder 515 for adding the output of the exclusive OR unit 514, a comparison between the output of the adder 515 and a preset allowable error bit number ε, and if the output value of the adder 515 is ε or less, known data is The determiner 516 that outputs the known data detection signal as detected, the first internal known data detection unit 600 includes the shift register 513, the memory 512, the exclusive OR unit 514, and the adder 51.
5. The selection circuit 511 including the decision unit 516
The output of the first selection terminal of 1 is input, the known data detection signal and the output of the adder 515 at that time are output, and the operation is performed in the symbol period. The second, third, and fourth internal known data detection units 601, 602, and 603 receive the outputs of the second, third, and fourth selection terminals of the selection circuit 511, respectively, and input the known data detection signal and the adder. Output the output. A buffer 517 that outputs the known data detection signal, an output terminal 518 that outputs the output signal of the buffer 517 to the outside, and the first, second, third, and fourth internal known data detectors 600, 601, 602. , 603 outputs of the adder output, and a comparator 519 for outputting the number (1 to 4) having the smallest value, and an output terminal 520 for outputting the output of the comparator 519 to the outside. FIG. 13 shows details of the moving average unit 60. The figure shows an input terminal 530 for inputting the output of the oversampled subtracter 12,
The selection circuit 51 operates with an oversample clock.
A selection circuit 531 in which an output terminal selected for one symbol makes one round in synchronization with 1, and the first, second, third and fourth selection terminal outputs of the selection circuit 531 are used as respective inputs,
First, second, third and fourth internal moving average circuits 532 and 5 for calculating a moving average of frequency deviations using each input data
33, 534, 535 and an input terminal 536 for inputting the output signal of the comparator 519 of the known data detecting section 61, and the first, second, third and fourth input terminals 536 according to the signals input to the input terminal 536. Internal moving average circuit 532, 533, 5
Selection circuit 53 for selecting one of 34 and 535 outputs
7. An output terminal 538 for outputting the output of the selection circuit 537 to the outside. Next, the operation will be described. Generally, in the case of wireless communication, the received signal is band-limited for effective use of frequency and improvement of signal power to noise power ratio (hereinafter abbreviated as SN ratio). This is shown in FIG. In FIG. 7, the symbol sequence is -1, -1, -1, -1,1, -1,1,1,
The waveform represents a band-limited waveform in the case of 1. In such a case, only one point called a Nyquist point in one symbol is the sample point having the highest SN ratio. Therefore, the SN ratio is deteriorated at other sample points, so that the operation using only the Nyquist point (oversampling 1) is desirable. However, since clock synchronization must be established in advance in order to perform oversampling 1 operation, in a state where clock synchronization is not established, oversampling processing for sampling a plurality of one symbol is performed. FIG. 7 shows an example of oversampling 4, where a, b, c, d
Represents each sample point. As with the conventional example and the first embodiment, the 4-fold oversampled signal is subjected to hard decision and frequency deviation detection for each sample using the delay detection result.
The output of the decision unit 11 oversampled by 4 times, that is, the hard decision result is input to the known data detection unit 61. The 4 times oversampling hard decision result input to the known data detection unit 61 is determined by the selector 511 for each of the first, second, third and fourth internal known data detection units 60.
0, 601, 602, 603 are input. For example, in FIG.
Of the sample point series corresponding to a is sent to the first internal known data detecting section 600, and the sample point series corresponding to b, c, and d of the second, third, and fourth internal known data detecting section 6 respectively.
01, 602 and 603 are input. That is, the first, second, third and fourth internally known data detection units 600, 60
1, 602, 603 are sample point series a, b,
Known data detection is performed on c and d, and a detection signal and an adder output, that is, the number of mismatch bits is output. Then, the buffer 517 assumes that one or more of the first, second, third, and fourth internal known data detection units 601, 602, and 603 have been detected, and that the known data detection signal has been detected. Output to. At the same time, the number of unmatched bits of the outputs of the internal known data detection units 601, 602, 603 is input to the comparator 519. The comparator 519 selects the internal known data detection unit having the smallest number of mismatch bits and outputs the selected number. That is, by this, even if a plurality of internal known data detection units output known data detection signals, by detecting the internal known data detection unit having the smallest number of mismatched bits, the most S among a, b, c, d is detected.
A sample point series having a good N ratio, that is, a sample point series that is considered to be closest to the sample point can be detected. Then, the signal indicating the sample point series that is considered to be closest to the Nyquist point is output from the output terminal 520 to the outside. Next, the output of the subtracter 12 that has been oversampled by a factor of 4 is input to the moving average unit 60. The 4 × oversampling frequency frequency deviation data input to the moving average unit 60 is sampled by the selector 531 for each sample to the first, second, third and fourth internal moving averagers 532, 533, 534, 5
35 is input. Here, the operation of the selector 531 is synchronized with the selector 511. Therefore, the first, second, third
Fourth internal moving averager 532, 533, 534, 535
The frequency deviation information calculated using the respective sample point series a, b, c, d is stored in. The frequency deviation information based on each sample point series is selected by the selection circuit 537 according to the sample point selection signal input from the input terminal 536, and the frequency deviation information using the sample point series that is considered to be closest to the Nyquist point is selected. Output terminal 53
It is output from 8. The output of the moving average unit 60, that is, the frequency deviation information selected at the sample points, is input to the averaging circuit 20 through the gate circuit 19 when known data is detected, and then the VC through the D / A converter 13.
Select the output frequency of O15.

As described above, in the second embodiment, when the known data is detected, only the sample point having the smallest number of mismatched bits at the time of detecting the known data is extracted and the frequency control is performed, so that only the highly reliable data is extracted. Therefore, the frequency control operation can be performed with high accuracy.

FIG. 2 shows the characteristic portion of the embodiment of claim 4 by extracting it, and in the figure, those having the same function as the circuit are indicated by the same symbols. The present invention realizes a high-speed pull-in / high-stable operation by returning the detected frequency deviation information, determining the certainty of the known data when detecting the known data, and changing the weighting value. The configuration is shown below. The known data detector 70 is shown in FIG.
With the same configuration as the first internally known data detection circuit 600 shown by 2, the hard decision output of the determiner 11 is input, and the known data detection signal and the number of mismatch bits are output. The loop coefficient α setter (1) 21 receives the number of mismatched bits of the known data detection unit 70 as an input, and sets the loop coefficient α of the automatic frequency control loop according to the value. The multiplier 32 adds the loop coefficient α to the frequency deviation information of the output of the moving average circuit 17.
The loop coefficient α of the output of the setting unit (1) 21 is multiplied. Next, the operation will be described. When the known data detection unit 70 outputs the known data detection signal, the moving average circuit 17 outputs the known data signal or the frequency deviation information calculated using the symbols before and after the known data signal. It is considered that when the number of mismatched bits at the time of known data detection is small, the frequency deviation information is high in accuracy in a good reception state, and when the number of mismatched bits is large, the accuracy of frequency deviation information is low. Therefore, the loop coefficient α setter (1) 21 sets α to a large value when the number of mismatched bits at the time of detecting known data is small, and sets α to a small value when the number of mismatched bits is large. The output value of the moving average circuit 17 is weighted. As a result, the frequency information is heavily weighted in a good reception state, and the frequency information is lightly weighted in a bad reception state, so that high-speed pull-in and highly stable frequency control can be realized.

As described above, in the third embodiment, the loop coefficient α is set according to the number of mismatched bits at the time of known data detection, so that the weighting at the time of feedback according to the reliability of the frequency deviation information is appropriately set. Therefore, high-speed pull-in and highly stable frequency control operation are possible.

FIG. 3 shows a characteristic portion of the embodiment of claim 5 extracted. In the figure, the same functions as those of the circuit are shown by the same symbols. The present invention, by setting the loop coefficient α according to the number of known data detection,
High-speed pull-in and high-stable operation are realized by performing high-speed frequency control during initial pull-in and operating at low speed during steady-state, and the configuration is shown below. The input terminal 24 is
An input terminal for inputting a reset signal for initial resetting the counter 23. The counter 23 counts the number of known data detections. The loop coefficient α setter (2) 22 sets the loop coefficient α value of the automatic frequency control loop according to the output value of the counter 23. Further, the loop coefficient α is the multiplier 32
Is multiplied by the output of the moving average circuit 18. Next, the operation will be described with reference to FIGS. Generally, it is desirable that the automatic frequency control circuit compensates for the frequency deviation at high speed even if there is some variation in the control during the initial operation, and operates stably in the steady state. As shown in FIG. 8C, when the frequency control is started, the reset signal is input from the input terminal 24 and the counter output becomes zero. At this time, the loop coefficient α is set to a large value (α ₀ ) as shown in FIG. 8B, and the frequency deviation is compensated at high speed as shown in FIG. 8A. Then, when the output of the control circuit, that is, the counter 23 becomes the C ₁ value, the loop coefficient is set to the α ₁ value, and when the output of the counter 23 becomes the C ₂ value, the loop coefficient becomes a small value (α ₂ ). Once set, the frequency control becomes highly stable.

As described above, according to the fourth embodiment, by setting the loop coefficient α according to the number of times of detection of known data, it is possible to realize high-speed pull-in and high-stable operation as shown in FIG.

FIG. 10 shows the characteristic portion of claim 6 in an extracted form. In the figure, components having the same functions as those of the circuit are indicated by the same symbols. According to the present invention, by setting the allowable error bit number ε of the known data detection unit according to the known data detection number information, the frequency deviation information, which is somewhat unreliable at the time of initial pull-in, is also fed back to operate at a high speed. At all times, only highly reliable information is returned to perform highly stable operation, high-speed pull-in, and highly stable operation are realized. The configuration is shown below. The known data detection unit 80 externally sets the value of the allowable error bit number ε and detects the known data, and the allowable error bit number ε setting circuit 81 sets the counter 2
3 The value of the allowable error bit number ε is set according to the output value.
Next, the operation will be described with reference to FIGS. 10 and 9. Similar to the fourth embodiment, the counter 23 is reset at the start of frequency control, the allowable error bit number ε setting circuit 81 outputs a large value ε _{0 accordingly} , and the known data detection unit 80 inputs ε ₀ to receive known data. Detect. As a result, the known data detection unit 80 outputs a known data detection signal if the number of mismatch bits is ε ₀ or less. In other words, the frequency of outputting the known data detection signal is increased, which realizes high-speed pull-in. However, the moving average circuit 1 used here
7 outputs, that is, the frequency deviation information has low reliability and large variations. Therefore, when the control circuit for frequency control reaches C ₁ , the allowable error bit number ε setting circuit 81 sets the allowable error bit number to a small value ε ₁ to reduce the number of detections and improve the reliability of the frequency deviation information. Further, the counter 23
When the output becomes C ₂ , the allowable error bit number ε is set to a smaller value ε ₂ and only the more reliable frequency deviation information is fed back to perform a stable operation.

As described above, in the fifth embodiment, the allowable error bit number ε is set according to the known data detection number information, so that high-speed pull-in and highly stable operation can be realized.

[0042]

According to the first aspect of the invention, the frequency control is performed only when the frequency deviation information is highly reliable, so that the frequency control can be performed with high accuracy and high stability.

According to the second aspect of the present invention, known data detection is performed in order to know whether or not the frequency deviation is correctly detected, and the frequency control is performed using the data at the time of detection, that is, the data with the correct differential detection result. Since this is performed, highly accurate and highly stable frequency control becomes possible.

According to the invention of claim 3, in addition to the effect of the invention of claim 2, the frequency deviation is obtained and controlled by using only the sample point series having the smallest number of error bits when the known data is detected in the case of oversampling. By doing so, high-speed and highly accurate frequency control becomes possible.

According to the invention of claim 4, in addition to the effect of the invention of claim 2 or 3, according to the reliability of the data, the feedback loop coefficient is set according to the number of error bits when the known data is detected. Since weighting can be performed, high-speed and highly stable frequency control can be performed.

According to the invention of claim 5, in addition to the effect of the invention of claim 2, claim 3, or claim 4, the feedback loop coefficient is set according to the number of times of known data detection, so that high-speed pull-in and high-speed Stable frequency control becomes possible.

According to the invention of claim 6, in addition to the effect of the invention of claim 2, claim 3, claim 4, or claim 5, the number of allowable error bits at the time of known data detection is determined according to the number of known data detections. It becomes possible to perform high-speed and highly-stable frequency control by switching between.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of claim 2.

FIG. 2 is a configuration block diagram showing an embodiment of claim 4;

FIG. 3 is a configuration block diagram showing an embodiment of claim 5;

FIG. 4 is a configuration block diagram showing a conventional example.

FIG. 5 is a configuration block diagram showing a circuit having the same function as a conventional example.

FIG. 6 is a diagram showing an internal configuration of a known data detector.

FIG. 7 is a diagram showing an example of a band-limited reception signal.

FIG. 8 is a diagram showing frequency control by switching feedback loop coefficients.

FIG. 9 is a diagram showing frequency control by switching the number of allowable error bits.

FIG. 10 is a configuration block diagram showing an embodiment of claim 6;

FIG. 11 is a configuration block diagram showing an embodiment of claim 3;

FIG. 12 is a diagram showing a detailed configuration of a known data detection unit.

FIG. 13 is a diagram showing a detailed configuration of a moving average unit.

FIG. 14 is a diagram showing an example (1) of a received signal under a transmission path in which a delayed wave exists.

FIG. 15 is a diagram showing an example (2) of a received signal under a transmission path in which a delayed wave exists.

FIG. 16 is a diagram showing an example of a received data format.

[Explanation of symbols]

 1 Input Terminal 2 Oscillator 3 Phase Shifter 4 Mixer 5 Mixer 6 A / D Converter 7 Complex-Angle Converter 8 Delay Circuit 9 Adder 10 Adder 11 Judgmenter 12 Subtractor 13 D / A Converter 14 Multiplier 15 VCO 16 Known data detector 17 Moving average circuit 18 BPF 19 Gate circuit 20 Average circuit 21 Loop coefficient α setter (1) 22 Loop coefficient α setter (2) 23 Counter 24 Input terminal 25 Input terminal 26 Memory (known data pattern ) 27 shift register 28 adder 29 exclusive OR unit 30 determiner 31 output terminal 32 multiplier 60 moving average circuit 61 known data detection unit 70 known data detection unit 80 known data detection unit 81 error bit number ε setting circuit 100 quasi Synchronization detection unit 101 Delay detection circuit 102 Automatic frequency control device 103 Frequency conversion unit 5 10 input terminal 511 selection circuit 512 memory (known data pattern) 513 shift register 514 exclusive OR section 515 adder 516 judgment device 517 buffer 518 output terminal 519 comparator 520 output terminal 530 input terminal 531 selection circuit 532 internal moving average circuit 533 Internal Moving Average Circuit 534 Internal Moving Average Circuit 535 Internal Moving Average Circuit 536 Input Terminal 537 Selection Circuit 538 Output Terminal 600 Internal Known Data Detector 601 Internal Known Data Detector 602 Internal Known Data Detector 603 Internal Known Data Detector

Claims (6)

[Claims] 1. A delay detection unit that delay-detects a received signal, a frequency deviation detection unit that detects a frequency deviation from post-delay-detection data, and a unit that determines that the detected frequency deviation is correct. Only in the case, the automatic frequency control device is provided with a frequency deviation compensating means for compensating the frequency deviation of the signal using the data. 2. Known data detecting means for detecting a known data sequence from a received signal, frequency deviation detecting means for detecting a frequency deviation from differential detection data including the known data, and known data detecting means for detecting the known data. The automatic frequency control device according to claim 1, further comprising frequency deviation compensating means for compensating the frequency deviation of the signal using the frequency deviation information. 3. A frequency deviation compensating means for extracting a sample point where the most probable frequency deviation is detected from the known data detection result for the oversampled received signal and compensating for the frequency deviation of the signal using the frequency deviation information. The automatic frequency control device according to claim 2, further comprising: 4. A loop coefficient setting means for setting a feedback loop coefficient according to the number of error bits at the time of detecting known data, and a loop coefficient multiplication means for multiplying a frequency deviation by the loop coefficient. The automatic frequency control device according to claim 2 or claim 3. 5. The loop coefficient setting means further comprises: loop coefficient setting means for setting the loop coefficient according to the number of times of detection of known data, and loop coefficient multiplication means for multiplying the frequency deviation by the loop coefficient. The automatic frequency control device according to claim 2 or claim 3. 6. The known data detecting means comprises an allowable error bit number setting means for setting an allowable error bit number at the time of known data detection according to the number of known data detections. The automatic frequency control device according to claim 4 or claim 5.