JPH07273748A - Binary signal transfer circuit - Google Patents

Abstract

PURPOSE:To reduce the power consumption by supplying a specific signal out of a binary signal to a simultaneous bidirectional binary signal transfer circuit at the time when an input signal is ineffective. CONSTITUTION:When the input signal supplied to an input terminal 8 is ineffective, the output of an AND circuit 2 goes to the low level independently of the value of the input signal, and this value is held in an FF circuit 3. The output of the circuit 3 is inputted to a simultaneous bidirectional binary signal transfer circuit 1 and is outputted to an output terminal 13 through an FF circuit 7 on the other party side. When the input signal supplied to an input terminal 11 is ineffective, the low level is inputted to the circuit 11 through an AND circuit 5 and an FF circuit 6 and is outputted to an output terminal 10 through an FF circuit 4 in the same manner. Consequently, if input signals supplied to terminals 8 and 11 are ineffective together, signals inputted to the circuit 1 go to the low level together, and a through current doesn't flow to a transfer line 16, and the power consumption is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a binary signal transfer circuit, and more particularly to a binary signal transfer circuit capable of bidirectional binary signal transfer at the same time.

[0002]

2. Description of the Related Art A conventional binary signal transfer circuit has been implemented using a complementary MOS circuit as shown in FIG.

That is, in FIG. 3, when a high level signal (hereinafter abbreviated as H signal) is applied to the input terminal 31, the output of the inverter 32 is inverted and a low level signal (hereinafter abbreviated as L signal). And this signal is complementary M
It is applied to the OS circuit, the transistor 33 is turned on, the capacitor 35 is charged, and the same H signal as the input signal of the input terminal 31 is output to the output terminal 36.

When an L signal is applied to the input terminal 31, the output of the inverter 32 is inverted and becomes an H signal, and this signal is applied to the complementary MOS circuit. This time, the transistor 34 is turned on and the capacitor is turned on. 35 is discharged, and the same L signal as the input signal of the input terminal 31 is output terminal 3
6 is output.

In this way, the binary signal transfer circuit of FIG. 3 transfers the binary signal from the input terminal 31 to the output terminal 36. In this circuit, however, the transfer is only in one direction. That is, for two-way simultaneous signal transfer between two points, for example, signal transfer from point P to point Q and signal transfer from point Q to point P at the same time, a signal transfer path from point P to point Q is used. However, there is a problem in that two signal transfer paths, that is, a signal transfer path from the point Q to the point P, are provided in the opposite direction, and the binary signal transfer circuit shown in FIG.

FIG. 4 shows a binary signal transfer circuit improved on this point. The binary signal transfer circuit of FIG. 4 includes a circuit 41 provided at a point P, a circuit 42 provided at a point Q, and
The transfer path 43 connects these circuits.

Since the circuit 41 and the circuit 42 have the same structure, the circuit 41 will be described. The circuit 41 includes an inverter 411 and a complementary MOS circuit 4 having a power supply voltage V _DD.
12 and a comparator 413 that generates a H signal when the input level is higher than the reference voltage V _RH (V _DD / 2 <V _RH <V _DD ), and a reference voltage V _RL (V _DD / 2> V _RL > 0), and when the input level is higher than this, the comparator 414 that generates the H signal when the H signal is low and the output of the comparator 413 when the output of the inverter 411 is the L signal are selected. It is composed of a selector 415 which selects the output of the comparator 414 when the signal is the H signal.

Next, the input terminal 410 of the circuit 41 and the circuit 4
The output terminal 416 of the circuit 41 and the output terminal 42 of the circuit 42 for each combination of the input signals at the two input terminals 420
The output signal at 6 is as follows.

(1) When both the input signals of the circuit 41 and the circuit 42 are L signals: The points A1 and A2 are H signals, whereby the selector 415 selects the output of the comparator 414, and the selector 425 selects the comparator 424. Select the output of. The B1 point and the B2 point become an L signal, which causes the comparator 4
14 and the comparator 424 output the L signal. Therefore, in this case, the L signal is output to the output terminals of both circuits.

(2) When both the input signals of the circuit 41 and the circuit 42 are H signals: The points A1 and A2 become L signals, whereby the selector 415 selects the output of the comparator 413, and the selector 425 selects the comparator 423. Select the output of. The B1 point and the B2 point become an H signal, which causes the comparator 4
13 and the comparator 423 output an H signal. Therefore, in this case, the H signal is output to the output terminals of both circuits.

(3) When the input signal of the circuit 41 is the H signal and the input signal of the circuit 42 is the L signal: The A1 point becomes the L signal, and the selector 415 makes the comparator 4
13 outputs are selected. The A2 point becomes the H signal, and the selector 425 selects the output of the comparator 424. Initially B
One point is an H signal and B2 point is an L signal, but B1 point and B2 point
The potential cannot be different from that of the point and both converge to the intermediate level V _DD / 2. Therefore, the selected comparator 413 outputs the L signal, and the L signal is output to the output terminal 416 of the circuit 41. Further, the selected comparator 424 outputs the H signal, and the H signal is output to the output terminal 426 of the circuit 42.

(4) When the input signal of the circuit 41 is the L signal and the input signal of the circuit 42 is the H signal: Point A1 becomes the H signal, and the selector 415 makes the comparator 4
14 outputs are selected. The A2 point becomes the L signal, and the selector 425 selects the output of the comparator 423. Initially B
One point becomes the L signal and B2 point becomes the H signal, but B1 point and B2
The potential cannot be different from that of the point and both converge to the intermediate level V _DD / 2. Therefore, the selected comparator 414 outputs the H signal and the H signal is output to the output terminal 416 of the circuit 41. Further, the selected comparator 423 outputs the L signal, and the L signal is output to the output terminal 426 of the circuit 42.

When the above-mentioned signal transfer modes are collectively expressed, the value of the input signal to the input terminal 410 of the circuit 41 is directly output from the circuit 42 regardless of the value of the input signal to the input terminal 420 of the circuit 42. The value of the input signal to the input terminal 420 of the circuit 42 is transferred to the output terminal 416 of the circuit 41 as it is, regardless of the value of the input signal to the input terminal 410 of the circuit 41. Is transmitted as the value of the output signal of.

That is, the binary signal transfer circuit shown in FIG. 4 is a circuit capable of simultaneous bidirectional binary signal transfer only with one transfer path 43, which is an improved circuit of the binary signal transfer circuit of FIG. Is.

[0015]

The above-mentioned conventional binary signal transfer circuit shown in FIG. 4 is a circuit capable of simultaneous bidirectional binary signal transfer with only one transfer path 43.
When the input signal of 1 and the input signal of the circuit 42 are different from each other as in the cases of (3) and (4) described above, there is a problem that a through current flows through the transfer path 43 and power consumption increases. There is.

An object of the present invention is to significantly reduce power consumption as compared with the prior art by supplying a signal having a specific value among binary signals to a simultaneous bidirectional binary signal transfer circuit when an input signal is an invalid signal. It is to provide a binary signal transfer circuit.

[0017]

A binary signal transfer circuit according to a first aspect of the present invention transfers a binary signal through a simultaneous bidirectional binary signal transfer circuit for transferring a binary signal through a transmission / reception common transfer path. In the binary signal transfer circuit, when the externally supplied input signal is an invalid signal, the first specific value signal in the binary signal is output, and when the input signal is a valid signal, the input signal value is output. It has a 1st signal output means, and is constituted by supplying an output signal from the 1st signal output means to the simultaneous bidirectional binary signal transfer circuit.

A binary signal transfer circuit according to a second aspect of the present invention is the binary signal transfer circuit according to the first aspect of the present invention, wherein the first signal output means is constituted by an AND circuit and an input signal and the input signal are valid / invalid. It is configured to output a logical product with a first identification signal supplied from the outside that indicates identification.

A binary signal transfer circuit according to a third aspect of the present invention is the binary signal transfer circuit according to the first aspect of the present invention, wherein the first signal output means is constituted by an OR circuit and the input signal and the input signal are valid / invalid. It is configured to output a logical sum with a first identification signal supplied from the outside that indicates identification.

A binary signal transfer circuit according to a fourth aspect of the present invention is the binary signal transfer circuit according to the first aspect of the present invention, which outputs a first specific value signal of the binary signals when a test is performed by a scan path. In the other cases, it is configured to have the second signal output means for outputting the signal value from the first signal output means and supplying it to the simultaneous bidirectional binary signal transfer circuit.

A binary signal transfer circuit according to a fifth aspect of the present invention is the binary signal transfer circuit according to the fourth aspect of the present invention, wherein the second signal output means is a logical product circuit and the signal value from the first signal output means. And a second identification signal indicating the presence / absence of the scan path test supplied from the outside, are output.

A binary signal transfer circuit according to a sixth aspect of the present invention is the binary signal transfer circuit according to the fourth aspect of the present invention, in which the second signal output means is an OR circuit and the signal value from the first signal output means. And a second identification signal indicating the presence / absence of a scan path test supplied from the outside are output.

[0023]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of a binary signal transfer circuit of the present invention.

The binary signal transfer circuit of the first embodiment is shown in FIG.
, The simultaneous bidirectional binary signal transfer circuit 1 and the first input terminals 8 and 11 to which a binary input signal is supplied.
When the signals supplied to these input terminals are meaningful valid signals, they become H signals, and when they are meaningless invalid signals, they become L signals, and identification signals for identifying whether the input signals are valid or invalid are supplied. Second input terminals 9 and 12, a logical product circuit 2 and 5 that creates a logical product of the input signal and its identification signal, and a flip-flop that holds the input signal to the simultaneous bidirectional binary signal transfer circuit 1. Circuit 3 and 6, flip-flop circuits 4 and 7 for holding output signals from the simultaneous bidirectional binary signal transfer circuit 1, and output terminals 10 and 13.

The simultaneous bidirectional binary signal transfer circuit 1 is the same as the circuit shown in FIG. 4 described above, and the circuits 14, 15 and transfer paths 16 which are the constituent elements of the simultaneous bidirectional binary signal transfer circuit 1 are , Circuit 42 and transfer path 43 of FIG. 4, respectively.

Next, the operation of the first embodiment shown in FIG. 1 will be described.

The logical product circuit 2 creates a logical product of the input signal supplied to the first input terminal 8 and the identification signal supplied to the second input terminal 9 for identifying whether the input signal is valid or invalid. .

When the input signal is a valid signal, the identification signal indicating that the input signal is valid is the H signal. Therefore, the output of the AND circuit 2 becomes the input signal itself, and its value is held in the flip-flop circuit 3 at the same time. It is input to the binary signal transfer circuit 1, transferred to the other side, held in the flip-flop circuit 7, and output to the output terminal 13.

Similarly, the logical product of the input signal supplied to the first input terminal 11 by the logical product circuit 5 and the identification signal supplied to the second input terminal 12 for identifying whether the input signal is valid or invalid. Is created. When the input signal is a valid signal, the identification signal indicating that the input signal is valid is the H signal. Therefore, the output of the AND circuit 5 becomes the input signal itself, and its value is held in the flip-flop circuit 6 and the simultaneous bidirectional 2 It is input to the value signal transfer circuit 1, transferred to the other side, held in the flip-flop circuit 4, and output to the output terminal 10.

Thus, when the input signal is a valid signal, the simultaneous bidirectional binary signal transfer circuit 1 operates as described above with reference to FIG.

When the input signal supplied to the first input terminal 8 is an invalid signal, the identification signal indicating that the input signal is invalid is the L signal. Regardless of this, it becomes the L signal, the value of which is held in the flip-flop circuit 3 and input to the simultaneous bidirectional binary signal transfer circuit 1 to be transferred to the other side, held in the flip-flop circuit 7 and output to the output terminal 13.

Similarly, when the input signal supplied to the first input terminal 11 is an invalid signal, the identification signal indicating that the input signal is invalid is the L signal, so the output of the AND circuit 5 is the value of the input signal. Irrespective of the above, it becomes an L signal, and its value is held in the flip-flop circuit 6 and input to the simultaneous bidirectional binary signal transfer circuit 1 to be transferred to the other side, held in the flip-flop circuit 4 and output to the output terminal 10. It

That is, when the input signal is an invalid signal, the signal to be input to the simultaneous bidirectional binary signal transfer circuit 1 is always the L signal.

Therefore, the first input terminals 8 and 11
When the input signals supplied to the both are invalid signals, the signals input to the simultaneous bidirectional binary signal transfer circuit 1 for both are the same L signal, and no through current flows in the transfer path 16.

As described above, in the first embodiment, when the input signals supplied to the first input terminals 8 and 11 are both invalid signals, the through current does not flow in the transfer path 16 and the conventional method is used. This has the effect of significantly reducing power consumption as compared to the simultaneous bidirectional binary signal transfer circuit.

In the first embodiment, the logical product of the input signal and the identification signal for identifying its validity and invalidity is created. However, the identification signal indicating validity is the L signal, and the identification signal indicating invalidity is the H signal as the input signal. If the input signals supplied to the first input terminals 8 and 11 are both invalid signals, a logical sum is created with an identification signal for identifying the validity and invalidity, and a simultaneous bidirectional binary signal transfer circuit for this is provided. Even if the signals input to 1 are both the same H signal, the same effect can be obtained.

That is, when the input signal is an invalid signal, a signal having a specific value among the binary signals is output, and when the input signal is a valid signal, the signal output means for outputting the input signal value is simultaneously operated. It may be provided on the input side of the bidirectional binary signal transfer circuit 1.

FIG. 2 is a block diagram showing a second embodiment of the binary signal transfer circuit of the present invention. This is effective when the scan path method often used for testing sequential circuits is applied to the flip-flop circuit of FIG.

The binary signal transfer circuit of the second embodiment is shown in FIG.
As shown in FIG. 5, the difference in configuration from the first embodiment is that AND circuits 17 and 18 are provided between the outputs of the flip-flop circuits 3 and 6 and the simultaneous bidirectional binary signal transfer circuit 1, The logical product of the output of the scan path operation signal, which becomes the L signal during the campus operation and becomes the H signal at other times, and the output of the flip-flop circuit 3 or 5 is created and supplied to the simultaneous bidirectional binary signal transfer circuit 1. There is.

Since the outputs of the flip-flop circuits 3 and 6 change during the scan path operation, the simultaneous bidirectional binary signal transfer circuit 1 at that time is changed by the L signal which is the scan path operation signal supplied to the AND circuit. By fixing the signal supplied to the L signal to the L signal which is a specific value, it is possible to prevent the through current from flowing through the transfer path 16 and reduce the power consumption.

Although the AND circuits 17 and 18 are used in the second embodiment, the present invention is not limited to this, and a scan path operation signal which becomes the H signal during the scan path operation and becomes the L signal at other times is used. By using an OR circuit that ORs this with the output signal of the flip-flop circuit 3 or 6, the signal supplied to the simultaneous bidirectional binary signal transfer circuit 1 at the time of the scan path operation is converted into the H signal which is a specific value. Even if fixed, the same effect can be obtained.

That is, at the time of the scan path operation, the signal output means for outputting a signal of a specific value among the binary signals, and for outputting the output value of the flip-flop circuit 3 or 6 at the other time, the simultaneous bidirectional binary signal transfer. It may be provided on the input side of the circuit 1.

[0044]

As described above, in the binary signal transfer circuit of the present invention, the through current is prevented from flowing in the transfer path when both input signals supplied are invalid signals or during the scan path operation. As a result, there is an effect that power consumption can be significantly reduced as compared with the conventional case.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a binary signal transfer circuit of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the binary signal transfer circuit of the present invention.

FIG. 3 is a circuit diagram showing an example of a conventional binary signal transfer circuit.

[FIG. 4] A conventional two-way signal transfer capable of bi-directional simultaneous transmission
It is a block diagram which shows the example of a value signal transfer circuit.

[Explanation of symbols]

 1 simultaneous bidirectional binary signal transfer circuit 2, 5, 17, 18 AND circuit 3, 4, 6, 7 flip-flop circuit 14, 15, 41, 42 circuit 16, 43 transfer path 32, 411, 421 inverter 33, 34 Transistor 35 Capacitor 412, 422 Complementary MOS Circuit 413, 414, 423, 424 Comparator 415, 425 Selector

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H03K 17/16 J 9184-5J 19/0175

Claims (6)

[Claims] 1. A binary signal transfer circuit for transferring a binary signal through a simultaneous bidirectional binary signal transfer circuit for transferring a binary signal through a transmission / reception common transfer path, wherein an input signal supplied from the outside is When the signal is invalid, the first of the binary signals
A specific value signal is output, and the input signal value is output when the input signal is a valid signal, the output signal from the first signal output means is the simultaneous bidirectional binary value. 2 to supply to a signal transfer circuit
Value signal transfer circuit. 2. The first signal output means is constituted by a logical product circuit, and outputs a logical product of an input signal and a first identification signal supplied from the outside which indicates whether the input signal is valid or invalid. 2. The binary signal transfer circuit according to claim 1, which is characterized in that. 3. The first signal output means is constituted by a logical sum circuit, and outputs a logical sum of an input signal and an externally supplied first identification signal indicating whether the input signal is valid or invalid. 2. The binary signal transfer circuit according to claim 1, which is characterized in that. 4. A simultaneous bidirectional binary signal which outputs a first specific value signal in a binary signal when a test is performed by the scan path and outputs a signal value from the first signal output means otherwise. 2. The binary signal transfer circuit according to claim 1, further comprising second signal output means for supplying the transfer circuit. 5. The second signal output means is composed of a logical product circuit and the logical product of the signal value from the first signal output means and a second identification signal supplied from the outside indicating the presence or absence of a scan path test. 5. The binary signal transfer circuit according to claim 4, wherein the binary signal transfer circuit outputs. 6. The second signal output means is constituted by a logical sum circuit and the logical sum of the signal value from the first signal output means and a second identification signal supplied from outside indicating the presence or absence of a scan path test. 5. The binary signal transfer circuit according to claim 4, wherein the binary signal transfer circuit outputs.