JPH0727343B2 - Video memory - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a video memory suitable for delaying or holding a digitized video signal for a predetermined period.

[Background of the Invention]

Conventionally, a general-purpose dynamic random access memory has been used as a video memory that delays or holds a digitized video signal for a predetermined period. This is "Nikkei Electronics" published by Nikkei Inc. February 11, 1985.
Japanese issue, p232-234, "Field memory using standard dynamic RAM". This is because the cost per bit of the dynamic RAM is low, but since the cycle time of the memory is long, parallel processing using the memories in parallel is required for real-time processing of video signals. However, as the memory capacity per chip increases to 256K bits and 1M bits, the utilization rate of the memory deteriorates when the conventional parallel processing method is used. Therefore, recently, Nikkei Electronics, February 11, 1985, P219-239, “TV and VT” published by Nikkei Inc.
As mentioned in "R dedicated field memory 320 row x 700 column image-only serial input / output dynamic memory", a memory designed for high speed by devising video data serially was devised. Has been done. Mainly like this,
There is a growing demand for a video memory that is easy to use and has multiple functions for the purpose of video signal processing.

[Object of the Invention]

An object of the present invention is to provide a video memory capable of high-speed input / output and suitable for video signal processing.

[Outline of Invention]

An m-bit first register capable of serially inputting data is provided, the contents of the first register are transferred to the memory cell array at one time, and the data is input from the memory cell array while the data is being input to the first register. By reading out m bits of data, high-speed input / output of data in real time is possible. Further, a second register for m bits for serially inputting data is provided, and the data in the first register is selected by the data in the second register and transferred to the memory cell array, thereby realizing the bit mask function. To be realized.

Example of Invention

FIG. 1 shows an embodiment of the present invention. 1 is a memory cell array having n rows and m columns and a capacity of about 1 field or 1 frame, 2 is a first register that can input serial data, 3 is a second register that can also input serial data, and 4 is a first register
Transfer means for selectively transferring the data of the register 2 to the memory cell array 1, 5 is a data input terminal to the second register 3, 6 is a data input terminal to the first register 2, 7 is a timing and address controller, and 8 is First reference signal input terminal, 9 is second reference signal input terminal, 10 is clock input terminal,
11a to 11m are AND gates, 12a to 12m are switch gates by MOS transistors, 13 is an output buffer for serially outputting data (m bits) for one row of the memory cell array 1, 1
4 is a data output terminal. Here, the memory cell array is configured such that one row corresponds to one horizontal scanning period of a television signal and the number of rows is almost equal to the number of scanning lines.

The timing chart is shown in FIG. 2 to explain the operation.
In FIG. 2, (1) is the digitized video signal data D ₁ input from the input terminal 6, (2) is the bit mask data D ₂ input from the input terminal 5, and (3) is the video signal. The write clocks P ₁ and (4) for fetching the data D ₁ and the bit mask data D ₂ into the first register 2 and the second register 3, respectively, give the timing for transferring the data in the first register 2 to the memory cell array 1. The pulses P ₂ , (5) are read clocks P ₄ , which output any one row of the memory cell array 1 in series, and (6) are the read data D ₃ . That is, the following three operations are performed during the horizontal scanning period.

(1) The serial data D ₁ of the video signal digitized at the timing of the clock P ₁ is written in the first register.

(2) Write the bit mask data D ₂ input in series at the timing of clock P ₁ to the second register.

(3) Data of any one row in the memory cell array 1 is serially read at the timing of clock P ₄ .

Next, the following operations are performed during the blanking period. The data in the first register is selectively and simultaneously transferred through the switch gate 12 which is opened / closed by the data of each bit of the second register 3 and the product signal of the transfer pulse P ₂ (output of the AND gate 11). 1 is transferred to any one line. That is, the bit data in the second register is low (zero).
If so, the switch gate 12 is turned off, the data of the corresponding bit of the first register is not transferred, and the memory cell 1
The corresponding data in is saved. On the contrary, if the bit data in the second register is high (1), the switch gate 12 is turned on while the transfer pulse P ₂ is high, and the corresponding data in the first register is stored in the memory cell array 1. Data is transferred and rewritten. As described above, in this embodiment, the video signal can be input / output in real time, and the data can be rewritten for each bit or the previous data can be stored.

When a dynamic memory is used as the memory, the refresh operation can be performed by utilizing a part of the blanking period.

As one of the forms of the output buffer 13, an m-bit output register is provided as in the input section, and any one row of data is transferred from the memory cell array 1 to the output register in the retrace line period, and in the scanning period. There is a configuration to read in series. As another form, a static column system as well known as a general-purpose memory may be used.

Timing and addressing pulses are generated by the timing and address controller 7. In this case, examples of the reference signals input from the input terminals 8 to 10 are a vertical synchronizing signal, a horizontal synchronizing signal of the TV signal, and a clock signal having a frequency which is an integer multiple (usually 4 times is appropriate) of the color subcarrier frequency. Is appropriate. However, it is not limited to this.

FIG. 3 shows another embodiment. Blocks having the same reference numerals as in FIG. 1 have the same functions. The difference from FIG. 1 is that four bits are provided in parallel for data input. Therefore, the memory cell array 1, the first register 2, the transfer means 4, the data input terminal 6, the output buffer 13 and the data output terminal 14
4 are provided as a to d (subscripts), respectively. However, the number of the second register 3, the data input terminal 5, and the timing & address controller 7 may be one.

FIG. 4 shows another embodiment. Blocks having the same reference numerals as in FIG. 1 have the same functions. 1A has the same number of rows as the number of scanning lines of the TV and the number of columns equals 1/4 of one horizontal period of the TV signal, and the same applies to the memory cell arrays 1B, 1C and 1D, which are equivalent to almost one field from 1A to 1D. To do. 2A has the same number of bits as 1/4 of one horizontal period, and the same applies to the first register and 2B which can input serial data. 3A is a second register in which the number of bits is equal to 1/4 of one horizontal period and serial data can be input. The same applies to 3B. 4A is a transfer means having a switch gate whose number is equal to the number of bits in the first register.
Is also the same. Reference numeral 15 is a sense amplifier for reading an arbitrary row of the memory cell arrays 1A and 1B, and 16 is a sense amplifier for reading an arbitrary row of the memory cell arrays 1C and 1D.

The timing chart is shown in FIG. 5 to explain the operation.
(1) indicates the time, (2) indicates the data D ₁ input from the input terminal 6, (3) indicates the type of the first register to which the data D ₁ is input, and (4) indicates the input terminal 5 The type of the second register to which the bit mask data input from is input is shown. (5) is a transfer pulse P2 that gives the timing of transferring the data of the first register 2A to the memory cell array 1.
A, (6) is a transfer pulse P2B, which gives a timing for transferring the data of the first register 2B to the memory cell array 1.
(7) shows the type of the memory cell array to which the data of the first register is transferred, and (8) shows the operation period of the sense amplifier 15, that is, any one row of the memory cell array 1A or 1B is read to the bit line. Period, (9) shows the period during which the sense amplifier 16 is operating, and (10) shows the output terminal.
Memory cell array 1 from which data is read serially from 14
Indicates the type of. In period I, the following four operations are performed.

(1) The data D ₁ and D ₂ from the data input terminals 6 and 5 are written in the first register 2A and the second register 3A, respectively.

(2) Of the data in the first register 2B, the second register 3B
Data that was not masked by the contents of the memory cell
It is transferred and written in any one row of 1D.

(3) Memory cell array 1A reproduced by the sense amplifier 15
Any one of the rows is read out from the output terminal 14 in series.

(4) After the operations of (2) are completed, the sense amplifier 16 starts reading an arbitrary row of the memory cell array 1C in preparation for the reading in the period II.

In period II, the following four operations are performed.

(1) The data D ₁ and D ₂ from the data input terminals 6 and 5 are written in the first register 2B and the second register 3B, respectively.

(2) Of the data in the first register 2A, the second register 3A
Data that is not masked by the contents of the memory cell
Transferred to any one line of 1A.

(3) Memory cell array 1C reproduced by the sense amplifier 16
Any one of the rows is read out from the output terminal 14 in series.

(4) After the operations of (2) are completed, the sense amplifier 15 starts reading an arbitrary row in the memory cell array 1B.

Hereinafter, in periods III to VIII, almost the same operation is repeated so that it can be easily inferred from the figure. This way,
Data during the blanking period can be written, held, and delayed. In the example of FIG. 4, there is a period in which one of the sense amplifiers 15 and 16 is not operating, so this period can be applied to the refresh operation period of the memory cell. Therefore, it is suitable for reading the output by the static column method.

In FIG. 4, the data input is shown by one bit, but it can be easily inferred that multiple bits can be input as in the embodiment of FIG.

The number of bits of the first register 2 and the second register 3 is set to a period corresponding to the horizontal scanning period in the example of FIG. 1 and 1/4 of the horizontal period in the example of FIG. It is an embodiment, and the number of bits is not limited to these two examples.

FIG. 6 shows a concrete circuit for realizing the embodiment shown in FIG. The MOS transistor 17 for any one bit and the inverters 18, 19 constitute a bit register 60 for indicating any one bit of the second register 3 of FIG. 1, for example. MOS transistors 21 and 22, and inverters 23 and 24
Thus, for example, a bit register 61 showing any one bit of the first register in FIG. 1 is constructed. NOR circuit 20 and MOS
The transistors 25 and 26 constitute, for example, any one of the transfer means 4 shown in FIG. One MO (shown by dashed line 62)
S transistor 27,29,31,33 and one capacitor 28,30,3
A combination of 2,34 memory cells (27,2
8), (29,30), (31,32), (33,34). The inverters 35 and 36 and the MOS transistor 37 form a sense amplifier. (Indicated by a broken line 63) 38 and 39 are MOS transistors. 40 is, for example, 1 of the second register 3 in FIG.
The input terminal of the bit selection signal for selecting the bit, 41 is also the input terminal of the bit selection signal of the first register 2, and 42 is
The data input terminal 43 of the second register is a transfer pulse input terminal that gives a timing for transferring the data of the first register to the memory cell array 1, and 44 is an inverter. 45
Is a data input terminal of the first register, and 46 is an inverter. 47 to 50 are arbitrary four word lines. Reference numeral 51 denotes a sense amplifier control signal line, which controls the operating state and non-operating state of the sense amplifier 63 by this control signal. The non-operating state is, for example, the inverter 3
Inverter 35,3 by turning off the power supply of 5,36
It is to put the input / output part of 6 in the floating state. 52 is a control signal line for opening and closing the MOS transistor 37, 53 and 54 are a pair of bit lines, 55 and 56 are a pair of data output lines, 57 is an output bit selection signal input terminal, 58
Is a buffer for converting a pair of output signals into a single logic level signal for output, and 59 is a data output terminal. Next, the timing chart is shown in FIG. 7 and the operation of FIG. 6 will be described. (A) is a bit selection signal input from the input terminal 40, (b) is data input from the input terminal 42, (c) is a bit selection signal input from the input terminal 41, (d) is Data input from the input terminal 45, (e)
Is the output of the bit register 60, (f) is the output of the bit register 61, the output data of the inverter 23, and (g) is
The signal on the control signal line 52 for opening and closing the MOS transistor 37, (h) is the potential of the pair of bit lines 53, 54, (i)
Is a transfer pulse which gives a timing for transferring the data of the first register to the memory cell array, which is input from the input terminal 43, (j) is the output of the MOR circuit 20, (k) the selection signal of the word line 47, (l) Is a signal on the control signal line 51 that activates the sense amplifier 63.

At time t ₁ , the data serially input from the input terminal 42 is latched to the bit register 60 of the second register at the timing of the bit selection signal input from the input terminal 40. At this time, the output of the bit register 60 is inverted and becomes low level in this example. Similarly, the data serially input from the input terminal 45 is latched to the bit register 61 of the first register at the timing of the bit selection signal input from the input terminal 41. At this time, the output of the bit register 61 is high on the output side of the inverter 23 and low on the output side of the inverter 24. By the above operation, the data is latched to any bit of the second register and the first register. Next, the operation of transferring the data in the first register to the memory cell array will be described. At time t ₂ , a high level signal is input from the input terminal 52, the MOS transistor 37 is turned on, and the bit lines 53 and 54 are short-circuited. Immediately before a short circuit, one pair of bit lines 53, 54 is high and the other is low.
The potentials of 53 and 54 are almost half of the power supply voltage. Then the time
When a transfer pulse that gives a timing for transferring the data of the first register to the memory cell array is input from the input terminal 43 to t ₃ , the output of the NOR circuit 20 becomes high, the MOS transistor 25, 26 is turned on, and the bit register is turned on. The contents of 61 are output to the pair of bit lines 53 and 54. At almost the same timing as the transfer pulse, any word line (here, word line 47
And) goes high and selects memory capacitor 28. At time t ₄ , the control signal of the sense amplifier 63 is input, the sense amplifier 63 is activated, and the bit line 5
Amplify the potential difference between 3, 54 and set bit line 53 high and bit line 54
Is fixed to low. This is the V of the MOS transistors 25 and 26.
It is more effective when the Z line 53 does not rise to the power supply voltage due to the influence of _TH . Then at time t ₅ , word line 47
Goes low, completing the writing of data to the capacitor 28. The above explanation is for the bit register of the second register.
The case where the high data from the input terminal 42 is latched is described in 60.

Next, the case where the low data from the input terminal 42 is latched will be described. FIG. 8 shows a timing chart in this case. (A) is a control signal of the control signal line 52 for opening / closing the MOS transistor 37, (b) is a bit line 53, 5
4 potential, (c) is the selection signal of the word line 47, (d) is
This is a signal on the control signal line 51 that activates the sense amplifier 63. In this case, the output of the bit register 60 is high, so the output of the NOR circuit 20 is always low. Therefore, the MOS transistors 25 and 26 are always off. Times t ₂ to t ₄ are the same as described above. Word line 47 at time t ₃
Becomes high. Here, if a high level is written in the capacitor 28, the potential of the bit line 53 slightly rises, and a slight potential difference occurs between the bit lines 53 and 54. This potential difference is due to the capacitance value of the capacitor 28 and the bit line.
It is determined by the relationship between the parasitic capacitance and stray capacitance of 53. At time t ₄ , when the sense amplifier control signal line 51 becomes high and the sense amplifier 63 becomes active, the potential difference between the bit lines 53 and 54 is amplified, and the bit line 53 becomes high and the bit line 54 becomes low. . At time t ₅ , the word line 47 goes low and the capacitor 28 retains the original data. In addition, if capacity 28
If the word line 47 becomes high at time t ₃ when a low level is written to the bit line 53, the bit line 53 is slightly lowered, and the slight potential difference between the bit lines 53 and 54 is amplified by the sense amplifier 63 and the word When the line 47 goes low, the capacitor 28 holds a low level. As described above, it is possible to control whether the content of the corresponding bit register 62 of the first register is transferred to the memory cell array or not depending on the data content latched in the arbitrary bit register 60 of the second register. The signal timings shown in FIGS. 7 and 8 are examples, and the phases, pulse widths, etc. are not limited in this figure. Further, the bit selection signals input from the input terminals 40 and 41 may be the same, so that they can be common. It is common in FIG.

Next, the read operation will be described. FIG. 9 shows a timing chart. (A) is a control signal of the control signal line 52 for opening and closing the MOS transistor 37, (b) is the potential of the bit lines 53 and 54, (c) is the signal of the word line 47, (d).
Is a control signal line that controls the sense amplifier 63
The signal of 51, (e) shows the read bit selection signal inputted from the input terminal 57, and (f) shows the potential of the output lines 55, 56.

At time t ₁ , control signal line 52 goes high, shorting bit lines 53, 54. At time t ₂ , word line 47 goes high and the data on capacitor 28 is read out on bit line 53. Here, if the high level is held in the capacitor 28, the potential of the bit line 53 rises slightly and a potential difference occurs between the bit lines 53 and 54. At time t _3, the control signal line 51 is connexion such high results in the sense amplifier 63 is the operating state, is amplified potential difference between bit lines 53 and 54, bit line 53 is high, bit line 54 is low. At time t ₄ , word line 47 goes low and capacitor 28 retains the original data. At time t ₅ , the read bit selection signal is input from the input terminal 57 and the MOS transistors 38 and 39 are turned on.
Then, the data on the bit lines 53 and 54 are output to the output lines 55 and 56, respectively. The potential of the output lines 55 and 56 before t ₅ has a value determined by the information of the bit read immediately before, but is not related to the reading of the bit. The data on the output lines 55 and 56 are converted into a single logic level by the buffer 58 and output from the output terminal 59.

FIG. 10 shows another embodiment. Similar to FIG. 6, FIG. 10 shows an arbitrary one bit corresponding to the second register, the first register and the transfer means. However, memory cells,
Sense amplifiers, output lines, etc. are not shown. 64 is a capacitor and 65 is an AND circuit. Elements, blocks, and lines having the same reference numerals as in FIG. 6 have the same function.
The difference from FIG. 6 is that an arbitrary bit register 60 of the second register is composed of a MOS transistor 17 and a capacitor 64. In this configuration, if a boost signal (for example, 7v) is used as the bit selection signal input from the input terminal 40, the MO
The influence of V _TH of the S transistor 17 can be suppressed. The operation of the other blocks is basically the same as in FIG.

FIG. 11 shows an essential part of another embodiment of the present invention. In the figure, 66a to 66m are switches, which switch between the positive phase output and the inverted output of each bit output of the second register 3. 67 is an input terminal for a control signal for controlling the switches 66a to 66m. Those having the same numbers as in FIGS. 1 and 4 have the same functions. The feature of the embodiment shown in FIG. 11 is that the same effect as instantaneously inverting the contents of the second register 3 can be obtained by the control signal input from the input terminal 67. The operation of the embodiment shown in FIG. 11 will be described with reference to FIG. In FIG. 12, the same numbers as those in FIGS. 1 and 11 have the same functions. In FIG. 12 (a), data of video signals A and B is input to the first register 2, and data is input to the second register 3 so that the information of the video signal A can be selectively written in the memory cell array 1. is doing. Next, in FIG. 2B, the information in the first register 2 is written in the memory cell array 1. At this time, a control signal is previously added to the input terminal 67 so that only the information of the video signal A can be written in the memory cell array 1 corresponding to the data stored in the second register 3.
Next, in FIG. 7C, the control signal of the input terminal 67 can be inverted, and only the information of the video signal B can be written in the memory cell array 1 this time. At this time, if the row selection address of the memory cell array is changed in advance, it can be easily understood that the video signals A and B can be continuously written in different rows as shown in (c). The function shown in FIG. 12 in the embodiment of FIG. 11 is very effective, for example, in an application example in which a television screen is vertically divided to display video signals A and B, respectively. Video signals that are out of sync with each other,
When writing to a video memory that performs serial read-in / read-out, use a frame synchronizer that uses a field memory or a frame memory to operate the main video signal (the video memory and the display system operate in synchronization with this video signal. It is necessary to match the sub video signal (this video signal does not match the operation of the display system and the video memory with the sync signal). However, in the configuration of FIG. 11, only the horizontal synchronization needs to be adjusted, and the horizontal synchronization phase adjustment can be realized by one or two line memories.

Needless to say, in the embodiment of FIG. 11, if the control signal of the input terminal 67 is fixed, the same operation as that of the embodiment shown in FIGS. 1 to 10 can be performed.

FIG. 13 shows another embodiment of the present invention. Figure 13 is the first
Register, second register, any one corresponding to transfer means
Bits are illustrated. Memory cells, sense amplifiers, output lines, etc. are not shown. In the figure, 68
Indicated by 69 and 69 are inverters, and 70 through 77 are transfer gates, and elements, lines, and blocks having the same reference numerals as in FIG. 6 have the same function. In this embodiment, writing to the second register 60 is performed using both the signal from the input terminal 42 and its inverted signal. In the transfer means 62, the transfer gates 74 and 76 or
This is different from the example of FIG. 6 or 10 in that it is configured by connecting 75 and 77 in series. Inverter 69
The transfer gates 72 and 73 also function as switches that switch the output of the second register 60 in response to the control signal from the input terminal 67. This is switch 66a in FIG.
It corresponds to ~ 66 m, and it can be easily guessed that this embodiment can operate as shown in FIG.

FIG. 14 shows another embodiment of the present invention. FIG. 14 shows an arbitrary one bit corresponding to the first register, the second register and the transfer means. In the figure, 78 is
It is a transfer gate of the PMOS and corresponds to the transfer gate 73 in FIG. 79 and 80 are NOR
Gates 81 and 82 are AND gates. In FIG. 14, the first
Those having the same reference numerals as those in FIG. 3 have the same function. 14th
The figure shows that any bit 60 of the second register consists of NOR gates 79 and 80, and that AND gates 81 and 82 are used for write control instead of transfer gates, and that transfer gate 78 is an inverter 69 because it is a PMOS. The configuration is the same as that shown in FIG. 13 except that is unnecessary, and the same operation can be performed.

FIG. 15 shows another embodiment of the present invention. FIG. 15 shows an arbitrary one bit corresponding to the first register, the second register and the transfer means. In the figure, 83 is an exclusive OR gate, and 84 and 85 are tri-state buffers. In FIG. 15, elements, blocks and the like having the same reference numerals as those in FIGS. 6 and 10 have the same functions.

In the present embodiment, an exclusive OR83 is used instead of selecting the output of the second register 60, and the tristate buffer 84, 84 as means for transmitting the output of the first register 61 to the bit lines 53, 54. Although it differs from Fig. 13 in that the 85 is used, it can be easily inferred that the same operation can be performed by inputting the control signal with the same timing from each input terminal.

FIG. 16 shows another embodiment. Blocks having the same reference numerals as in FIG. 1 have the same functions. 86 is the first register 2
Is a third register that latches all the data at the same transfer timing, and has the same number of bits as the first register 2, m bits. 87 is a fourth register that latches all the data in the second register 3 at the same transfer timing, and the number of bits is m
Is a bit. 88 is a continuous m in the memory cell array 1
The output first register 89 for latching bit data at the same transfer timing is an output second register 89 for latching the data in the output first register 88 at the same transfer timing and outputting the data in series. The configuration of the memory cell array 1 is
The number of columns is an integer multiple of the number m of bits of the first register 2, and the total capacity is about one field. The output P ₃ of the timing & address controller 7 selects a row of the memory cell array 1, and the output P ₄ selects a column in units of m bits. P ₇ is a pulse giving a timing for transferring continuous m-bit data of the memory cell array 1 to the output first register 88,
P ₈ outputs the data of the output first register 88 to the second register 89
It is a pulse that gives the timing to transfer to.

The operation will be described with reference to the timing chart shown in FIG. First
In FIG. 17, (1) is the first register 2 from the input terminal 6.
Input data to the second register 3 from the input terminal 5, (3), (4), (5),
(6), (7) and (8) are outputs P ₁ , P ₅ , P ₂ , P ₇ , P ₈ from the timing & address controller 7, respectively.
P is _4. (9) is the output data D ₃ from the output second register 89.

In period 1, the following five operations are performed at the timing shown in FIG.

1) The data D ₁ input from the input terminal 6 is the m-bit data that continues at the timing of the pulse P ₁ in the first register 2
All the m-bit data of the first register 2 are transferred to the third register 86 at the timing of the pulse P ₅ .

2) The data D ₂ input from the input terminal 5 is continuous in the timing of the pulse P _{1 and} the m-bit data is the second register 3
Is taken into the second register 3 at the timing of pulse P _5.
All the m bits of data are transferred to the fourth register 87.

3) All the m-bit data of the output first register 88 are transferred to the output second register 89 at the timing of the pulse P ₈ , and the m-bit data are output in series at the timing of the pulse P ₄ .

4) Transfer consecutive m-bit data in the memory cell array 1 designated by the row selection signal P ₃ and the column selection signal P ₆ to the output first register 88 at the timing of the pulse P ₇ .

5) at the timing of the pulse P _2, data not subjected the mask data of the fourth register 87 among the data of m bits of the third register 86, the row selection signal P _3, the column selection signal P ₆
Are transferred to the area in the memory cell array 1 designated by.

The same operation is performed in period II and period III.

In the above description, it was explained that the data D ₁ from the input terminal 6 was serially taken in the first register 2 for m bits and transferred to the third register 86 at the timing of the pulse P ₅ , but the timing described below may also be used.

(M-1) -bit data is loaded into the first register 2, and the next m-th bit data is already loaded (m
-1) Directly transfer to the third register 86 at the same timing as the bit data. In this case, the number of bits of the first register 2 can be reduced by 1 bit. This operation is also possible for transfer from the second register 3 to the fourth register 87. Further, it can be easily inferred that the same can be applied to the transfer from the output first register 88 to the output second register 89. Further, although FIG. 16 has been described with a 1-bit input, it is obvious that a multi-bit input may be used as in the example of FIGS. 1 and 3.

FIG. 18 shows an embodiment of the present invention. In this example, when the number of columns of the memory cell array 1 is N times the number of bits m of the first register 2 (N is an integer), the input part to the output part corresponding to 1 bit of the first register 2 is shown. There is. However,
In this example, two memory cells are shown in one bit line pair, and other cells are omitted. Block elements having the same reference numerals as in FIGS. 6 and 14 have the same function. 91 is the third data of the first register 2 and the second register 3 respectively.
The signal lines 92, 93, 94 and 95 of the signal P ₅ which gives the timing of transferring to the register 86 and the fourth register 87 are MOS transistors and have a transfer gate function. 96 and 97 are inverters, and 96 and 97 form a 1-bit latch of the fourth register 87. 98,99 is an inverter, 98,99 is the third register
Configure a 1-bit latch for 86. 100A to 100N are MOS transistors, 101A to 101N are capacitors, and the MOS transistor 100 and the capacitor 101 form a 1-bit memory cell in the memory cell array 1. 102A to 102N are MOS transistors, and 103A to 103N are capacitors. MOS transistor
A MOS transistor 100 has the same function as the capacitor 102, and a capacitor 103 has the same function as the capacitor 101. 105A _{1 to} 105N ₂ are MOS transistors having a transfer gate function. 106A ₁ and 106
A ₂ is a pair of bit lines, which are the same from 106B ₁ and 106B _{2 to} 106N ₁ and 106N ₂ . The reference numerals 104A to 104N denote N bit line pairs 106A to 106N each of which is an arbitrary 1-bit output line of the third register 86.
It is a signal line for selecting which of the above is connected. This can be obtained by decoding the column address data.
This allows random access in the column direction in units of m bits.

Reference numeral 107 is a signal that gives timing for transferring continuous m data in the memory cell array 1 to the first output register 88.
Signal lines 108 and 109 of P ₇ are MOS transistors having a transfer gate function. 110 and 111 are inverters
The 0,111 constitutes a 1-bit latch of the output first register 88. 112 indicates the data of the output first register 88 and outputs the second
Signal lines 113 and 114 for the pulse P ₈ which give the timing of transfer to the register 89 are MOS transistors having a transfer gate function. Reference numerals 115 and 116 denote inverters, and 115 and 116 form a latch for one bit of the output second register 89.
Inverters 117 and 118 have a buffer function. 119,120
Is a MOS transistor having a transfer gate function. 121 and 122 are output line pairs.

In the configuration of FIG. 18, the number of bits of the first register 2 and the second register 3 is 1 / N, so that the first register 2 and the second register 3 are arranged in parallel in the IC layout as shown in the figure. Easy to place.

Although the first register 2, the second register 3, and the output second register 89 are shown in FIG. 18 as data selector type latches, they may be constituted by shift registers.

In the present invention, an m-bit first register that can input serial data and an m-bit second register that can input serial data are provided, and one transfer pulse and a logical signal of each of the m-bit data in the second register. Among the m-bit data in the first register, any data corresponding to the data in the second register is transferred to the memory cell array via the transfer means operating in 1. This enables the bit mask function.

Further, since the input data is fetched into the m-bit first register, high-speed writing is possible, and during the period when the data is fetched into the first register, writing does not always monopolize the memory cell array, so reading is performed at high speed. It is possible.

〔The invention's effect〕

According to the present invention, it is possible to realize a video memory capable of inputting and outputting a digitized video signal in real time and having a mask function in bit units.

[Brief description of drawings]

1 is a block diagram of an embodiment of the present invention, FIG. 2 is a timing chart for explaining FIG. 1, FIG. 3 is a block diagram of another embodiment of the present invention, and FIG. FIG. 5 is a block diagram of yet another embodiment of the present invention, FIG. 5 is a timing chart for explaining FIG. 4, and FIG. 6 is a block diagram of still another embodiment of the present invention, FIG. 7, FIG. FIG. 9 is a timing chart for explaining the embodiment of FIG. 6, FIG. 10 is a configuration diagram of still another embodiment of the present invention, and FIG. 11 is a configuration of yet another embodiment of the present invention. FIG. 12 is a schematic diagram for explaining the operation of the embodiment of FIG. 11, and FIGS. 13, 14, and 15 are configuration diagrams of still another embodiment of the present invention. FIG. 16 is a configuration diagram showing an embodiment of the present invention, FIG. 17 is a timing chart of the embodiment shown in FIG. 17, and FIG. 18 is a configuration diagram of another embodiment of the present invention. 1 ... Memory cell array, 2 ... First register 3, ... Second register, 4 ... Transfer means 7 ... Timing address controller 14 ... Output buffer

Front page continued (72) Inventor Ichio Nakagawa, 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Home Appliances Research Laboratory, Hitachi, Ltd. (72) Inventor Shigeru Hirahata, 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Inside the Hitachi Home Appliances Research Laboratories (72) Inventor Noboru Kojima 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock Company Inside the Hitachi Home Appliances Research Laboratories (72) Inventor Nao Horiuchi 292 Yoshida-cho, Totsuka-ku Yokohama-shi, Kanagawa Ceremony Company Hitachi, Ltd. Home Appliances Research Laboratory (72) Inventor Haruki Wakimoto 1450, Josuihonmachi, Kodaira-shi, Tokyo Hitachi, Ltd. Musashi Factory (72) Inventor, Yasuki Yamaguchi 1450, Josuihoncho, Kodaira-shi, Tokyo Hitachi, Ltd. In Device Development Center (56) References JP 59-131979 (JP, A) JP 59-180871 (JP, A) JP 60-72020 (JP, A)

Claims (1)

[Claims] 1. A memory cell array, an m-bit first register that can input serial data, an m-bit second register that can input serial data from one external terminal of an LSI, and a transfer pulse generation circuit. Any one of the first registers through the m number of transfer means having a logical signal of the output signal of the transfer pulse generation circuit and the m number of respective data in the second register. A video memory, which transfers data to the memory cell array.