JPH07264436A - Video signal processing circuit and liquid crystal display device using it - Google Patents

Abstract

PURPOSE:To provide a video signal processing circuit in which deterioration in display quality is less even when a received field cannot be discriminated. CONSTITUTION:An EXOR 42 receives a current field signal A and a field signal A of one preceding field latched by a latch circuit 41. An output signal of the EXOR 42 is latched by a latch circuit 43 and outputted to a control terminal of a multiplexer 45 as a field confirmation signal C. When the field confirmation signal C is at a high level, that is, the field is normally discriminated, the multiplexer 45 provides an output of the received field signal A as it is and when the field confirmation signal C is at a low level, the multiplexer 45 provides an output of a pseudo field signal whose polarity is inverted synchronously with vertical synchronizing signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit for TV, video and the like and a liquid crystal display device using the same.

[0002]

2. Description of the Related Art Some commercially available video software and laser disk software output a video signal at a timing out of standard. Also, some VTRs and LD players output a signal at a timing out of the standard at the time of fast-forwarding, rewinding, or pausing.
When such a signal is input to a video processing circuit such as a TV, the field may not be discriminated and the image may not be displayed correctly. Also, if the field cannot be determined,
Since the display is fixed in the even-numbered field or the odd-numbered field and the display device is driven by direct current, it adversely affects a display element such as LCD that needs alternating drive.

First, the case of displaying a video signal on a CRT will be described. FIG. 11 is a diagram showing a video signal waveform. The pulse width of the vertical blanking period of the video signal is different between the even field and the odd field, and it is possible to distinguish the even field and the odd field from this difference in pulse width.

There are two types of methods for displaying a video signal on a CRT: interlaced (interlaced) scanning and non-interlaced scanning. The interlaced scanning is a method of displaying an image of one frame by displaying a solid line portion in an odd field and a broken line portion in an even field of the video signal as shown in FIG.

A case where a video signal is displayed on a liquid crystal display device by interlaced scanning will be described. Figure 1
3 is a block diagram of a drive circuit of the liquid crystal display device. The video signal processing circuit 10 includes a Y / C separation circuit 11, a color signal demodulation circuit 12, a 1H delay circuit 13, a matrix circuit 14, a sync separation circuit 15, and a field discrimination circuit 16. The video signal input to the video signal processing circuit 10 is supplied to the luminance signal Y in the Y / C separation circuit 11.
And a color signal C are separated, and the color signal is further converted in the color signal demodulation circuit 12 into three types of color difference signals of RY, GY, and BY. Then, those color difference signals are 1
The luminance signal delayed by one horizontal period in the H circuit 13 and the matrix circuit 14 are arithmetically processed and converted into color signals of three primary colors of R, G, and B.

On the other hand, the luminance signal is separated into a horizontal synchronizing signal and a vertical synchronizing signal in the sync separating circuit 15, and a field signal is created from the horizontal synchronizing signal and the vertical synchronizing signal in the field determining circuit 16. Then, in the timing generating circuit 17, a timing signal necessary for displaying on the liquid crystal display device is created from the horizontal synchronizing signal, the vertical synchronizing signal, and the field signal, and is output to the RGB processing circuit 18. The RGB processing circuit 18 includes R, G,
The color signals of the three primary colors B are subjected to processing such as amplification, inversion, and correction, and the signals are output to a liquid crystal driving IC (not shown) according to the timing signals output from the timing generation circuit 17.

By the way, as a driving method for displaying a video signal on a liquid crystal display (LCD), for example, FIG.
As shown in FIG. 4, a method of performing interlaced scanning in which odd fields and even fields are alternately displayed as in the case of CRT display (this is called a first driving method), and 2 in a horizontal period as shown in FIG. There is a method of displaying lines line by line, and displaying them by shifting one line between an even field and an odd field (this is called a second driving method). In addition, FIG.
A method of converting an analog video signal into a digital signal, synthesizing data of two fields and storing it in a memory, and displaying the data in the memory in order (referred to as a third driving method) is shown in FIG. is there. 14 to 16
1-2, 1-3 ... is the second line of the odd field,
The third line is shown, and 2-2, 2-3, ... Show the second line, the third line, ... Of the even field.

When driving the liquid crystal display device, it is necessary to perform AC driving in order to prevent deterioration of the liquid crystal. Therefore, for example, as shown in FIGS. 17A and 17B, the polarity is inverted for each frame to drive the liquid crystal display device. Specifically, as shown in FIG. 17A, in the display of the odd field of the Nth frame, adjacent dots on the same horizontal line are driven to have different polarities, and further each horizontal line is driven to have a different polarity. Each dot is similarly driven in the display of the even field. Then, in the next display of the (N + 1) th frame, each line of each field is driven to a polarity different from the previous polarity.

FIG. 18 is a diagram showing a main part of a conventional drive circuit for AC driving a liquid crystal display device. The timing generation circuit 17 includes a latch circuit 21 whose output is inverted in synchronization with a field signal, a latch circuit 22 whose output is inverted in synchronization with a horizontal synchronizing signal, and an exclusive logic of output signals of these latch circuits 21 and 22. A polarity inversion signal generation circuit composed of an exclusive OR gate (hereinafter referred to as EXOR) 23 for summing, and a driver (not shown) for generating a signal for controlling the liquid crystal driver from horizontal synchronization, vertical synchronization and field signals. It is composed of a control signal generation circuit. In the driver control signal generation circuit, by the field signal,
It also controls whether the video signal is applied to the even rows or the odd rows of the liquid crystal panel.

The timing generating circuit 18 includes an inverting circuit 25 for inverting and outputting a video signal, and a video signal and inverting circuit 2.
Multiplexer 2 for selecting one of the video signals inverted in step 5 and outputting it to liquid crystal driving source drivers 26, 27
It is composed of 4 and.

The liquid crystal display device comprises a liquid crystal panel 29, a gate driver 28 which supplies a drive voltage to a common line of the liquid crystal panel 29, and source drivers 26 and 27 which supply a drive voltage to segment lines. .

Now, the operation of the above-mentioned drive circuit when the liquid crystal display device is driven by the above-mentioned first drive method will be described. The latch circuit 21 outputs a frame signal whose polarity is inverted in synchronization with the frame, and the latch circuit 22 outputs a signal whose polarity is inverted in synchronization with the rising of the horizontal synchronization signal.

First, the case of displaying the Nth frame will be described. Now, assuming that the output signal of the latch circuit 21 is at the low level and the output signal of the latch circuit 22 is at the high level when displaying the first line of the odd field, at this time, the output signal of the EXOR 23 becomes at the high level. Therefore, the multiplexer 24 outputs the video signal to the upper source driver 26 with the same polarity, and outputs the video signal whose polarity is inverted by the inverting circuit 25 to the lower source driver 27.

Here, the source driver 26 on the upper side supplies a drive voltage to the dots in the odd columns of each horizontal line of the liquid crystal panel 29, and the source driver 27 on the lower side drives the dots of the even columns of each horizontal line. Since the voltage is supplied, 2
A drive voltage having the same polarity as the video signal is supplied to the odd-numbered columns of the line, and a drive voltage having the opposite polarity to the video signal is supplied to the even-numbered columns. Therefore, the positive drive voltage is supplied to the odd-numbered columns of the second line, and the negative drive voltage is supplied to the even-numbered columns.

When displaying the next line, the output signal of the latch circuit 22 changes to the low level in synchronization with the horizontal synchronizing signal, so that the output signal of the EXOR 23 becomes the low level and the multiplexer 24 causes the upper source driver 26 to operate. To the source driver 27 on the lower side and output the video signal with the same polarity. As a result, the odd-numbered and even-numbered columns of the second line are supplied with the drive voltage having the opposite polarity to the odd-numbered and even-numbered columns of the first line. Hereinafter, the drive voltage is similarly supplied to each line.

Next, when the first line of the even field is displayed, the output signal of the latch circuit 21 remains at the low level and the output signal of the latch circuit 22 becomes the high level, so that the output signal of the EXOR 23 is high. The level of the multiplexer 24 becomes higher than the level of the source driver 26 on the upper side.
To the source driver 27 on the lower side, and the video signal whose polarity has been changed is output.

When the next line is displayed, the output of the latch circuit 22 is inverted in synchronization with the horizontal synchronizing signal and its output signal changes to low level, so that the output signal of the EXOR 23 becomes low level. When the output signal of the EXOR 23 is at the low level, the multiplexer 24 outputs the video signal whose polarity is inverted to the upper source driver 26,
The video signal is output to the lower source driver 27 with the same polarity. As a result, the drive voltage having the opposite polarity to the odd and even columns of the second line of the even field is supplied to the odd and even columns of the first line.

Next, the case of displaying the (N + 1) th frame will be described. When the frame is switched, the output signal of the latch circuit 21 becomes high level, and when the first line of the odd field is displayed, the output signal of the latch circuit 22 becomes high level, so the output signal of the EXOR 23 becomes low level. Become. When the output signal of the EXOR 23 is at a low level, the multiplexer 24 outputs the video signal whose polarity is inverted to the upper source driver 26 and outputs the video signal to the lower source driver 27 with the same polarity.

As a result, the odd-numbered column of the first line of the odd-numbered field of the (N + 1) th frame has a driving voltage of the opposite polarity to the driving voltage supplied to the same column of the same line of the immediately preceding N-th frame. Is supplied to the even columns as well.
A drive voltage having the opposite polarity to the previous frame is supplied.
Similarly, when displaying an even field, a drive voltage having a polarity opposite to that of the drive voltage of the odd and even columns of the even field of the immediately preceding Nth frame is supplied.

As a result, as shown in FIG. 17, each dot of the liquid crystal display device is always supplied with a drive voltage having a polarity opposite to that of the drive voltage one frame before, and the liquid crystal display device is AC-driven.

[0021]

By the way, when the liquid crystal display device is driven by using the above-mentioned drive circuit, when the field can be normally discriminated by the field discriminating circuit 16, correct display can be performed. However, if the field cannot be discriminated for some reason, the video signal is displayed redundantly in the even field or the odd field.

19 and 20 show the display state when the field cannot be discriminated. FIG. 19 shows a display example when the field signal is fixed to the odd field. In this case, the even field data is displayed together with the line where the odd field data should be displayed, and every other line. Since only the display is performed, the display quality is significantly deteriorated. Similarly, FIG. 20 shows a display example when the field signal is fixed to the even field, and the data of the odd field is displayed together with the line on which the data of the even field is displayed. Since the display is not performed, the display quality is significantly deteriorated.

If the field cannot be discriminated, the latch circuit 21 of the timing generating circuit 17 shown in FIG.
Since the field signal input to the input terminal does not change, the polarity of the drive voltage does not reverse every frame. As a result, a DC voltage is applied as a driving voltage of the liquid crystal display device, which causes a problem that the liquid crystal deteriorates.

An object of the present invention is to provide a video signal processing circuit and a liquid crystal display device using the video signal processing circuit which can reduce deterioration of display quality even when a field cannot be determined. Another problem is to enable the liquid crystal to be driven by alternating current even when the field cannot be determined.

[0025]

FIG. 1 is a block diagram showing the principle of a video signal processing circuit according to the present invention. In the figure, the field signal output means 1 outputs a signal for distinguishing fields of a video signal composed of a plurality of fields.

The field confirmation means 2 confirms whether the field can be normally discriminated from the signal output from the field signal output means 1. Note that FIG. 1 shows an example of the configuration of the field confirmation means 2 when the field signal output means 1 outputs field signals having different polarities in the even field and the odd field.

In the figure, the field signal holding circuit 3
Holds the field signal one field before. The polarity discriminating circuit 4 is stored in the field signal holding circuit 1
It is determined whether or not the polarities of the field signal before the field and the current field signal are different.

The pseudo field signal generation circuit 5 generates a pseudo field signal whose polarity is inverted in synchronization with the vertical sync signal. When the polarity determination circuit 4 determines that the two field signals have different polarities, the selection circuit 6 selects and outputs the field signal output from the field signal output means 1, and the polarity determination circuit 4 outputs the two fields. When it is determined that the polarities of the signals are the same, the pseudo field signal generated by the pseudo field signal generation circuit 5 is selected and output. The pseudo field circuit 5 and the selection circuit 6 constitute a field signal output circuit.

[0029]

In the video signal processing circuit and the liquid crystal display device using the same according to the present invention, it is confirmed whether or not the field of the video signal can be normally discriminated. Create a pseudo field signal whose polarity is inverted in synchronization with the vertical sync signal,
By performing the display based on the pseudo field signal, it is possible to prevent the video signal from being fixedly displayed in one of the even field and the odd field and the display quality from being deteriorated. Further, even if the field signal cannot be discriminated, the even field and the odd field are alternately displayed by the pseudo field signal, so that it is possible to prevent the liquid crystal display device from being driven by direct current to deteriorate the liquid crystal. Also,
When the field cannot be determined, a warning message is displayed to notify the user of the abnormality.

[0030]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram of the video signal processing circuit 30 according to the embodiment of the present invention. In the figure, the same circuit blocks as those of the conventional video signal processing circuit 10 of FIG. 13 are designated by the same reference numerals, and their description will be omitted. The field signal confirmation circuit 31 is a circuit for confirming whether or not the field determination circuit 16 has normally performed the field determination. When the field determination is not normally performed, the pseudo field signal in which the polarity is inverted for each field. Is generated and output.

FIG. 3 is a diagram showing an example of the field signal confirmation circuit 31. In the figure, the latch circuit 41 is
This is a circuit that latches the field signal A output from the field discrimination circuit 16 in synchronization with the rising edge of the vertical synchronization signal, and the latched signal is one input terminal of an exclusive OR gate (hereinafter referred to as EXOR) 42. Output to. The field signal A is input to the other input terminal of the EXOR 42. EXOR42
Takes the exclusive OR of the field signal A and the output signal of the latch circuit 41, and outputs the result to the D input terminal of the latch circuit 43. The latch circuit 43 latches the output signal of the EXOR 42 in synchronization with the rising edge of the vertical synchronizing signal, and outputs the latched signal as a field confirmation signal C to the control terminal of the multiplexer 45. The field confirmation signal C is used as a selection signal for the multiplexer 45.

The latch circuit 44 is a circuit for inputting the inverted output signal of its own inverted output terminal to the input terminal and latching the inverted output signal in synchronization with the rising of the vertical synchronizing signal supplied to the clock terminal. A signal obtained by dividing the vertical synchronizing signal by two is output from the latch circuit 44, and the signal is output to one input terminal of the multiplexer 45 as a pseudo field signal. The field signal A is input to the other input terminal of the multiplexer 45, and the multiplexer 45 selects one of the field signal A and the pseudo field signal D based on the field confirmation signal C output from the latch circuit 43 to the control terminal. The signal is selected and used as the field signal B in the timing generation circuit 17 of FIG.
Output to.

Next, the operation of the field signal confirmation circuit 31 having the above configuration will be described. First, the operation in the normal state, that is, in the case where the field discriminating circuit 16 can discriminate the field normally will be described with reference to the time chart of FIG.

In this case, the field discriminating circuit 16 outputs the field signal A whose polarity is inverted between the even field and the odd field, and the field signal A is latched by the latch circuit 41 by the timing synchronized with the rising of the vertical synchronizing signal. It Here, since the field signal A and the vertical synchronizing signal change at the timing shown in FIG. 4, the output signal of the latch circuit 41 has a polarity opposite to that of the field signal A of the next field.

Therefore, the field signal A one field before latched by the latch circuit 41 is input to one input terminal of the EXOR 42, and the current field signal A is input to the other input terminal of the EXOR 42. Since the polarities of the input signals of both input terminals do not match, the output signal of the EXOR 42 becomes high level. And that EXOR4
The output signal 2 is latched by the latch circuit 43 at the timing synchronized with the rising edge of the vertical sync signal. Therefore, when the field signal can be normally discriminated, the latch circuit 4
The field confirmation signal C output from 3 is always at high level.

When the field confirmation signal C is at the high level, the multiplexer 45 operates in the field discrimination circuit 16
The field signal B output from the above is selected and output as the field signal B to the timing generation circuit 17 described above. As a result, the same signal as the field signal A is sent from the multiplexer 45 as shown in FIG.
Is output as.

Next, the operation at the time of abnormality, that is, when the field determination circuit 16 cannot determine the field,
This will be described with reference to the time chart of FIG. in this case,
Since the polarity of the field signal A output from the field discrimination circuit 16 is not inverted for each field, the polarity of the field signal of the previous field latched by the latch circuit 41 is the same as the polarity of the current field signal A. , And the input signals of the input terminals of the EXOR 42 have the same polarity, the output signal of the EXOR 42 is always at the low level. The low level output signal is latched by the latch circuit 43 in synchronization with the rising of the vertical synchronizing signal, and the latched low level signal is output to the multiplexer 45 as the field confirmation signal C.

When the field confirmation signal C is at low level, the multiplexer 45 selects the pseudo field signal D output from the latch circuit 44 and selects the field signal B.
Is output to the timing generation circuit 17. As a result,
As shown in FIG. 5, the multiplexer 45 outputs a pseudo field signal D obtained by dividing the vertical synchronization signal by two as a field signal B.

FIG. 6 is a diagram showing a display example when the field discriminating circuit 16 cannot discriminate a field. In this embodiment, when the field cannot be discriminated, in the field signal confirmation circuit 31,
Since the pseudo field signal D whose polarity is alternately inverted at the timing synchronized with the vertical synchronizing signal is generated, the data is alternately displayed on the even lines and the odd lines as shown in FIG. At this time, the field signal confirmation circuit 31 cannot recognize whether the data is to be displayed on the even lines or the odd lines, so that the data to be displayed on the even lines is on the odd lines. There is a 50% chance that the data to be displayed and to be displayed on the odd lines will be displayed on the even lines.

However, even in that case, the display quality is remarkably improved as compared with the conventional case where the data is displayed on only one of the even lines and the number of lines. Further, since it is possible to supply a voltage whose polarity is inverted alternately to even lines and odd lines based on the pseudo field signal D whose polarity is inverted to perform AC driving, the liquid crystal is displayed even when displaying on a liquid crystal display device. The conventional drawback of deterioration can be eliminated.

Further, in the above-described embodiment, when the field signal confirmation circuit 31 does not detect the field signal normally, the pseudo field signal D is generated from the vertical synchronizing signal so that the liquid crystal is not driven by direct current. It is also possible to prevent the liquid crystal from being driven by direct current without generating the field signal D.

For example, in a display device which displays an image from a video signal input from the outside, when no video signal is input, a video signal or a timing signal for displaying a fixed color is created, and a full blue display (this is displayed). Many are designed to display a fixed color such as black (blue background display) or black. Therefore, when the field signal A is not detected by the field signal confirmation circuit 31 described above, if a fixed color is displayed by using the function, the liquid crystal is driven by direct current even when the field signal is not detected. It can be prevented.

Next, FIG. 7 shows a field signal confirmation circuit 31.
FIG. 7 is a diagram showing a main part of a drive circuit of a liquid crystal display device according to a second embodiment of the present invention which displays a warning message when a field signal is not normally detected in FIG.

In the figure, the field signal confirmation circuit 5
0 is the field signal confirmation circuit 3 of the first embodiment described above.
The circuit is basically the same as 1. However, in this embodiment, since the pseudo field signal D is not generated, the circuit is simplified accordingly.

The ROM 51 stores a warning message such as "input error", and the field signal confirmation circuit 3
When the field signal A is not detected normally in 1
The data creation unit 52 creates a video signal corresponding to the warning message and outputs the video signal to the multiplexer 53. The video signal generated from the warning message and the normal video signal are input to the multiplexer 53, and the multiplexer 53 selects one of the input signals according to the field confirmation signal C output from the field signal confirmation circuit 31. And outputs it to the inverting circuit 25 and the multiplexer 17 described above.

Next, the operation of the above circuit will be described. When the field signal confirmation circuit 50 does not detect the field signal A, the field signal confirmation circuit 50 outputs to the multiplexer 53 a selection signal for instructing the selection of the video signal of the warning message output from the data creation unit 52. To be done.

As a result, the multiplexer 53 selects the video signal of the warning message and outputs it to the inverting circuit 25 and the multiplexer 17. The multiplexer 17 outputs the video signal of the warning message output from the multiplexer 53 as it is or an inverted video signal to the source driver of the liquid crystal display device described above. Accordingly, when the field signal is not detected, a warning message is displayed, and the user can know from the display that a nonstandard video signal is input.

Next, the one-shot multivibrator 6
FIG. 8 shows an example in which the field signal confirmation circuit 31 is configured by 1.
Will be described with reference to. In the figure, when a pulse is input to the B input terminal of the one-shot multivibrator 61, a capacitor C that determines the pulse width output from the output terminal Q, that is, the pulse width of the output pulse (the period when the output pulse is at the high level). And the value of the resistance R are set so that the pulse width is a little longer than two vertical periods.

The operation of the one-shot multivibrator 61 will be described with reference to the time charts of FIGS. 9 and 10. First, as shown in the time chart of FIG. 9, the field signal A whose polarity is inverted at a constant cycle is used.
Is the input terminal B of the one-shot multivibrator 61
When the field signal A is changed, the one-shot multivibrator 61 is re-triggered and the pulse width of the output pulse is extended. As a result, from the one-shot multi-vibrator 61,
As shown in FIG. 9, a high level signal is always output as the field confirmation signal C.

On the other hand, when the polarity of the field signal A is fixed to, for example, a high level as shown in the time chart of FIG. 10, the one-shot multivibrator 61 is not retriggered, and after two vertical periods have elapsed, the one-shot multivibrator 61 shown in FIG. The output pulse becomes low level as shown in FIG.

That is, the one-shot multivibrator 61 always outputs a high level signal when the field signal A is normally detected, and outputs a low level signal when the field signal A is no longer detected. To do. Therefore, the field signal confirmation circuit 31 of FIG.
Similarly to, it is possible to confirm whether the field can be normally discriminated.

In the above embodiment, the latch circuit,
Although the field signal confirmation circuit 31 is configured by using a logical circuit such as an EXOR and a multiplexer and a one-shot multivibrator, the field signal confirmation circuit 31 is not limited to these circuits and may be configured by another circuit. Further, the field signal is not limited to the signals having different polarities described in the embodiment, and may be any signal capable of distinguishing individual fields.

[0053]

According to the present invention, even if a field signal cannot be discriminated due to input of a nonstandard video signal, for example, display is performed based on a pseudo field signal whose polarity is inverted in synchronization with the vertical sync signal. Therefore, it is possible to prevent the display quality from deteriorating and prevent the liquid crystal display device from being driven by direct current. Further, if the field discrimination cannot be performed normally, a warning message or the like is displayed to call the user's attention.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram of a video signal processing circuit according to an embodiment.

FIG. 3 is a configuration diagram of a field signal confirmation circuit.

FIG. 4 is a time chart when a field can be normally discriminated.

FIG. 5 is a time chart when a field cannot be discriminated.

FIG. 6 is a diagram showing a display state when a field cannot be discriminated.

FIG. 7 is a diagram showing a main part of a drive circuit according to a second embodiment.

FIG. 8 is a diagram showing another configuration example of the field signal confirmation circuit.

FIG. 9 is a time chart when the field can be normally discriminated in the second embodiment.

FIG. 10 is a time chart when the field cannot be discriminated in the second embodiment.

FIG. 11 is a diagram showing a video signal waveform.

FIG. 12 is an explanatory diagram of a CRT display method.

FIG. 13 is a circuit block diagram of a drive circuit of a conventional liquid crystal display device.

FIG. 14 is a diagram showing a display screen of an LCD according to a first driving method.

FIG. 15 is a diagram showing a display screen of an LCD according to a second driving method.

FIG. 16 is a diagram showing a display screen of an LCD according to a third driving method.

FIG. 17 is a diagram showing the polarities of LCD drive signals.

FIG. 18 is a diagram showing a main part of a conventional drive circuit.

FIG. 19 is a diagram showing a display state when a field signal is fixed to an odd field.

FIG. 20 is a diagram showing a display state when a field signal is fixed to an even field.

[Explanation of symbols]

 1 field signal output means 2 field confirmation means 3 field signal holding circuit 4 polarity discrimination circuit 5 pseudo field signal generation circuit 6 selection circuit

Claims (16)

[Claims] 1. A field signal output means (1) for outputting a signal for discriminating a field of a video signal composed of a plurality of fields, and a field can be normally discriminated from a signal output from the field signal output means (1). A video signal processing circuit, comprising: a field confirming means (2) for confirming whether or not it is present. 2. A video signal selection circuit for selecting and outputting one of a video signal and a signal obtained by inverting the polarity of the video signal based on the confirmation result of the field confirmation means (2). The video signal processing circuit according to claim 1. 3. The field signal output means (1) comprises:
A circuit for outputting field signals having different polarities between an even field and an odd field of a video signal, wherein the field confirmation means (2) outputs the field signal of one field before output from the field signal output means (1). A field signal holding circuit (3) for holding, and 1 held in the field signal holding circuit (3)
A polarity discriminating circuit (4) for discriminating whether or not the polarities of the field signal before the field and the current field signal are different from each other.
When the polarity discriminating circuit (4) discriminates that the two field signals have different polarities, the field signal output from the field signal output means (1) is outputted, and the polarity discriminating circuit (4). When it is determined that the two field signals have the same polarity, a field signal output circuit that generates a signal whose polarity is inverted in synchronization with the vertical synchronization signal and outputs the signal as a field signal is provided. The video signal processing circuit according to claim 1, wherein 4. The field signal output circuit includes: a pseudo field signal generation circuit (5) for generating a pseudo field signal whose polarity is inverted in synchronization with a vertical synchronization signal; When it is determined that the polarities of the field signals are different, the field signal output from the field signal output means (1) is selected and output, and the polarities of the two field signals are the same in the polarity determination circuit (4). When it is determined that
The video signal processing circuit according to claim 3, further comprising a selection circuit (6) for selecting and outputting the pseudo field signal generated by the pseudo field signal generation circuit (5). 5. The field confirmation means (2) latches a field signal of one field before output from the field signal output means (1), and one field before held in the latch circuit. An exclusive OR gate for determining whether or not the polarities of the field signal and the current field signal are different from each other; a second latch circuit for generating a pseudo field signal whose polarity is inverted in synchronization with a vertical synchronizing signal; When it is determined by the exclusive OR gate that the two field signals have different polarities, the field signal output from the field signal output means (1) is selected and output, and the exclusive OR gate outputs the field signal. Generated by the second latch circuit when it is determined that the polarities of the two field signals are the same. 4. The video signal processing circuit according to claim 3, further comprising a selector for selecting and outputting the generated pseudo field signal. 6. A field signal output means (1) for outputting a signal for discriminating a field of a video signal composed of a plurality of fields, and a field is normally discriminated from a field signal output from the field signal output means (1). A video signal processing circuit having a notifying means for notifying an abnormality when it is not possible. 7. The video signal processing circuit according to claim 6, wherein the notifying means displays a warning message on the display device when the field cannot be discriminated. 8. The video signal processing circuit according to claim 6, wherein the notifying unit notifies the occurrence of an abnormality by displaying a fixed color on the display device when the field cannot be discriminated. 9. A field signal output means (1) for outputting a signal for discriminating fields of a video signal composed of a plurality of fields, and a field can be normally discriminated from a signal output from the field signal output means (1). A liquid crystal display device, comprising a video signal processing circuit comprising a field confirmation means (2) for confirming whether or not it is present. 10. A video signal processing circuit comprising a video signal selection circuit for selecting and outputting one of a video signal and a signal obtained by inverting the polarity of the video signal based on the confirmation result of the field confirmation means (2). The liquid crystal display device according to claim 9, further comprising: 11. The field signal output means (1)
Is a circuit for outputting field signals having different polarities between an even field and an odd field of the video signal, and the field confirmation means (2) is a field preceding the field output from the field signal output means (1). A field signal holding circuit (3) holding a signal, and 1 held in the field signal holding circuit (3)
A polarity discriminating circuit (4) for discriminating whether or not the polarities of the field signal before the field and the current field signal are different from each other.
When the polarity discriminating circuit (4) discriminates that the two field signals have different polarities, the field signal output from the field signal output means (1) is outputted, and the polarity discriminating circuit (4). When it is determined that the polarities of the two field signals are the same, the video including a field signal output circuit that generates a signal whose polarity is inverted in synchronization with the vertical synchronization signal and outputs the signal as a field signal. The liquid crystal display device according to claim 9, further comprising a signal processing circuit. 12. The field signal output circuit includes a pseudo field signal generation circuit (5) for generating a pseudo field signal whose polarity is inverted in synchronization with a vertical synchronization signal, and the polarity discriminating circuit (4) for providing the two signals. When it is determined that the polarities of the field signals are different, the field signal output from the field signal output means (1) is selected and output, and the polarities of the two field signals are the same in the polarity determination circuit (4). When it is determined that
12. The liquid crystal display device according to claim 11, further comprising a video signal processing circuit including a selection circuit (6) for selecting and outputting a pseudo field signal generated by the pseudo field signal generation circuit (5). 13. The field confirmation means (2) includes a latch circuit for latching a field signal of one field before output from the field signal output means (1), and one field before stored in the latch circuit. An exclusive OR gate for determining whether the polarities of the field signal and the current field signal are different, and a second latch circuit for generating a pseudo field signal whose polarity is inverted in synchronization with the vertical synchronizing signal, When the exclusive OR gate determines that the two field signals have different polarities, the field signal output from the field signal output means (1) is selected and output, and the exclusive OR gate outputs the field signal. When it is determined that the two field signals have the same polarity, the second latch circuit generates The liquid crystal display device according to claim 11, characterized in that it comprises a video signal processing circuit comprising a pseudo-field signal selector for selecting and outputting to be. 14. A field signal output means (1) for outputting a signal for discriminating a field of a video signal composed of a plurality of fields, and a field is normally discriminated from a field signal output from the field signal output means (1). A liquid crystal display device having a video signal processing circuit including a notifying unit for notifying an abnormality when it is not possible. 15. The liquid crystal display device according to claim 14, wherein the notification means displays a warning message on the display device when the field cannot be discriminated. 16. The liquid crystal display device according to claim 14, wherein the notifying unit notifies the occurrence of an abnormality by displaying a fixed color on the display device when the field cannot be discriminated.