JPH07264250A - Serial data transmitter - Google Patents

Abstract

PURPOSE:To transmit serial data by allowing a transmission controller not having an oscillating source to superimpose data onto a clock signal from a transmission controller having an oscillation source and taking the operating timing with the clock signal. CONSTITUTION:An oscillating source 11 is provided to only a master station 10 and an original oscillating signal is frequencydivided into a prescribed frequency signal by a frequency divider circuit 12 to generate a clock signal and a transmission reception circuit 13 sends/receives a data signal and provides an output of the clock signal to a transmission line 20. On the other hand, a transmission reception circuit 31 of a slave set 30 connecting to the transmission lien 20 and not having any oscillating source transmits data serially while superimposing the data onto the received clock signal. Then a clock extract section 32 in the slave station 30 extracts the clock signal from the received signal comprising superimppsed clock and data signals and all the processing operations are implemented for the slave station 30 by using the extracted clock signal. Thus, the semi-duplex serial data transmission is conducted by having only to provide the oscillating source to one station on a network.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data transmission device for transmitting a data signal and a clock signal via a single transmission line.

[0002]

2. Description of the Prior Art Two lines, a data line and a clock line, are required to perform synchronous serial transmission in which bit synchronization is achieved by a clock signal. However, in the case of long-distance transmission or multi-station transmission, the large number of lines has a great influence on the cost. Therefore, it is desirable to send the data signal and the clock signal by one line (one transmission line). , A self-synchronization method of extracting a clock signal from the data signal and decoding the data signal using the extracted clock signal is required.

As a conventional method of self-synchronization, the use of Manchester code as shown in FIG. 11 is well known.
The NRZ code shown in FIG. 10 is the simplest and most basic code as a digital code, but there is no change in the signal when data is followed by "0" or "1", and sufficient clock information is available. Is not included. On the other hand, in the case of Manchester code, when the data is "0", it is composed of a code that rises at the center of the bit and when the data is "1", it is composed of a code that falls at the center of the bit. There is a drop, and clock information is included in each bit.

FIG. 12 shows an example of a circuit for extracting a clock component from Manchester code, which will be described with reference to the timing chart of FIG. In FIG. 12, the data signal A according to the Manchester code received from the transmission line is directly input to one input end of the exclusive OR circuit 1, and is input to the other input end of the exclusive OR circuit 1 via the delay circuit 2. Input as a delayed signal (delayed signal B). The output signal C of the exclusive OR circuit 1 is input to one input terminal of the AND circuit 3. A signal D negating the output of the monomultivibrator 4 is input to the other input terminal of the AND circuit 3. Then, the output signal E of the AND circuit 3 is extracted as a clock component. A signal obtained by negating the output signal E is fed back to the input of the mono-multivibrator 4. The signals A to E are the same as those in FIG.
It corresponds to.

When a Manchester coded data signal A corresponding to a data value as shown in FIG. 11 is received, the exclusive logic circuit 1 determines which of the data signal A directly input and the delay signal B from the delay circuit 2. The output signal C becomes Hi (high) level only when one of them is at Hi level. On the other hand, a Hi-level signal is input to the monomultivibrator 4 when the output signal E of the AND circuit 3 falls, and this is used as a trigger to generate a Hi-level output for a certain period. Therefore, since the output of the mono multivibrator 4 is negated and input to the other input terminal of the AND circuit 3, the output from the Hi level output of the mono multivibrator 4 is ended until the next trigger. During this period, the output signal C of the exclusive OR circuit 1 becomes Hi level during that period, and the output of the AND circuit 3 becomes Hi level. By such an operation, the clock component indicated by E in FIG. 13 is extracted. The clock component thus obtained is further processed and used for decoding the received data.

[0006]

However, in such a conventional self-synchronization method, although the clock component can be extracted for each bit, the generation timing of the clock component differs depending on the received data signal, and therefore the decoding is performed as it is. It cannot be used as a timing signal, and an oscillator or the like that serves as a time reference is required to generate the timing for determining "0" / "1" of each bit.

Further, the clock signal is extracted only when receiving data and cannot be used for any purpose other than the receiving operation. In order to transmit data, it is necessary to provide an oscillation source for generating clock information, and other processing operation timings. Was also based on the signal from this oscillator. Therefore, in the conventional serial data transmission device using the self-synchronous system, it is necessary to provide an oscillation source for each of a plurality of stations forming the network, which is an obstacle to cost reduction.

The present invention has been made in view of the above circumstances, and serial data transmission is achieved by providing only one of a plurality of transmission control devices connected to each other by a transmission line with an oscillation source for generating clock information. It is an object of the present invention to provide a serial data transmission device that enables the above.

[0009]

For this reason, the serial data transmission apparatus according to the present invention includes an oscillation source and a clock signal output means for constantly outputting a clock signal generated based on the signal of the oscillation source to the transmission line. A data signal output means for outputting a data signal having a frequency equal to that of the clock signal superimposed on the clock signal on the transmission line in synchronization with a clock signal generated based on the signal of the oscillation source; And a signal processing means for processing the extracted data signal in synchronism with a clock signal generated based on the signal of the oscillation source. A device, a clock signal extracting means for receiving a signal on the transmission line and extracting a clock signal, and a data signal output for outputting a data signal by superimposing it on the clock signal on the transmission line. And at least one signal processing means for extracting a data signal from the received signal from the transmission line and processing the extracted data signal in synchronization with the extracted clock signal from the clock signal extraction means. Two transmission control devices.

Further, the clock signal output means is configured to alternately switch the potential of the transmission line between a high potential and a low potential in synchronization with the clock signal and output the clock signal to the transmission line. The signal output means, when the transmission line is in a high potential state, switches the potential of the transmission line between the high potential and an intermediate potential between the high potential and the low potential according to the data to be output, and outputs the data. It is configured to be superimposed on the clock signal.

More specifically, the clock signal output means connects the transmission line to a constant voltage source via a pull-up resistor, and turns on between the transmission line and ground in synchronization with the clock signal. The data signal output means is connected between the transmission line and the ground in parallel with the first transistor and turned on / off according to the pull-down resistor and the data signal. The configuration is such that a series circuit with the second transistor that is turned off is interposed.

Further, the clock signal extracting means is constituted by including a comparing means for comparing the potential of the received signal with a reference potential having a preset potential between the intermediate potential and the low potential. Further, a data transmission start detecting means for detecting the start of data transmission when receiving a predetermined signal sequence set in advance is provided, and a signal after the signal sequence is taken in as a data signal based on the detection signal of the data transmission start detecting means. It is good to have a configuration.

Further, the serial data transmission device according to the present invention comprises one of an oscillation source and a clock signal output means for constantly outputting a clock signal generated based on the signal of the oscillation source to the transmission line. A first transmission control device; a clock signal extraction means for receiving a signal on the transmission line and extracting a clock signal; a data signal output means for superimposing a clock signal on the transmission line to output a data signal; A plurality of second transmission control devices each including a signal processing means for extracting a data signal from a received signal from the line and processing the extracted data signal in synchronization with the extracted clock signal from the clock signal extracting means; You may make it comprise.

[0014]

According to this structure, the first transmission controller having the oscillation source always outputs the clock information on the transmission line. On the other hand, on the side of the second transmission control device having no oscillation source, the clock signal is constantly extracted from the signal on the transmission line, and the extracted clock signal is output at the timing of all operations such as processing of received data and transmission of data. To use. Further, the data transmission operation on the side of the first transmission control device is timed by the clock information from its own oscillation source.

Furthermore, when the first transmission control device side has only the oscillation function of the clock signal, the first transmission control device side constantly outputs the clock signal to the second transmission line.
On the transmission control device side, and the second transmission control devices transmit and receive data based on the extracted clock signal.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a network configuration of a first embodiment of a serial data transmission device according to the present invention. In FIG. 1, a master station 10 as a first transmission control device is connected to a plurality (three in this embodiment) slave stations 30 as second transmission control devices by one transmission line 20. .

The master station 10 includes an oscillation source 11 composed of, for example, a crystal oscillator, and a frequency dividing circuit for dividing the original oscillation from the oscillation source 11 into a predetermined frequency to generate a clock (CLK) signal.
12, a transmission / reception circuit 13 that operates based on the clock signal from the frequency dividing circuit 12, and a decoder 14 that extracts and decodes a data signal from the reception signal received by the transmission / reception circuit 13.
A transmission control section 15 including a communication IC and a microcomputer that outputs the data signal to be transmitted to the slave station 30 to the transmission / reception circuit 13 while performing a predetermined processing operation by taking in the data signal from the decoder 14 It is equipped with. The transmission / reception circuit 13 outputs a clock signal onto the transmission line 20 while transmitting / receiving a data signal. Here, the transmission / reception circuit 13 corresponds to clock signal output means and data signal output means, and the decoder 14 and the transmission control unit 15 correspond to signal processing means.

On the other hand, the plurality of slave stations 30 have the same structure,
A clock signal is received from a transmission / reception circuit 31 that receives a signal on the transmission line 30 and that transmits a data signal from the slave station 30, and a reception signal in which the clock signal and the data signal received by the transmission / reception circuit 31 are superimposed. A clock extracting unit 32 as a clock signal extracting unit for extracting, a decoder 33 for extracting and decoding a data signal from a received signal, and the clock extracting unit
A master station that receives and processes the data signal from the decoder 33 in synchronization with the extracted clock signal extracted by 32 and outputs a data signal to be transmitted to the master station 10 or another slave station 30 to the transceiver circuit 31. The transmission control unit 34 is composed of the same communication IC as 10 and a microcomputer. Here, the transmission / reception circuit 31 corresponds to the data signal output means in the second transmission control device, and the transmission control unit 34
And the decoder 33 correspond to the signal processing means in the second transmission control device.

As described above, in the serial data transmission system of this embodiment, only the master station 10 has the oscillation source 11 for generating the clock signal, and the slave station 30 side has no oscillation source. . Next, FIG. 2 shows an example of the transmission / reception circuit 13 built in the master station 10. In FIG. 2, the transmission line 20 is connected to a constant voltage source of constant voltage Vdd via a pull-up resistor R1. Further, a signal obtained by inverting a clock signal (shown by TX-CLK in the drawing) from the frequency dividing circuit 12 by an inverter 41 is provided between the transmission line 20 and the ground to turn ON / OF.
Transistor Tr1 as the first transistor for F
Are connected. Further, between the transmission line 20 and the ground, a transistor Tr2 as a second transistor in parallel with the transistor Tr1 and a pull-down resistor R2 having a resistance value similar to that of the pull-up resistor R1.
The series circuit of is connected. The transistor Tr2
Is configured to be turned on / off by a data signal (denoted by TX-NRZ in the drawing) of the NRZ code from the transmission control unit 15. In addition, a reception signal (RX in the figure) is transmitted from the transmission line 20 through a filter composed of a resistor R3 and a capacitor C1.
(Denoted by) is captured and input to the decoder 14.

On the other hand, FIG. 3 shows an example of a transmission / reception circuit 31 built in the slave station 30 side. The configuration of the transmission / reception circuit 31 on the slave station 30 side is based on the data signal (TX-NRZ in the figure) from the transmission control unit 34.
A series circuit of a transistor Tr3 as a second transistor which is turned on / off based on the above) and a pull-down resistor R4 is connected between the transmission line 20 and the ground. In addition, from the transmission line 20 to the resistor R5 and the capacitor C2
The received signal (indicated by RX in the drawing) is taken in through the filter configured in (4) and input to the clock extraction unit 32.

The transmitter / receiver circuit 31 on the side of the slave station 30 includes a circuit portion of a pull-up resistor R1 and a transistor Tr1 for transmitting a clock signal to the transmission line 20, which is provided in the transmitter / receiver circuit 13 on the side of the master station 10. It has been removed. FIG. 4 shows an example of codes of transmission data corresponding to binary data of “0” and “1” applied to the transmission apparatus of this embodiment.

Two determination levels of V _H and V _L (V _H > V _L > 0) are provided, a pulse having a potential of V _H or more is “0”, and a pulse having a potential of V _L or more and less than V _H is set. "1"
To determine. That is, the data transmission on the master station 10 side will be described as an example. When data having a logical value “0” is input from the transmission control unit 15 to the base of the transistor Tr2, the transistor Tr2 is turned off and the transmission line 20 is high. It becomes the constant voltage Vdd. On the other hand, when the data of the logical value "1" is input from the transmission control unit 15 to the base of the transistor Tr2, the transistor Tr2 is turned on and the potential of the transmission line 20 divides the constant voltage Vdd by the resistors R1 and R2. It becomes an intermediate voltage value. Therefore, setting the V _H to a value between the divided constant voltage Vdd, by setting the V _H lower than the divided voltage value value, corresponding to the potential on the transmission line 20 the data values The data can be encoded and transmitted, and the data can be identified on the receiving side.

Next, FIG. 5 shows an example of a circuit of the clock extraction unit and the decoder of the slave station 30, which converts the reception signal RX received by the transmission / reception circuit of FIGS. 2 and 3 into an NRZ code. In FIG. 5, the received signal RX is the comparator C
It is input to the non-inverting inputs of mp1 and Cmp2, and the resistor R is provided on the inverting input side of each comparator Cmp1 and Cmp2.
The voltage value V _H resulting from the voltage division of 6, R7 and the voltage value V _L resulting from the voltage division of the resistors R8 and R9 are respectively inputted as reference values. However, V _H and V _L are the determination levels described in FIG. 4, and V _H > V _L.

The output of the comparator Cmp1 is the delay circuit 5
1 and the output of the delay circuit 51 is input to the reset terminal of the flip-flop FF1. Further, the output of the comparator Cmp2 is a pulse having a constant cycle regardless of the data value because the received signal RX is composed of pulses as shown in FIG. 4, and this is the extracted clock signal RX-
Flip-flop F at the same time as CLK
It is input to the clock terminal of F1. Further, the Hi-level signal is always input to the input terminal of the flip-flop FF1, and the output is connected to the input of the flip-flop FF2. The extracted clock signal RX-CLK is input to the clock terminal of the flip-flop FF2, operates at the falling edge of the extracted clock signal RX-CLK, and outputs the decoded data signal RX- of the NRZ code.
Imported as NRZ.

Therefore, the comparator Cmp2 corresponds to the comparing means, and the comparator Cmp2 and the resistors R8 and R9 are included.
The clock extraction unit 32 is composed of a comparator Cm.
The decoder 32 is composed of p1, resistors R6 and R7, a delay circuit 51, and flip-flops FF1 and FF2. The decoder 14 on the master station 10 side also has the same configuration as the decoder 32 of the slave station 30. Then, on the side of the master station 10, the circuit portion corresponding to the clock extraction unit 32 composed of the resistors R8 and R9 and the comparator Cmp2 is unnecessary.

Next, the operation will be described with reference to the timing chart of FIG. A clock signal TX-CLK for synchronization, as shown in the figure, obtained by dividing the original oscillation of the oscillation source 11 is constantly input to the transmission / reception circuit 13 of the master station 10, and the transistor Tr1 is turned on / off. Transistor Tr1 is ON
In the case of, the transmission line 20 is grounded and has a low potential, and in the case of OFF, it is connected to a constant voltage source and has a high voltage substantially equal to the constant voltage Vdd. Therefore, a pulse having a potential equal to or higher than V _L and having the same frequency as the clock signal TX-CLK is always output on the transmission line 20 regardless of the presence or absence of a data signal.

When transmitting data from the master station 10, the clock signal T
N that changes data at the falling edge of X-CLK
The data signal TX-NRZ of the RZ code is given to the base of the transistor Tr2 of the transmission / reception circuit 13. When the clock signal TX-CLK is at Lo (low) level, the transistor Tr1 is turned on and the transmission line 20 is grounded. Therefore, regardless of the state of the transmission data signal TX-NRZ, that is, ON / OFF of the transistor Tr2. The signal on the transmission line 20 becomes Lo level. On the other hand, when the synchronous clock (1001) is at the Hi level, the transistor Tr1
Is turned off, the signal level on the transmission line 20 changes depending on the state of the transmission data signal TX-NRZ. That is, the transmission data signal TX-NR by the NRZ code
When Z is "0", that is, Lo level, the transistor Tr2 is turned off, and the output of the transmission line 20 becomes substantially equal to Vdd due to the pull-up resistor R1. In addition, the transmission data signal TX-
When NRZ is "1", that is, Hi level, the transistor Tr
2 is turned on, and the intermediate potential of about 1/2 Vdd is output to the transmission line by the voltage division of the pull-up resistor R1 and the pull-down resistor R2.

The received signal shown in FIG. 6 is shown when such a data signal is superimposed on the clock signal. Upon receiving the reception signal RX from the transmission line 20, the slave station 30 side extracts the clock signal and decodes the reception signal by the circuit of FIG. The received signal RX is the comparator C
Input to mp1 and Cmp2, respectively. Reference potential is V _L
The comparator Cmp2 outputs a pulse having a constant cycle regardless of the potential of the reception signal RX, that is, regardless of the value of the reception data, which is the extracted clock signal RX-CL.
It is used as K for sampling received data and for internal logic operation. On the other hand, since the reference potential of the comparator Cmp1 is V _H , the pulse is output only when the reception signal RX has a high potential, that is, when the reception data is “0”. The output of the comparator Cmp1 is delayed by the delay circuit 51 and input as the signal F to the reset terminal of the flip-flop FF1. Therefore, the extracted clock signal RX-CLK
Even when the output signal G of the flip-flop FF1 becomes Hi level due to the rising of the signal, when the received data is "0", it becomes Lo level after a certain delay time. The output signal G of the flip-flop FF1 is extracted as a clock signal RX-
The flip-flop FF2 samples at the falling edge of CLK. That is, the flip-flop FF
2 holds and outputs the input (signal G) state when the extracted clock signal RX-CLK falls. The output of the flip-flop FF2 becomes the received data signal RX-NRZ by the NRZ code after decoding, and the transmission control unit 34
Is taken into. Then, the extracted clock signal RX-CL
As described above, K is also output to the transmission control unit 34 in addition to the decoding of the received signal, and the control operation on the slave station 30 side,
It is used for all logical operations such as transmission.

The transmission from the slave station 30 to the master station 10 is also the same operation except that the synchronization clock signal TR-CLK is still output by the master station 10. And
The intermediate potential of the transmission signal (when the data value is "1") is the master station.
It is determined by the voltage division value of the pull-up resistor R1 on the 10 side and the pull-down resistor R4 on the slave station 30 side. The transmission operation on the slave station 30 side is shown in FIG.
Similarly to the transmission data signal TX-NRZ of the master station 10 shown by, the transmission data can be changed at the falling edge of the extracted clock signal RX-CLK. However, since the master station 10 side has the oscillation source 11, it is not necessary to extract the clock signal from the received signal RX, and the decoder 14 and the transmission controller 15 are controlled using the clock signal TX-CLK generated by itself. is doing.

As described above, the oscillation source 11 is provided only on the master station 10 side, and clock information is constantly output to the transmission line 20.
On the side of the slave station 30 having no oscillation source connected by, the data is serially transmitted by being superimposed on the clock signal. In the slave station 30 having no oscillation source, clock information is extracted from the signal on the transmission line 20, and all processing operations on the slave station 30 side are performed by the extracted clock. Therefore, only one of the stations that make up the network
Only the station needs to have the oscillation source, and the cost can be reduced as compared with the conventional configuration in which all stations have the oscillation source as the time reference.

Further, if attention is paid only to the method of changing the amplitude of the carrier wave to obtain transmission data, AM (amplitude modulation) using a sine wave as a carrier wave can be taken as an example. However, in AM, since the carrier wave and the transmission data have no synchronous relationship, the frequency of the carrier wave needs to be sufficiently higher than the frequency of the transmission data. In addition, the circuit is complicated because it is an analog technology using a sine wave. On the other hand, in the present embodiment, the carrier wave is always used as the clock of the digital waveform and the transmission data is the digital data of the same frequency synchronized with this clock, so that the simple circuit configuration facilitates the synchronization. Therefore, it is possible to perform half-duplex bidirectional transmission. Further, the characteristics are different from the AM in that the digital technology is mainly used and the circuit is simple and therefore the integration is easy.

FIG. 7 shows an example in which the code used in the serial data transmission apparatus of the present invention has transparency. As shown in (A) of the figure, SOM (Start) indicating the start of communication
of Message) is “111” pulse, data “00” is “100” pulse as shown in FIG. (B), and data “01” is “110” as shown in FIG.
Pulse, data “10” as shown in FIG.
1 "pulse, data" 11 "as shown in FIG. 7E is represented by" 011 ", and 2-bit data is represented by three pulses.

[0033] When data is transmitted using such a code, except during the data transmission, if and to turn OFF the transistor Tr2 of each station transmitting and receiving circuit, when not in communication state exceeds V _H level " Only the high voltage pulse corresponding to "0" is continuously output to the transmission line 20, and the SOM is detected when the low voltage pulse corresponding to "1" is received three times in succession, The subsequent signal can be captured as transmission data.

FIG. 8 shows an example of the configuration of the transmission control unit of each station in the embodiment in which the code of FIG. 7 is used, which is often used when detecting character coded data. . Here, for example,
A case where this circuit is incorporated in the transmission control unit on the side of 30 will be described. The data signal RX-NRZ converted into the NRZ code by the decoder 33 having the circuit configuration shown in FIG. 5 is converted into 3-bit parallel data by the shift register 61 in the transmission control unit 34 'of this embodiment. When this 3-bit data becomes “111”, the SOM detection circuit 62 outputs S
The OM detection signal is output to the control timing generation circuit 63. When this output is input, the control timing generation circuit 6
3 operation is started, various timing signals are generated based on the extracted clock signal RX-CLK extracted by the decoder 33, each latch 64 and the control circuit 65 are controlled, and then the three bits from the shift register 61 The received data is latched and controlled. The master station 10 is similar to the above except that the clock signal TX-CLK obtained by dividing the original oscillation of its own oscillation source 11 is used instead of the extracted clock signal RX-CLK. is there.

According to this structure, it is possible to easily determine the presence or absence of data on the transmission line 20, and it is also possible to adopt a procedure in which each station performs transmission asynchronously like the contention system. In addition, EOM (End of Messa
It goes without saying that it is also possible to provide the end of data by providing ge) or the like.

FIG. 9 shows still another embodiment of the present invention. In the embodiment shown in FIG. 9, one station 70 specialized for clock output is provided as a first transmission control device, and this station 70 is used as a transmission line.
The configuration is such that 20 is connected to a station 80 as a second transmission control device for transmitting a plurality of data. Bureau 70
Is a configuration including only an oscillation source 11, a frequency dividing circuit 12, and a transmitting circuit 13 '. The oscillation source 11 and the frequency dividing circuit 12 are the same as those in the embodiment shown in FIG. Also, the transmitter circuit 13 '
Need only have a function of transmitting a clock signal, and the transistor Tr1 of the circuit shown in FIG.
And a resistor R1 for pulling up the transmission line 20 to a constant voltage Vdd, and other transistors Tr2 and R
The components such as 2, R3 and the capacitor C1 are unnecessary.

Further, each station 80 for transmitting data has the same structure as the slave station 30 shown in FIG. In this embodiment, the station 70 constantly outputs a clock signal onto the transmission line 20, superimposes the clock signal on this clock signal, and performs data transmission between the other stations 80. Each station 80 extracts clock information from the signal on the transmission line 20 in the same manner as described above, and takes timing of each operation in the station. That is, the station 70 is the same as in the above-described embodiments except that the station 70 has only a clock signal output function and does not have a data transmission function.

[0038]

As described above, according to the present invention, the clock information is constantly output on the transmission line from the only first transmission control device having the oscillation source, and the oscillation source connected by the transmission line is controlled. The other second transmission control device side, which does not have it, performs serial data transmission by superimposing data on the clock signal, and the second transmission control device side extracts the clock from the signal on the transmission line and extracts the clock. Since the configuration is such that all the operations in the device are timed using signals, half-duplex serial data transmission is possible by only providing an oscillation source in one station on the network, and serial data transmission by conventional self-synchronization. It has an effect that the cost can be reduced as compared with that of the system.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment of a serial data transmission device according to the present invention.

FIG. 2 is a circuit diagram of a transmitter / receiver circuit of a master station according to the first embodiment.

FIG. 3 is a circuit diagram of a transmitter / receiver circuit of the slave station according to the first embodiment.

FIG. 4 is a diagram showing an example of codes applied to the first embodiment.

FIG. 5 is a circuit diagram showing a clock extraction unit and a decoder of the slave station according to the first embodiment.

FIG. 6 is a timing chart for explaining the operation of the first embodiment.

FIG. 7 is a diagram showing an example of encoding for making a data code transparent.

FIG. 8 is a circuit diagram of a main part of another embodiment of the serial data transmission device according to the present invention.

FIG. 9 is an overall configuration diagram of still another embodiment of the serial data transmission device according to the present invention.

FIG. 10 is a diagram showing an NRZ code.

FIG. 11 is a diagram showing Manchester codes.

FIG. 12 is a conventional self-synchronous clock extraction circuit diagram.

13 is a timing chart for explaining the operation of the circuit of FIG.

[Explanation of symbols]

 10 Master station (first transmission control device) 11 Oscillation source 13 Transmission / reception circuit 13 'Transmission circuit 14 Decoder 15 Transmission control unit 20 Transmission line 30 Substation (second transmission control device) 31 Transmission / reception circuit 32 Clock extraction unit 33 Decoder 34 Transmission control unit

Claims (6)

[Claims] 1. An oscillation source, clock signal output means for constantly outputting a clock signal generated based on the signal of the oscillation source to a transmission line, and a clock signal generated based on the signal of the oscillation source. And a data signal output means for outputting a data signal having the same frequency as the clock signal by superimposing it on the clock signal on the transmission line, and extracting the data signal from the received signal from the transmission line, and extracting the extracted data signal. A signal processing means for processing in synchronization with a clock signal generated based on the signal of the oscillation source; and a first transmission control device, and a signal on the transmission line to receive and extract a clock signal. Clock signal extracting means, data signal outputting means for outputting a data signal by superimposing it on the clock signal on the transmission line, and extracting a data signal from a received signal from the transmission line, A serial data transmission device comprising: at least one second transmission control device comprising: a signal processing means for processing the extracted data signal in synchronization with the extracted clock signal from the clock signal extraction means. 2. The clock signal output means is configured to alternately switch the electric potential of the transmission line between a high electric potential and a low electric potential in synchronization with the clock signal and output the clock signal to the transmission line. The signal output means, when the transmission line is in a high potential state, switches the potential of the transmission line between the high potential and an intermediate potential between the high potential and the low potential according to the data to be output, and outputs the data. The serial data transmission device according to claim 1, wherein the serial data transmission device is configured to be superimposed on a clock signal. 3. The clock signal output means connects the transmission line to a constant voltage source via a pull-up resistor, and turns on / off in synchronization with the clock signal between the transmission line and ground.
The data signal output means is ON / OFF between the transmission line and the ground in parallel with the first transistor in accordance with the pull-down resistor and the data signal. 3. The serial data transmission device according to claim 2, wherein the serial data transmission device has a configuration in which a series circuit with the second transistor is interposed. 4. The clock signal extracting means is provided with a comparing means for comparing the potential of the received signal with a reference potential having a preset potential between the intermediate potential and the low potential. 3. The serial data transmission device described in 3. 5. A data transmission start detection means for detecting the start of data transmission when a preset predetermined signal stream is received, and the data of the signals after the signal stream is data based on the detection signal of the data transmission start detection means. The serial data transmission device according to claim 1, wherein the serial data transmission device is configured to be captured as a signal. 6. A first transmission control device comprising: an oscillation source; and a clock signal output means for constantly outputting a clock signal generated based on the signal of the oscillation source to a transmission line; Clock signal extracting means for receiving the signal of (1) and extracting a clock signal, data signal outputting means for outputting a data signal by superimposing it on the clock signal on the transmission line, and extracting a data signal from the reception signal from the transmission line. A plurality of second transmission control devices each including: a signal processing unit that processes the extracted data signal in synchronization with the extracted clock signal from the clock signal extracting unit;