JPH07262031A - Device and method for error correcting and coding - Google Patents

Abstract

PURPOSE:To simplify the circuit configuration for executing interleave and second coding while being hardly affected by the constitutive length of a product code and an interleave length by applying interleave to every symbolic block composed of mXn pieces of rows as unit. CONSTITUTION:Six sets of units A, B, C, D, E and F divided into six blocks, for which the size of one unit is 14 symbols X 14 rows, are mutually linked and arranged in the column direction and when second coding is executed to the block set of A0, F1, E2, D3, C4 and B5 and the result is transmitted, this area is made empty. Next, a (G-th) source data packet is inputted to this area. Afterwards, first coding is executed to this packet and as a result, the sequence of first error correcting codes 14 composed of G0-G5 is formed. At such a time, second coding is executed to the next block set of B0, A1, F2, E3, D4 and C5 in parallel with the first coding and after a second parity symbol Pi is added, the result is transmitted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction coding apparatus and an error correction coding method applicable to recording and reproduction of digital data.

[0002]

2. Description of the Related Art As an error correction method used for transmitting and recording digital data, a method of converting an error correction code sequence such as Reed-Solomon code into a product code or interleaving data before and after product coding has been put into practical use. .

FIG. 15 shows an example of this product code. In the figure, the part of m columns × n rows is a two-dimensional array of data packets. Here, the first correction code Po for q symbols
Is n− for each row from the code sequence of m−q symbols in the row direction.
p rows are generated. The second correction code Pi is n in the column direction.
-M columns are generated for each column from the code sequence of -p symbols.
FIG. 16 shows another example of the product code. In the figure, m-
The portion of (q + p) columns × n rows is a two-dimensional array data packet. Here, the first correction code Po for q symbols
Is generated for n rows from a code sequence obtained by obliquely scanning data of mp columns × n rows. The second correction code Pi for p symbols is generated for each n rows from the code sequence of m symbols in the row direction.

In such a product code of two series of error correction codes, since each data symbol is included in two error correction codes, even if one error correction code cannot be corrected, the other error If the correction code can be corrected, iterative correction can be performed based on the correction result. Further, by generating an erasure pointer in the other error correction code based on one uncorrectable error code, it is possible to perform erasure error correction with a large number of correction symbols.

Data interleaving has the effect of lengthening correctable burst errors by dispersing burst errors, and is therefore used in most recording systems where burst errors are likely to occur.

However, regardless of the product code configuration or the data interleaving, both of the encoding device and the decoding device require a memory having a size corresponding to the product code configuration length and the interleave length and its control circuit. Therefore, the product code having a long configuration length (code length) and the code having a long interleave length, which have high error correction capability, have a drawback that the device becomes complicated.

That is, since the conventional product code constituent device with interleaving performs the error correction coding process on the basis of a large data packet as shown in FIGS. In the case of processing in real time, a memory for storing the next packet data is required during correction coding. This problem is the same in decoding. In particular, when the code length must be long in order to improve the error correction capability, the data packet becomes large accordingly. In addition, a large data packet capacity means that when the management unit becomes large and various data are mixed, alignment may be performed according to the type of data, which also reduces the data utilization efficiency.

[0008]

DISCLOSURE OF THE INVENTION The present invention is intended to solve such a problem and includes an interleave and a second
For the purpose of providing an error correction coding device and an error correction coding method, which can simplify the circuit configuration of the part that performs the coding of 1) without being greatly affected by the configuration length and interleave length of the product code. There is.

Further, the present invention is an error correction code capable of reducing the memory capacity for the first coding and the second coding, particularly when a complete type error correction code sequence is constructed by real-time processing. It is an object of the present invention to provide an encoding device and an error correction encoding method.

[0010]

According to the present invention, in order to achieve the above object, if k, m, and n are arbitrary positive integers, and a positive integer smaller than k × m is po, then (k
× m−po) symbols × n rows of the original data packet, with the addition of po symbols × n rows of the first parity symbols, (k × m) symbols × n rows of the first error correction code sequence Dividing the first error correction code sequence formed by the first coding means into k blocks each having a size of m symbols × n rows, The first error correction code sequence divided into k blocks is taken as L units (where L is L ≧ k
Positive integers) are connected to each other in the column direction, and the block numbers in the row direction are 0 to k−1 and the unit numbers are 0 to L−1, the units are unit numbers L−1. Units with number 0 are rotatably arranged to form a ring block matrix that can handle units with unit numbers L and above, and each block that constitutes the i-th (where 0 ≦ i ≦ L−1) unit with respect to this ring block matrix. With a block rearranging means for rearranging the unit number and the block number by 1 from 0 block of the i-th unit to each position on the circular block matrix, and a plurality of originals to be successively transmitted in sequence. The data packets are controlled so that the first encoding by the first encoding means and the block rearrangement by the block rearrangement means are sequentially performed. And a cyclic block matrix consisting of (k × m) symbols × n rows after the block rearrangement by the block rearranging means, with p i symbols (where p i is any positive integer) × n lines 2 parity symbols are added, and (k × m + pi) symbols × n
A second encoding unit that forms a second error correction code sequence of a row and a matrix symbol of the second error correction code sequence formed by the second encoding unit are (k × m) in the row direction.
+ Pi) symbols, and output means for sequentially outputting for n rows.

[0011]

That is, according to the present invention, the block rearranging means sets the first error correction code sequence formed by the first encoding means to a k of one size of m symbols × n rows.
First divided into k blocks
The error correction code sequence of 1 is used as one unit, and L units are connected to each other in the column direction. Next, block numbers in the row direction are 0 to k-1, and unit numbers are 0 to L-.
When it is set to 1, the unit of unit number 0 is rotatably arranged in the unit of unit number L-1 to form a ring block matrix that can handle units of unit number L and above, and the i-th unit is configured for this ring block matrix. Each block to be rearranged is rearranged to each position on the circular block matrix obtained by increasing the unit number and the block number by 1 from the 0th block of the i-th unit.

Then, the second encoding means adds a second parity symbol of pi symbols × n rows to the circular block matrix consisting of (k × m) symbols × n rows after block rearrangement, and k × m + pi) symbol × n rows of the second
Error correction code sequence is formed.

Therefore, according to the present invention, interleaving is performed in the unit of m × n row symbol blocks, so that the circuit configuration of the interleaving and the second encoding can be performed particularly by changing the configuration length of the product code and the interlace. It can be simplified without being greatly affected by the reeve length.

Further, the first encoding and the second encoding can be performed in units of 1 / L of the memory capacity necessary for forming a complete error correction code sequence. Therefore, even when performing real-time encoding processing, 1 / L of the above-mentioned encoding completion capacity, that is, one original data packet is sufficient as a memory area for storing the original data packet to be encoded next, and the memory is miniaturized. Can be achieved.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below with reference to the drawings.

FIG. 1 shows an original data packet before encoding. The original data packet is composed of (6 × 14−6) symbols × 14 rows. The data is arranged in the original direction in the row direction as indicated by the dashed-dotted line arrow in the drawing in the original data packet of 78 symbols × 14 rows. That is, 78 symbols are arranged in order from the 0th row and 0th column to the 0th row and 77th column, and then the row is updated to similarly arrange 78 symbols from the 1st row and 0th column to the 1st row and 77th column. There is.

To the original data packet matrix, first, as first encoding, 14 rows of the first 6 parity symbols Po from the 78th column to the 83rd column are added. This gives 84
An outer code 14 sequence of symbols × 14 rows is formed as a first code sequence. This first code sequence is, for example, 14 Reed-Solomon (84, 78, 7) codes.

FIG. 2 shows a procedure for forming the 14-series outer code. Here, the first of 84 symbols x 14 lines
Code sequence matrix row numbers 0 to 13 and column numbers 0 to 8
3, the row corresponding to the row number 14 is rotatably arranged as the row with the row number 0, and the rows with the row number 14 and above are handled in the first symbol sequence matrix of 84 symbols × 14 rows. Then, the i (0 ≦ i ≦ 13) -th first code sequence is obtained by increasing the row number and the column number by 1 from the i-th row and the 0-th column to the (i + 77) -th and the 77-th column of the original data of 78 pieces. Six first parity symbols Po are generated from the symbols and are obtained by incrementing the row number and the column number by 1 from (i + 78) rows 78 columns (i + 83) rows 8
It is formed by arranging as 6 symbols in up to 3 columns. Thus, as shown in FIG. 2, the first code sequence is formed by diagonally scanning a matrix of 14 symbols with 84 symbols × 14 rows. More specifically, all the 14 series of codes are formed by periodically repeating the same diagonal scanning for every 14 symbol columns, which is the number corresponding to the number of rows of the matrix. Therefore, if the second code sequence is further crossed on the first code sequence for product coding, one symbol in one code forming the first code sequence is left as it is. Only second
Cannot be included in one code constituting the code sequence of. Therefore, in the present embodiment, the second code sequence is further crossed on the first code sequence so that a product code can be formed, and at the same time, the first code sequence is interleaved in order to improve the burst error correction capability. Apply reeve.
At this time, all of the 14 series of codes forming the first code series are skillfully utilized by utilizing the property that the same diagonal scanning is periodically repeated for every 14 symbol columns, which is the number corresponding to the number of rows of the matrix. The following block interleaving is performed in which the interleave unit is a block of 14 rows × 14 columns. That is, in FIG. 2, first, the outer code 14 sequence of 84 symbols × 14 rows is set as one unit, and this one unit is divided into six blocks each having a size of 14 symbols × 14 rows. Then, as shown in FIG. 3, 6 sets of units A, B, C, D, E, which are divided into 6 blocks,
Blocks F are connected to each other in the column direction, and a block interleave process for generating a second error correction code sequence is performed using these 6 sets of units as a connected packet aggregate for complete encoding. In FIG. 3, the numbers 0 to 5 added to the symbols A, B, C, D, E, and F of each unit are block numbers.

A matrix selection method is used for block interleaving. That is, 6 blocks × 6 units = 36
Cleverly select blocks to form 6 new sets of packets with new block combinations.

Here, by rotatably arranging the unit of unit number 0 to the unit corresponding to unit number 6,
An annular block matrix that can handle unit numbers 6 and above is used. The block interleave increases the unit number and the block number by 1 from the 0 block of the i-th unit for each block forming the i (0 ≦ i ≦ 5) -th unit to the circular block matrix. It is performed by rearranging each position on the circular block matrix obtained as described above, thereby forming a new data packet for forming the second code sequence. FIG. 4 shows a result of performing block interleaving by the matrix selection method on the unit array of FIG.

After that, the second encoding is performed. That is, as shown in FIG. 5, the second parity symbol (inner code parity) Pi of 6 symbols × 14 rows is added to the matrix of (6 × 14) symbols × 14 rows, and the respective code lengths are ( Second error correction code 1 of 6 × 14 + 6) symbols
An inner code (second error correction code) sequence of 90 symbols × 14 rows is formed without forming a set of 4 sequences. The second error correction code sequence formed in this way is shown by a frame 100 of 90 symbols × 14 rows in FIG. 5, and for example, 14 sequences of Reed Solomon (90, 84,
7) A code. As shown in FIG. 6, since this calculation is performed in units of rows, it is possible to sequentially output and transmit 14 rows as the final encoded packet data.

The above second encoding process will be described again with reference to FIG. First, A0, F1, E2, D3, C4, B
A second parity symbol (inner code parity) Pi is generated for each row by using a block set consisting of 5 as a second error correction code 14 sequence, and this is added to a data packet,
An inner code sequence of (m × k + Pi) symbols × 14 rows is formed. Then, the inner code sequence is similarly formed for the block set of the next row, and thus the inner code sequence is formed for the block sets of all rows.

The first encoding process and the second encoding process described above are simultaneously performed in parallel, thereby realizing an encoding process excellent in real time.

Next, the parallel execution of the first encoding process and the second encoding process will be described with reference to FIGS. 3 and 4 again.

If the second encoding is performed on the block set of A0, F1, E2, D3, C4 and B5 and the data is transmitted and output, this area becomes empty. When an empty area occurs, the next original data packet (Gth) is input here. Then, the G-th original data packet is subjected to the first encoding, and as a result, G0, G1, G2,
A first error correction code 14 sequence consisting of G3, G4 and G5 is formed. At this time, in parallel with the first encoding, the second encoding is performed on the next block set of B0, A1, F2, E3, D4 and C5, and after the addition of the second parity symbol Pi, It is transmitted and output.

As described above, in this embodiment, interleaving is performed in the unit of a symbol block of m × n rows, and in particular, the circuit configuration of the part that performs interleaving and the second encoding is the product code configuration length. And can be simplified without being greatly affected by the interleave length.

Further, by performing the first encoding and the second encoding simultaneously in parallel, the first encoding and the second encoding are performed in order to form a complete error correction code sequence. 1 / L of the required capacity, that is, 1/6 in this embodiment can be used as a unit. Therefore, even when performing real-time encoding processing, 1 / L of the above-mentioned encoding completion capacity, that is, one original data packet is sufficient as a memory area for storing the data packet to be encoded next, and the memory is downsized. be able to.

In this embodiment, as shown in FIG.
For example, for 90 symbols for one line, which is the length of one inner code, a synchronization frame F (shaded area in the figure) is configured and transmitted with 30 symbols of one-third length as one unit. I am trying to do it. This 30-symbol synchronization frame has a frame synchronization signal (DCC + S
YNC).

Although one embodiment of the present invention has been described above, as another embodiment, as shown in FIG. 9, data in the original data packet matrix before encoding composed of 78 symbols × 14 rows is , As indicated by the one-dot chain line arrow A in the figure,
It may be arranged in the order of 13 rows to 0 rows of each column. Further, the arrangement order of each column may be reversed, and the columns may be arranged in the order of 0 to 13 rows. Further, in the formation of the 14-series outer code by the first encoding device 11, the direction of the 6-symbol × 14-row outer code parity generation operation is, as shown in FIG. 10, an oblique direction opposite to that of FIG. May be FIG. 11 shows the state of block interleaving in this case, which is basically the same as the case of one embodiment.

In yet another embodiment, 78 symbols ×
Data of 1092 symbols of the original data packet for 14 rows before encoding is 84 symbols × 1 as shown in FIG.
In the outer code matrix of 4 rows, 0 to 7 rows are arranged with 84 symbols in the order of 0 to 83 columns, and 8 to 13 rows are 70 symbols in the order of 0 to 69 columns of each row. It does not matter even if they are arranged. Although not shown in the figure, in the outer symbol matrix of 84 symbols × 14 rows,
For each block of 14 rows × 14 columns, in the first 5 blocks, 196-symbol data is arranged in the order of 0 to 14 rows in each row block, and 0 to 13 columns in each block, and 0 in the last block. The present invention can be applied even when data of 112 symbols is arranged in the order of 0th column to 13th column in a row block from the 7th row to the 7th row. In this case, the direction of the outer code parity generation operation is shown in FIG. 13 so that the 14 series outer code parities by the first encoding device 11 are generated and added to 6 symbols × 14 rows in the first block. As shown in the column direction. The state of block interleaving in this case is shown in FIG. Basically, this block interleave is the same as in the case of one embodiment.

The block interleave diagram in each of the above embodiments is a conceptual diagram, and it is not necessary to move the memory area for actual processing as shown in the diagram. It is only necessary to read / write the symbol data required for the input / output processing.

[0032]

As described above, according to the error correction coding apparatus and the error correction coding method of the present invention, interleaving is performed in the unit of a symbol block of m × n rows. It is possible to simplify the circuit configuration of the part that performs the encoding of 2 without being greatly affected by the configuration length of the product code and the interleave length. Further, the first encoding and the second encoding can be performed in units of 1 / L of the memory capacity required to form the complete error correction code sequence. Therefore, even when performing real-time encoding processing, 1 / L of the above-mentioned encoding completion capacity, that is, one original data packet is sufficient as a memory area for storing the original data packet to be encoded next, and the memory is miniaturized. Can be achieved.

[Brief description of drawings]

FIG. 1 is a diagram showing an original data packet before encoding.

FIG. 2 is a diagram showing a procedure for forming an outer code.

FIG. 3 is a diagram showing a circular block matrix of 6 units × 6 blocks.

4 is a diagram showing a result of performing block interleaving on the circular block matrix of FIG. 3;

FIG. 5 is a diagram showing a state of block interleaving according to the present embodiment.

FIG. 6 is a diagram showing a state of output transmission of final encoded packet data.

FIG. 7 is a diagram for explaining a second encoding process.

FIG. 8 is a diagram showing a structure of final encoded packet data.

FIG. 9 is a diagram showing another data arrangement order of the original data packet matrix.

FIG. 10 is a diagram showing an example of an outer code parity generation calculation order.

11 is a diagram showing a state of block interleaving when the outer code parity generation calculation order of FIG. 10 is adopted.

FIG. 12 is a diagram showing another data arrangement order of the original data packet matrix.

FIG. 13 is a diagram showing another example of the outer code parity generation calculation order.

14 is a diagram showing a state of block interleaving when the outer code parity generation calculation order of FIG. 13 is adopted.

FIG. 15 is a diagram showing an example of a product code.

FIG. 16 is a diagram showing another example of the product code.

[Explanation of symbols]

Po ... first parity symbol (outer code parity) Pi ... second parity symbol (inner code parity) 100 ... second error correction code sequence A0, A1, A2, A3, A4, A5 ... first Each block constituting the error correction code sequence A0, F1, E2, D3, C4, B5 ... Each block constituting the second error correction code sequence

Claims (15)

[Claims] 1. When k, m, and n are arbitrary positive integers and a positive integer smaller than k × m is po, (k × m)
A first parity symbol of p0 symbols × n rows is added to an original data packet composed of m−po) symbols × n rows to obtain a first error correction code sequence of (k × m) symbols × n rows. Forming a first coding means for forming the first error correction code sequence formed by the first coding means;
First divided into k blocks
Error-correcting code sequence as one unit, L units (where L is a positive integer satisfying L ≧ k) are connected to each other in the column direction, and block numbers in the row direction are 0 to k−1. When the numbers are changed from 0 to L-1, the unit of unit number 0 is rotatably arranged in the unit of unit number L-1 to form a circular block matrix that can handle units of unit number L and above. Each block on the annular block matrix obtained by increasing the unit number and the block number by 1 from the 0 block of the i-th unit for each block forming the i-th (where 0 ≦ i ≦ L−1) unit Block rearrangement means for rearranging the positions, and a plurality of original data packets to be successively transmitted in sequence, the first encoding by the first encoding means and the block A means for performing control so that the block rearrangement means sequentially performs the block rearrangement, and a circular block matrix consisting of (k × m) symbols × n rows after the block rearrangement by the block rearrangement means has a pi symbol ( However, pi is an arbitrary positive integer) × n
Add the second parity symbol in the row, (k × m + p
i) second encoding means for forming a second error correction code sequence of symbols × n rows, and matrix symbols of the second error correction code sequence formed by the second encoding means, in the row direction. To (k × m + pi
) An error correction coding apparatus, comprising: an output unit that sequentially outputs n rows for each symbol. 2. The error correction coding apparatus according to claim 1, wherein the symbol groups forming the original packet data are arranged in order in the row direction, that is, the symbol arrangement order is (k × m-po) in the row direction. ) An error correction coding device characterized by being symbols × n rows. 3. The error correction coding apparatus according to claim 1, wherein the symbol groups forming the original packet data are arranged in the column direction in order, that is, the symbol arrangement order is n in the column direction.
An error correction coding device characterized in that it is a symbol x (k x m-po) sequence. 4. The error correction coding apparatus according to claim 1, wherein a symbol arrangement order of the original packet data is m in a row direction.
Symbol × n rows × {(k × m-po) / m} times and {(k × m-po) mod m} symbols in row direction × n rows ×
An error correction coding device characterized by being once. 5. The error correction coding apparatus according to claim 1, wherein the first coding means sets a row number of a matrix of (k × m) symbols × n rows including the original data packet matrix at a left end. 0 to n-1, column number 0
From k × m−1 to the row corresponding to the row number n, the row having the row number 0 is rotatably arranged and converted into a circular matrix capable of handling the rows having the row number n or more, and the i-th first error correction is performed. The code is obtained by incrementing the row number and the column number by 1 from the i-th row and 0-th column (i + k × m−po)
-1) rows (k × m-po -1) up to (k × m-po)
) Original parity symbols are generated from p original data symbols, and (i + k × m−po) rows (k × m) are generated.
It is possible to perform code formation by arranging as p o symbols up to (i + k × m−1) rows (k × m−1) columns obtained by increasing the row number and the column number by 1 from −po) column. Characteristic error correction coding device. 6. The error correction coding apparatus according to claim 1, wherein the first coding means is a matrix element of (k × m) symbols × n rows including the original data packet matrix on the left end side. Each symbol is converted into a conversion matrix of a first error correction code n series, in which one row is rearranged so as to form one series of the first error correction code, and each row of the conversion matrix is converted. An error correction coding device characterized by generating and adding p0 first parity symbols to each of the above and re-converting into a matrix of (k × m) symbols before conversion × n rows. 7. The error correction coding apparatus according to claim 1, wherein the second coding means is for each row of a circular block matrix composed of (k × m) symbols × n rows after the block rearrangement. An error correction coding apparatus characterized by adding pi second parity symbols. 8. The error correction coding apparatus according to claim 1, wherein the first error correction code sequence of (k × m) symbols × n rows is the same as m and n. Error correction coding device. 9. The error correction coding apparatus according to claim 8, wherein the symbol arrangement order of the original packet data is n in a row direction.
Symbols × n rows × {(k × n-po) / n} times and n symbols × {(k × n-po) modn} rows × 1 in the row direction.
An error correction coding device characterized by being a round. 10. The error correction coding apparatus according to claim 8, wherein the first coding means is (k × n−po) symbols ×
Contains the original data packet matrix of n rows on the left side (k × n)
When the row numbers of the matrix of n rows of symbols are 0 to n−1 and the column numbers are 0 to k × n−1, the i-th first error correction code is the 0th row to the n−1th row of the i-th column. From the n symbols up to the n symbols from the 0th row to the n-1th row of the {(k-1) × n + i) column, and k × n symbols including the first parity symbol p o in the final part. An error correction coding device characterized by forming. 11. The error correction coding apparatus according to claim 1, wherein the values of L and k are equal to each other. 12. The error correction coding apparatus according to claim 1, wherein the output means is a fraction of an integer of (k × m + pi) symbols, which is the code length of the second error correction code sequence. An error correction coding apparatus characterized by forming a synchronization frame in which each unit is a unit. 13. The error correction coding apparatus according to claim 1, wherein the forming process of the first error correction code sequence by the first coding means and the second processing by the second coding means are performed.
An error correction coding apparatus further comprising means for performing control so that the error correction code sequence forming process of 1) is performed at the same time. 14. The error correction coding apparatus according to any one of claims 1 to 13, wherein all row and column relationships are exchanged. 15. A plurality of (k
× m−po) symbols × n rows of the original data packet, the first parity symbols of po symbols × n rows are sequentially added, and (k × m) symbols × n rows of the first parity symbols are sequentially added. And a first encoding step for forming the error correction code sequence (where k, m, and n are arbitrary positive integers, p o is a positive integer smaller than k × m), and the first encoding step is performed. Each of the matrix symbols of the first error correction code sequence formed in sequence is sequentially divided into k blocks each having a size of m × n rows, and the first error is divided into k blocks. A process of connecting L units (where L is a positive integer satisfying L ≧ k) in the column direction to each other with the correction code sequence as one unit, and setting the block number in the row direction to 0 in the unit array state after connection. To k-1 and the unit numbers from 0 to L-
When it is set to 1, the unit of unit number 0 is rotatably arranged to the unit of unit number L-1 to form a ring block matrix that can handle units of unit number L and above, and the i-th (however, 0 ≤i≤L-
A block rearranging step of rearranging each block constituting the unit of 1) to each position on the annular block matrix obtained by increasing the unit number and the block number by 1 from 0 block of the i-th unit; A circular block matrix consisting of (k × m) symbols × n rows after block rearrangement has pi symbols (where pi
Is an arbitrary positive integer) × n rows of a second parity symbol, and forms a second error correction code sequence of (k × m + pi) symbols × n rows. And an output step of sequentially outputting the matrix symbols of the formed second error correction code sequence in the row direction by (k × m + pi) symbols for n rows.