JPH07254909A - Packet transfer equipment - Google Patents

Abstract

PURPOSE:To allow both transmitter and receiver sides to detect a transmission error by allowing a master side to count a transmission data quantity and to send it, allowing a slave side to count a received data quantity and to provide a reply output at the reception of final data. CONSTITUTION:A master M adds a data size to an address part of a packet and sets a bus busy signal to be a set state and sends the resulting packet, and decrements a count of a counter 34 to which a data number is set according to a data transmission cycle. A slave S sets a received data number to a counter 6 and decrements the count of the counter 6 at each reception cycle. The slave S discriminates that the packet is received normally when the bus busy signal is set to a clear state and the count of the counter 6 is zero. Furthermore, the slave S sends a reply after receiving final data. The master M discriminates that the transfer is normally executed when the count of the counter 34 is zero at a cycle when the reply is received. Thus, even when either of the master or slave sides is faulty, since the other detects a fault the system is recovered quickly when a fault is detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet transfer device in an information processing device which uses packet transfer as information transfer means between information processing devices and as information transfer means for each of CPU, memory and IO channels in the information processing devices. .

[0002]

2. Description of the Related Art In recent information processing apparatuses, the transfer capacity of a bus is greatly related to the processing capacity. In order to improve the transfer capability of the bus, the number of bits of the bus is increased and the cycle is increased, but packet transfer of the bus is being promoted as one of the effective means.

The packet transfer on the bus is a system in which the bus is exclusively occupied only when the data transmission source (hereinafter referred to as "master") and the reception side (hereinafter referred to as "slave") can transfer data, and is very efficient. It is possible to transfer, and it is possible to send a lot of data in one transfer.

On the other hand, as a demerit, since data transmission / reception is packetized, many data cycles exist from the master to the slave, and it is necessary to confirm the normality of the data cycle to be transmitted in order to maintain reliability. It was

FIGS. 13 and 14 are diagrams showing a conventional example, and FIG. 13 is a transfer data abnormality detection time chart, FIG.
4 is a slave operation flow explanatory diagram. In the figure, a is a clock cycle, b is packet data, c is an address strobe signal, d is a data strobe signal, e is a response signal, f is a bus busy signal, g is a last data strobe signal, and h is a data reception confirmation counter value. , A indicates an address phase, D1 to D3 indicate a data phase, Aa indicates address information, Ab indicates a data size, Ac indicates a packet type, and S21 to S24 indicate respective processing numbers.

Packet transfer in the conventional method for transferring address and data on the same bus will be described below. For packet transfer, address phase A as shown in FIG.
And data phases D1 to D3. FIG. 13 shows an example in which the master outputs the packet data b in the address phase 1 cycle and the data phase 3 cycle.

In addition, the master outputs a bus busy signal f during packet transmission to notify a transfer source (master), which may be another master on the bus, that the bus is in use, and contention on the bus occurs. Control so that it does not occur.

If the output packet data b is the address phase A, the master sends the address strobe signal c indicating the address phase and the data phase D.
If 1 to D3, the data strobe signal d indicating the data phase is output.

Further, the master outputs the last data strobe signal g indicating that the data phases D1 to D3 to be transmitted are the final data D3 together with the final data phase D3.

The slave receives the address phase A by inputting the address strobe signal c output from the master, and receives the data phases D1 to D3 by inputting the data strobe signal d.

The slave outputs the address of the received packet data b and whether or not the data is normal as a response signal e. Then, the master confirms the packet transmitted by the response signal e.

Next, the conventional operation for confirming the transfer amount (the number of cycles) of the packet data b will be described with reference to FIG. First, the master adds the data size (transfer amount) Ab and the packet type Ac of the packet to be transmitted to the address phase A of the packet data b.

The slave receiving the packet address Aa analyzes the data size Ab of the address phase A and determines the number of data phase cycles (S21). The number of data phase cycles calculated in the processing number S21 is set in the data reception confirmation counter (S22).
A value obtained by subtracting 1 from the number of received data phase cycles is set in the counter after address analysis.

Since the packet data D1 to D3 are valid during the cycle when the data strobe signal d is on,
Every data reception cycle (with clock cycle),
The data reception confirmation counter set in the processing number S22 is counted down (S23).

The slave receives the last data strobe signal g indicating that the data phase sent by the master is the final data, and the data reception confirmation counter value h receives the last data strobe signal g (clock cycle). Then, it is determined whether or not it has become 0 (zero) (S24). As a result, if the data reception confirmation counter value is 0 at this timing, normal reception,
If it was other than 0, it was determined that the reception was abnormal.

The data reception confirmation counter value h in FIG. 13 shows the case of normal reception, and the counter value h is 0 at the clock cycle which is the confirmation timing of the counter value h.

[0017]

SUMMARY OF THE INVENTION The above-mentioned conventional devices have the following problems. Since the data transfer mismatch (abnormal data transfer amount) can be detected only on the slave side, the data transfer mismatch may not be detected due to the failure on the slave side. Also, when the slave side tried to receive a large amount of data due to an incorrect data size, the master side did not send the data and the waiting state sometimes continued.

An object of the present invention is to solve such a conventional problem and to improve the reliability of detection of an abnormal data transfer amount by detecting an abnormal data transfer amount on the master side.

[0019]

FIG. 1 is a diagram for explaining the principle of the present invention. In the figure, M is a master (data transmission source), S is a slave (data reception side), 6 is a data reception confirmation counter, 29 is an abnormality (error) detection circuit in the slave, 30
Is an abnormality (error) detection circuit in the master, and 34 is a transmission counter.

The present invention has the following structure to solve the above problems. In a packet transfer device for transferring packet data from a master M to a slave S using a bus, means for adding data size information to an address portion of a packet, means for indicating bus busy, and counting the number of transmitted data The master M is provided with the means 34, the means for judging the data size, the means 6 for counting the number of received data, and the means for outputting the final data reception information are provided in the slave S, and the master M receives the final data. An abnormality in the data transfer amount is detected by comparing the information with the number of transmitted data, and an abnormality in the data transfer amount is detected by comparing the means indicating that the bus is being used in the slave S and the means for counting the received data number. I chose

[0021]

The operation of the present invention based on the above configuration will be described. The master adds the data size (amount) transferred by itself to the address phase and sends it. The slave outputs the final data reception information as a reception response means of the transfer data size (amount). The master compares the final data reception information with the amount of data transferred by itself. As a result, the master can also detect the transfer amount abnormality.

As described above, it becomes possible to detect an abnormality in the amount of data transfer on the slave side and the master side, and even if one fails, the other can detect the abnormality, and when an error is detected. The recovery can be speeded up and the reliability of packet transfer can be improved.

[0023]

Embodiments of the present invention will be described with reference to the drawings.
2 to 12 are diagrams showing an embodiment of the present invention, FIG. 2 is an error detection circuit configuration diagram in a slave, FIG. 3 is an explanatory diagram of a counter set timing circuit, FIG. 4 is an explanatory diagram of a slave operation flow, FIG. 5 is a time chart when the slave is normal, FIG. 6 is a time chart when the slave is abnormal (state A), FIG. 7 is a time chart when the slave is abnormal (state B), FIG. 8 is an error detection circuit configuration diagram in the master, and FIG. 9 is the master. FIG. 10 is an operation flow explanatory diagram, FIG. 10 is a master normal time chart, FIG. 11 is a master abnormal time chart (A state), and FIG. 12 is a master abnormal time chart (B state).

In the figure, the same reference numerals as those in FIGS. 1, 13 and 14 indicate the same elements. Further, 1 is a buffer, 2 is a data buffer, 3 is an encoder (ENC), 4 is an address buffer, 5 is a data size analysis circuit, 6 is a data reception confirmation counter, 7 is a counter set timing circuit, 8 is a comparison circuit, 9 to 15 are flip-flops (FF), 16 to
18 is an AND gate, 19 and 20 are OR gates, 21 is an inverter, 31 is an address generation unit, 32 is a data buffer, 33 is a packet transfer control unit, 34 is a transmission counter, 35 is a comparison circuit, 36 is a decoder, and 37 is a buffer. , 38-45 are flip-flops (FF), 46, 4
7 is an AND gate, 48 and 49 are OR gates, 71 is an OR gate, 72 and 73 are AND gates, 74 is a flip-flop (FF), j is a transmission counter value, and k is a last data receive signal.

(Description of Intra-Slave Error Detection in Embodiment) (1) Description of In-Slave Error Detection Circuit Configuration in Embodiment FIG. 2 is a configuration diagram of an in-slave error detection circuit. In this example, the received packet data b is held in the temporary buffer 1, the address is output to the address buffer 4, and the data is output to the data buffer 2.

The data buffer 2 outputs data to a disk or the like when the slave is a disk device, for example. The address buffer 4 temporarily holds the address from the buffer 1 when the address strobe signal c is received by the flip-flop 9.

The data size analysis circuit 5 analyzes the data size with the signal from the address buffer 4 and subtracts 1 from the number of data cycles which is the analyzed data size.
The calculated value is output to the data reception confirmation counter 6.

The data reception confirmation counter 6 sets the number of data cycles from the data size analysis circuit 5 in response to the signal from the counter set timing circuit 7, and receives the data strobe signal d from the flip-flop 10 in response to the signal. It is counted down every data strobe cycle and outputs the value of the data reception confirmation counter 6 to the AND gate 18 and the OR gate 19.

The counter set timing circuit 7 outputs a one-shot signal which is turned on by the first output of the data strobe signal from the flip-flops 9 and 10.

The AND gate 18 is a circuit for detecting the counter value 1 of the data reception confirmation counter 6. The OR gate 19 is a circuit that detects the counter value 0 of the data reception confirmation counter 6.

The AND gate 17 outputs a logical product of the output of the AND gate 18 and the output of the flip-flop 10 and creates a last (final) data reception signal. This last data reception signal is output as the last data receive signal k through the flip-flop 13. The output of the AND gate 17 is encoded into a signal representing the last data receive by the encoder 3 without using the flip-flop 13 and then the flip-flop 1
It is also possible to output from 2 as a response signal e.

The OR gate 20 receives the output of the OR gate 19 and the output of the flip-flop 11 which outputs an output when the bus busy signal f is received. The output of the OR gate 20 is input to the flip-flop 14, and the flip-flop 15 is the flip-flop 14.
The output of is input.

The comparison circuit 8 receives the output obtained by inverting the output of the flip-flop 11 by the inverter 21 and the output of the OR gate 19, and outputs "1" when the two inputs do not match.
Is output.

The AND gate 16 is a flip-flop 1
It outputs a logical product of the inversion Q output of No. 5, the Q output of the flip-flop 14 and the output of the comparison circuit 8, and is turned on for one cycle when a data transfer error is detected.

The parity check PC checks the output of the address and data from the buffer 1 for error, and outputs whether the address and data are normal or not as a response signal e via the encoder 3 and the flip-flop 12. It is a thing.

The flip-flop 9 receives the address strobe signal c, the flip-flop 10 receives the data strobe signal d, and the flip-flop 11 receives the bus busy signal f.

The flip-flop 12 outputs the response signal e from the encoder 3 which generates a response code. FIG. 3 is an explanatory diagram of the counter set timing circuit, and shows an example of the counter set timing circuit 7 that generates a one-shot pulse for setting the data cycle value in the data reception confirmation counter 6.

The counter set timing circuit 7 is provided with an OR gate 71, AND gates 72 and 73, and a flip-flop 74. In the operation of the counter set timing circuit, first, the address strobe signal is input from the flip-flop 9 to the OR gate 71, and the output of the OR gate 71 is input to the flip-flop 74. The Q output of the flip-flop 74 is supplied to the flip-flop 74 via the AND gate 72 and the OR gate 71.
Is input again to hold the Q output state.

Next, when the data strobe signal is output from the flip-flop 10 to the AND gates 72 and 73, an output is output from the AND gate 73 and the Q output of the flip-flop 74 is blocked to prevent the output of the AND gate 72. Stop late.

As a result, the one-shot pulse is output from the counter set timing circuit 7 at the first output of the data strobe signal d after the address strobe signal c.

(2) Description of error detection operation in slave FIG. 4 is an explanatory view of a slave operation flow. In the figure, S1
S5 indicates each processing number. The slave operation will be described below with reference to FIG.

In the address phase A of the packet data b received by the slave, the data size Ab of the packet is added by the master. First, the slave receiving the packet address analyzes the data size Ab of the address phase A by the data size analysis circuit 5 and calculates the number of data phase cycles (S1).

The number of data phase cycles calculated in the processing number S1 is set in the data reception confirmation counter 6 (S2). The data reception confirmation counter 6 is set to a value obtained by subtracting 1 from the number of received data phase cycles.

Since the packet data is valid when the data strobe signal d is on, the data reception confirmation counter 6 set at the processing number S2 is counted down every data reception cycle (S3).

The slave is the data reception confirmation counter 6
The bus busy state when the counter value of 0 becomes 0 is determined (S4). If the bus busy signal f is off when the counter value becomes 0, the packet data b reception is normal reception, and if the bus busy signal f is on, the packet data b reception is abnormal reception (the counter value is set to a small value). , Hereinafter referred to as B state).

Further, the slave determines whether or not the counter value of the data reception confirmation counter 6 when the bus busy signal f is turned off is 0 (S5). If this counter value is 0, it is determined that the packet data b reception is normal reception, and if the counter value is other than 0, the packet data b reception is abnormal reception (a large number of counter values are set, hereinafter referred to as state A). become.

As described above, the packet data reception is normal reception only when the counter value 0 of the data reception confirmation counter 6 and the bus busy signal f are turned off at the same timing, and the error detection signal from the AND gate 16 is received. Does not occur. If either the counter value 0 or the bus busy signal f is turned off earlier, an abnormal reception occurs, and the AND gate 16 outputs an error detection signal.

FIG. 5 is a time chart when the slave is normal. The operation during normal slave reception will be described below with reference to FIG. The packet transfer is made up of the address phase A and the data phases D1 to D3. In this example,
The master outputs packets in the address phase 1 cycle and the data phase 3 cycle.

Upon receiving the packet data b, the slave uses the address strobe signal c to indicate that the packet on the bus is being output from the address phase A, and the data strobe signal d to indicate that the packet on the bus is being output from the data phases D1 to D3. It is something to detect. Furthermore, the slave is
The address of the received packet and whether the data is normal or not are output as a response signal e.

The master outputs the bus busy signal f during packet transmission. In this example, the bus busy signal f is output for another cycle after the last data phase D3 is completed, and then disappears. Here is an example.

Here, the slave receiving the packet address analyzes the data size by the data size analysis circuit 5, calculates the number of data phase cycles, and the counter 6 for data reception confirmation receives the counter value 2 in the clock cycle.
Set. This is because the one-shot pulse from the counter set timing circuit 7 is generated in the clock cycle. The counter value 2 to be set is a value obtained by subtracting 1 from the received data size. This is because the counter value of the data reception confirmation counter 6 is set to 0 in the case of normal reception at the clock timing when the bus busy signal f is turned off.

In other words, one data strobe has already been used to set the number of data phase cycles to the data reception confirmation counter, so this one is subtracted in advance.

Next, the data reception confirmation counter 6 is counted down every reception cycle of the data strobe signal d. Since the data strobe signal d is once latched in the flip-flop 10 and then input to the data reception confirmation counter 6, it is input to the data reception confirmation counter 6 with a delay of one clock cycle from the time of reception by the slave. Will be.

In FIG. 5, the counter value of the data reception confirmation counter 6 is 0 in the clock cycle in which the bus busy signal f is turned off, which means that the packet data transfer is normally received. Note that this determination is made at the timing of the clock cycle.

FIG. 6 is a time chart (A in the case of a slave abnormality)
State). Hereinafter, a description will be given of a case where the slave is abnormal, based on FIG. In FIG. 6, the number of data cycles output by the master is three, but the slave side determines that the number of data cycles is four due to some failure.

In this case, the counter value 3 is set in the data reception confirmation counter 6 in the clock cycle, and the bus busy signal f is turned off in the clock cycle. The counter value of the data reception confirmation counter 6 when the bus busy signal f is off is confirmed. In this case, since the counter value of the data reception confirmation counter 6 is 1, it is detected that a data transfer abnormality has occurred.

FIG. 7 is a time chart (B in the case of slave abnormality)
State). Hereinafter, a description will be given of a case where the slave is abnormal based on FIG. In FIG. 7, the number of data cycles output by the master is three, but the slave side determines that the number of data cycles is two due to some failure.

In this case, the counter value 1 is set in the data reception confirmation counter 6 in the clock cycle, and the counter value of the data reception confirmation counter 6 becomes 0 in the clock cycle. The state of the bus busy signal f when the counter value becomes 0 is confirmed. In this case, since the bus busy state is on, it is detected that a data transfer abnormality has occurred.

(Description of Intra-Master Error Detection in Embodiment) (1) Description of In-Master Error Detection Circuit Configuration in Embodiment FIG. 8 is a diagram showing an in-master error detection circuit configuration. In this example, the address generation unit 31 generates the address phase A in which the data size is added to the address information.

The data buffer 32 temporarily holds data to be packet-transferred. The packet transfer controller 33 controls the address generator 31, the data buffer 32, sets and counts down the transmission counter value of the transmission counter 34, and outputs an address strobe signal, a data strobe signal, and a bus busy signal.

The transmission counter 34 includes the address generator 31.
The data size (the number of data cycles) is set by the set output of the packet transfer control unit 33, and is counted down for each data transmission cycle.

The comparison circuit 35 compares the last data reception signal from the decoder 36 or the flip-flop 42 with the output of the OR gate 48 which is a counter value 0 detection circuit,
If they do not match, "1" is output.

The decoder 36 is a circuit that decodes the last data receive signal k into a last data reception signal when the last data receive signal k is input as the response signal e. Buffer 3
Reference numeral 7 temporarily holds the output from the data buffer 32 and outputs it as packet data b. The flip-flop 38 outputs the address strobe signal c, the flip-flop 39 outputs the data strobe signal d, and the flip-flop 40 outputs the bus busy signal f.

The flip-flop 41 receives the response signal e. The flip-flop 42 receives the last data receive signal k. The flip-flop 42 is not necessary when the last data receive signal k is received as the response signal e.

The flip-flop 43 receives the output of the OR gate 48, which is a counter value 0 detection circuit, and outputs it to the flip-flop 44. The flip-flop 44 outputs to the flip-flop 45 and the AND gate 46. The flip-flop 45 outputs the inverted Q output to the AND gate 46.

The AND gate 47 receives the output of the OR gate 49 and the output of the comparison circuit 35 and outputs a signal that turns on for one cycle when an error is detected. The OR gate 48 is a circuit that detects the counter value 0 of the transmission counter 34. The OR gate 49 receives the output of the AND gate 46 and the last data reception signal.

(2) Description of the error detection operation in the master FIG. 9 is an explanatory view of the master operation flow. In the figure, S11-
S16 indicates each processing number. The master operation will be described below with reference to FIG.

The address generator 31 adds the data size value to the address (S11). Next, the transmission counter 34
The packet transfer control unit 33 sets the data size value to (S12). Next, the address is sent from the data buffer 32 through the buffer 37 (S13). Next, data is transmitted from the data buffer 32 through the buffer 37, and the count value of the transmission counter 34 is counted down every time this data is transmitted (S14).

The master determines whether or not the last data receive signal in the next cycle in which the counter value of the transmission counter 34 becomes 0 (S15). If the last data receive signal k is on, it is determined that the packet transmission is normal, and if the last data receive signal k is off, the packet transmission is abnormal.

Further, the master judges whether the transmission counter value of the transmission counter 34 before the cycle in which the last data receive signal k is turned on is 0 (S16). If the transmission counter value is 0, the packet transmission is normal, and if the transmission counter value is other than 0, the packet transmission is abnormal.

As described above, packet transmission becomes normal only when the last data receive signal k is turned on in the cycle following the cycle in which the transmission counter value becomes 0, and FIG.
In this example, the AND gate 47 does not output an error detection signal. However, in other cases, an error occurs and an error detection signal is output from the AND gate 47.

FIG. 10 is a time chart when the master is normal. The operation when the master is normal will be described below with reference to FIG. The packet data b consists of an address phase A of 1 cycle and data phases D1 to D3 of 3 cycles. If the packet on the bus is outputting the address phase A, the master outputs the address strobe signal c, and the data phase If D1 to D3 are being output, the data strobe signal d is output.

The slave outputs a response signal e indicating whether the address and data of the received packet are normal. In this example, the slave responds with a delay of two cycles. Further, in this example, the slave outputs the last data receive signal k at the cycle next to the timing when the counter value of the data reception confirmation counter 6 is 1 and the flip-flop 10 of the data strobe signal d is on (that is, countdown logic) in this example. It is a thing.

The master sets the transmission data size value 3 in the transmission counter 34 and counts down every data transmission cycle. Then, as shown in FIG. 10, the master determines that the packet transmission is normal when the last data receive signal k is turned on in the cycle following the cycle in which the counter value of the transmission counter 34 becomes zero.

Note that this determination is made in a clock cycle, and in FIG. 8, it is made by the comparison circuit 35, flip-flops 43 to 45, AND gates 46 and 47, or OR gate 49, and when an error is detected, the AND gate is used. Four
An error detection signal that turns on for one cycle is output from 7.

FIG. 11 is a time chart of the master abnormality (A
State). In the following, a master abnormality will be described with reference to FIG. FIG. 11 shows an example in which the number of data cycles, which is the data size output by the master, is 3 cycles, but the slave side determines that it is 4 cycles due to some failure.

In this case, the last data receive signal k is not turned on in the next cycle in which the counter value of the transmission counter 34 becomes 0 in the clock cycle. This is confirmed in the clock cycle and it is judged that the packet transmission is abnormal.

FIG. 12 is a time chart of the master abnormality (B
State). In the following, a master abnormality will be described with reference to FIG. In FIG. 12, the number of data cycles, which is the data size output by the master, is three, but this is an example of the case where the slave side determines that there are two cycles due to some failure.

In this case, the last data receive signal k is turned on in the clock cycle. Therefore, it is determined in the clock cycle whether the count value of the transmission counter 34 in the clock cycle before the last data receive signal k is turned on is 0. In this case, transmission counter 3
Since the counter value of 4 is 1, it is determined that the packet transfer is abnormal.

(Other Embodiments) The embodiments have been described above, but the present invention can be implemented as follows. (1) In the above embodiment, the data reception confirmation counter 6 and the transmission counter 34 are used by counting down, but it is also possible to set a complementary value at the time of setting and counting up. That is, either a count-up or a count-down can be performed if the counter indicates the final data value.

(2) Even if the transfer protocol of the above embodiment is not used, it can be implemented by changing the confirmation cycle. (3) When the bus busy signal is turned on, packet transfer is started, and the address and data transmission timings are fixed. Even in a packet transfer protocol that does not have an address strobe or a data strobe, the address data size information and the bus busy signal Can be implemented by using.

[0082]

As described above, the present invention has the following effects. (1) Since the transfer abnormality of the bus for packet transfer is detected on the master side and the slave side, even if one fails, the other can be detected, and the reliability is improved.

(2) By detecting packet transfer abnormality on the master side, when an error occurs, the master side can quickly perform error recovery such as preparation for data retransmission.

(3) The last data strobe signal can be omitted by using the bus busy signal.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram of an error detection circuit in a slave according to an embodiment.

FIG. 3 is an explanatory diagram of a counter set timing circuit according to the embodiment.

FIG. 4 is an explanatory diagram of a slave operation flow according to the embodiment.

FIG. 5 is a time chart when the slave is normal in the embodiment.

FIG. 6 is a time chart (state A) when a slave is abnormal in the embodiment.

FIG. 7 is a time chart (state B) when a slave is abnormal in the embodiment.

FIG. 8 is a configuration diagram of an error detection circuit in a master in the embodiment.

FIG. 9 is an explanatory diagram of a master operation flow according to the embodiment.

FIG. 10 is a time chart when the master is normal in the embodiment.

FIG. 11 is a time chart (state A) when the master is abnormal in the embodiment.

FIG. 12 is a time chart (state B) when the master is abnormal in the embodiment.

FIG. 13 is a transfer data abnormality detection time chart of a conventional example.

FIG. 14 is an explanatory diagram of a slave operation flow of a conventional example.

[Explanation of symbols]

 6 Data Reception Confirmation Counter 29 Abnormality Detection Circuit in Slave 30 Abnormality Detection Circuit in Master 34 Transmission Counter M Master (Data Transmission Source) S Slave (Data Reception Side)

Front page continued (72) Inventor Junji Hirooka, 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor, Ryo Matsuda 1015, Ueda-anaka, Nakahara-ku, Kawasaki, Kanagawa

Claims (5)

[Claims] 1. A means for counting the number of packet data to be transmitted in a packet transfer device for transmitting and receiving packet data using a bus.
And a means for receiving final data reception information from the destination of the transmitted packet, and a means for comparing the final data reception information with the number of transmitted data. 2. A packet transfer device for transmitting and receiving packet data using a bus, means for judging the data size of a packet from the data size information added to the address part of the received packet, and detecting that the bus is in use. Means, a means (6) for counting the data reception cycle based on the data size, a bus state by means for detecting the busy state of the bus, and a reception cycle by the means (6) for counting the data reception cycle And a means for comparing with each other. 3. A means for confirming the counter value of the means for counting the number of received data at the timing when the bus busy signal is turned off, and a counter value for the means for counting the number of received data,
3. A bus busy signal status confirmation means at the timing when the final data reception value is reached.
The packet transfer device described. 4. A counter value confirmation means for confirming the number of transmitted data at the timing when the signal of the final data reception information is turned on, and a counter value confirmation means for confirming the counter value of the transmitted data when the signal becomes the final data transmitted value. The packet transfer device according to claim 1, further comprising: a final data reception information status confirmation means. 5. The packet transfer apparatus according to claim 1, wherein the final data reception information is defined as a code in a response signal for data reception.