JPH07250330A - Hierarchical coding transmission system and transmitter-receiver - Google Patents

Abstract

PURPOSE:To simplify the configuration of the hierarchical transmitter-receiver. CONSTITUTION:A demultiplexer 104 demultiplexes data Le1 subject to forced refresh among data compression coded by a video image coder 103 as high importance data and the demultiplexed data are processed by a channel of an FEC coder 107 having a high error correction capability, other data Le2 is processed by an FEC coder 106 and multiplexed by a multiplexer 108 and a modulator 108 and the result is transmitted. A signal demodulated by a demodulator 203 at a receiver side is separated into data Le1, Le2 by a demultiplexer 204, they are decoded by FEC decoders 205, 206 respectively and multiplexed by a multiplexer 209 and decoded by a video decoder 210. The content of frame compensation is changed in the video decoder 210 depending on error flags 1, 2 and the configuration of the transmitter-receiver is simplified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for encoding, compressing, transmitting and receiving image data.
In particular, the present invention relates to a hierarchical coding transmission / reception system and device in which error countermeasures are strengthened and the hardware scale is reduced.

[0002]

2. Description of the Related Art FIG. 8 shows a high-efficiency compression coding apparatus for performing compression coding processing on a video signal by a hybrid discrete cosine transform (DCT) method including motion prediction coding.
That is, the luminance signal Y and the color signal C respectively input to the input terminals 11 and 12 are processed by the preprocessing circuit 13 in units of blocks (8 × 8 pixels = 64 pixels) each including 8 pixels in the horizontal direction and 8 pixels in the vertical direction. , After the pixels are rearranged, they are supplied to the subtraction circuit 14 and the motion vector detection circuit 15, respectively. The subtraction circuit 14 performs a subtraction process described later, and the output thereof is input to the DCT circuit 16. The DCT circuit 16 fetches pixels in the block unit and outputs a coefficient obtained by converting the pixel array from the time domain to the frequency domain.

Each coefficient output from the DCT circuit 16 is
The quantization circuit 17 quantizes the signal to a finite level. In this case, the quantization circuit 17 has 32 types of quantization tables, and each coefficient is quantized based on the selected quantization table. In the quantization circuit 17,
The quantization table is provided so that the amount of generated information and the amount of transmitted information are within a certain range.

The coefficient data output from the quantizing circuit 17 is zigzag-scanned from the low band to the high band for each unit block and is extracted, and then is input to the variable length coding circuit 18 to continue the zero coefficient. Variable length coding is performed by using a number (run length) and a non-zero coefficient as one set. The encoder is
This is a variable-length encoder whose code length differs depending on the frequency of occurrence of Huffman code and the like.

The variable-length coded data is input to the buffer memory 19 and read at a prescribed speed, and then supplied to the next stage multiplexer (not shown) via the output terminal 20 and sent to the transmission path. It Buffer memory 19
Is a variable rate output of the variable length coding circuit 18,
Since the rate of the transmission path is a fixed rate, it serves as a buffer that absorbs the difference between the generated code amount and the transmitted code amount. Further, the data indicating the memory occupation amount of the buffer memory 19 is supplied to the quantization circuit 17 and is used for selection of the quantization table, so that the buffer memory 19 is controlled so as not to overflow.

The output of the quantization circuit 17 is the inverse quantization circuit 2
It is input to 1 and inversely quantized. Further, the output of the inverse quantization circuit 21 is input to the inverse DCT circuit 22 and returned to the original signal. This signal is delayed by the frame memory 24 via the adder circuit 23. Frame memory 2
The output of 4 is supplied to the motion compensation circuit 25 and the motion vector detection circuit 15, respectively.

The motion vector detection circuit 15 compares the preprocessed signal with the output signal of the frame memory 24, detects the overall motion of the image, and detects the phase position of the signal output from the motion compensation circuit 25. To control. The output of the motion compensation circuit 25 can be supplied to the subtraction circuit 14 via the switch 26, and can also be fed back from the addition circuit 23 to the frame memory 24 via the switch 27. Switch 2
The switches 6 and 27 are on / off controlled based on the refresh signal supplied to the input terminal 30.

The basic operation of this encoding means is a refresh (intra-frame compression encoding) process and a non-refresh (inter-frame compression encoding) process. When the refresh process is performed, both switches 26 and 27 are controlled to be in the off state. The pre-processed signal is converted from the time domain to the frequency domain by the DCT circuit 16 and quantized by the quantization circuit 17. The quantized signal is subjected to a variable length coding process and then is subjected to a buffer memory 19
Is output to the transmission line via.

The quantized signal is returned to the original signal by the inverse quantization circuit 21 and the inverse DCT circuit 22, and delayed by the frame memory 24. Therefore, at the time of refresh processing, it is equivalent to that the information of the input video signal is variable length coded as it is. This refreshing process is performed in a proper cycle in units of predetermined blocks and scene changes of the input video signal.

When the non-refreshing process is performed, both switches 26 and 27 are controlled to be in the ON state. Therefore, the subtraction circuit 14 obtains a signal (prediction error signal) corresponding to the difference between the input video signal and the prediction signal obtained by motion-compensating the video signal one frame before with the motion vector. This difference signal (= prediction error signal) is DC
It is input to the T circuit 16, converted from the time domain to the frequency domain, and quantized by the quantization circuit 17.
Since the differential signal and the video signal are added to the frame memory 24 by the adder circuit 23 and input, a predicted video signal that predicts the input video signal that is the source of the differential signal is created and input. It will be.

As described above, there are two conditions under which the switches 26 and 27 are turned off and the refresh process is performed. One is a case where the amount of data is smaller when the original signal is transmitted only by the quantization and the compression by the variable length coding than the difference signal, such as in the case of a scene change. This is performed by the prediction switching circuit 29 by the motion compensation circuit 25 and the preprocessing circuit 1.
When the difference signal is calculated from the output signal (original signal) of No. 3, the difference signal and the original signal are compared, it is judged that the amount of data to be transmitted decreases, and if it is judged that intra-frame compression is better, the frame Generate an internal compression flag. This processing is performed in DCT macroblock units.

Another condition relates to error propagation in differential prediction. The necessary condition for normal decoding from the differential signal is that the previous frame is normally decoded. Therefore, if the previous frame is not normally decoded due to an error that has occurred in the transmission path, the decoding of the current frame and the subsequent frames is not normally performed, and the error propagation continues. In order to prevent this, the forced refresh process is periodically (for example, 10 frame periods), and the original signal is compressed and transmitted. This timing depends on the forced refresh flag input from the terminal 30. The logical sum of the forced refresh flag and the in-frame compression flag is taken by the OR circuit 28 and used as a refresh signal for turning on / off the switches 26 and 27. The forced refresh flag and the intra-frame compression flag are multiplexed with the compression encoded data and transmitted. The origin of the refresh comes from the operation of stopping the predictive coding based on the difference and refreshing as described above. Therefore, the process when the switches 26 and 27 are turned off is called a refresh process.

FIG. 9 shows a high-efficiency decoding device for performing a decoding process on the video signal compression-coded as described above. That is, the compression-encoded video signal supplied to the input terminal 29 is temporarily stored in the buffer memory 30, read by the variable length decoding circuit 31 at a variable rate, and then the inverse quantization circuit 32 and the inverse DCT circuit. At 33, the original signal is restored.

The output of the inverse DCT circuit 33 is the addition circuit 34.
After that, the post-processing circuit 35 performs a pixel rearrangement process opposite to that at the time of pre-processing, so that a luminance signal Y and a color signal C are generated and taken out from the output terminals 36 and 37.
The output of the adder circuit 34 is delayed by the frame memory 38 and then input by the motion compensation circuit 39 to the input terminal 40.
Is subjected to motion compensation processing based on the motion vector supplied to the adder circuit 34 and is supplied to the adder circuit 34 via the switch 41. The switch 41 is on / off controlled based on the refresh signal supplied to the input terminal 42.

When the video signal at the time of refresh processing is supplied to the input terminal 29, the switch 41 is controlled to the off state, the output of the inverse DCT circuit 33 passes through the adding circuit 34, and then the switch 43 normally operates. It is located on the n side, is subjected to post-processing by the post-processing circuit 35, is taken out from the output terminals 36 and 37, and is stored in the frame memory.
When the prediction error signal at the time of the non-refreshing process is supplied to the input terminal 29, the switch 41 is controlled to the ON state, and the output of the inverse DCT circuit 33 is added to the video signal stored in the frame memory 38. After that, the post-processing circuit 35 performs post-processing, takes out from the output terminals 36 and 37, and stores it in the frame memory.

The error compensation is performed as follows, for example. The error compensation signal is usually an external error detector (FEC
(Foward Error Correction) It is often included in the decoding unit) (error flag).

FIG. 10 shows an example of the timing of error compensation for interpolation in the previous frame. A forced refresh period is shown, and the leading I data (forced refresh frame data) and the following P data (predictive coded data) are present in this period. The figure shows a state in which an error has occurred in the predictive coded data P12 and an error flag has occurred.

Normally, the switch 43 of FIG. 9 selects the n side and inputs the compressed and decoded data to the post-processing circuit 35. For a frame in which a large number of error flags have been generated and contains an error, the switch 43 becomes the f side by the previous frame interpolation signal and uses the data of the previous frame as video decoded data.

Assuming that an error occurs in the data P12 as shown in FIG. 10, basically in error compensation or the like, error propagation occurs until the next forced refresh frame data I2 arrives, and normal decoding cannot be performed. . Therefore, the data P11 of the previous frame is repeatedly used.

The error compensation judgment means 44 counts the error compensation signal (error flag) inputted from the terminal 45 by the frame timing signal and the forced refresh flag, and when it judges that an error has occurred within the forced refresh cycle, A front frame interpolation signal for performing the front frame interpolation processing is generated until the end of the cycle. In actual implementation, when the error flag is input corresponding to the frame position of the input compressed data, two types of the frame timing signal and the forced refresh timing are required. That is, the one corresponding to the timing of the input compressed data is represented by (... 1), and the one corresponding to the timing of the video decoded data is represented by (... 2). The error flag is counted by the internal counter of the error compensation determination means 44 using the frame timing 1 for each frame of the input compressed data, and when the value exceeds a value designated in advance, an output signal (internal counter output) is generated. This output signal is cleared at the rising timing of the forced refresh flag 1.

Since the video decoded data has a time difference due to the decoding delay from the input compressed data, the output of the internal counter is delayed by the frame timing 2 by the time delay to generate the preceding frame interpolation signal, and the switch 43 is switched to f. Turn it to the side.

Next forced refresh frame data I2
Is received without error, it can be decrypted normally.
The previous frame interpolation signal is cleared and returns to normal operation. At this time, the video decoded data after error compensation is repeatedly output for 9 frames of P11.

By the way, in recent years, a hierarchical structure of transmission information has been proposed especially for mobile broadcasting. this is,
This is to cope with the situation that the reception state changes every moment due to many multipaths caused by shadows of buildings in urban areas. In this mobile reception, even by the error compensation,
The time rate during which normal reception is possible becomes extremely small, and the screen changes occasionally, resulting in a still image reception state, which is not very enjoyable as broadcast reception. One way to deal with this is to reduce transmission errors by stronger FEC encoding, but generally strong FEC is used.
The higher the redundancy, the wider the frequency bandwidth is required, which is uneconomical.

In the layered coded transmission, the information source is divided into two layers, for example, one with a high degree of importance and one with a low degree of importance, and only those with a high degree of importance are transmitted on a channel having a good transmission error characteristic. .

FIG. 11 shows the structure of conventional hierarchical coding transmission. This is called pyramid coded transmission, and two types of devices for coding an information source (video signal) can be prepared.

The video signal input from the input terminal 51 is compression encoded by the video encoding device 53 and output as the signal Le2. This signal Le2 is decoded by the video decoding device 55, and the subtracter 54 calculates the difference from the source signal. The differential signal from the subtractor 54 is compression encoded by the video encoding device 56 and transmitted as the signal Le1.

In general, the video encoding device 53 handles low-quality signals instead of high compression rate, and it is assumed that basic images can be transmitted. The video encoding device 56 compresses and encodes information excluding the basic image signal and transmits it. Therefore, even if only the information (Ld2) corresponding to the signal Le2 can be received on the receiving side, a reasonable image can be viewed. Further, assuming that the information (Ld1) corresponding to the signal Le1 can also be correctly received, it is possible to obtain an image quality (high quality) faithful to the original video signal.

The signal Le2 containing the basic image information is input to the weighting transmitter 57 and is encoded by the FEC encoder 59 having a strong correction capability because it has a high degree of importance. On the other hand, the signal Le1 including the additional information is encoded by the weaker FEC encoder 58 because it is less important. The respective FEC encoded outputs are multiplexed by the multiplexer 60, modulated by the modulator 61, and output from the output terminal 6
2 and is transmitted.

Assuming that the correction capability of the FEC coding used when the layers are not hierarchized is medium, the video coding device 56,
By appropriately selecting 53 and the FEC encoders 57, 57, hierarchical encoding can be realized with almost no increase in transmission rate.

The operation on the receiving side is as follows. The received signal is input to the demodulator 73 via the input terminal 71 and demodulated. Demultiplexer 74 converted to digital data
FE corresponding to the FEC encoders 58 and 59.
It is input to the C decoders 75 and 76. Here, the previous signal L
The signals Ld1 and Ld2 corresponding to e1 and Le2 are decoded. The signals Ld1 and Ld2 are supplied to the video coding devices 56 and 5, respectively.
3 is input to and decoded by the video decoding devices 79 and 80. Error flag 2 output from the FEC decoder 76
Is directly used as an error compensation signal of the video decoding device 80. On the other hand, the error flag 1 output from the FEC decoder 75 may be used as the error compensation signal of the video decoding device 79, but is input to the determination means 78 separately. The determining means 78 turns off the switch 81 when the error flag 1 occurs at a frequency exceeding a prespecified value Th1 so that the video signal output only by the signal Ld2 is obtained at the output terminal 83. This is because when the signal Ld1 contains many errors, the video decoding device 7
This is because the image quality is better when the decoded output of 9 is not used. Normally, Th1> Th2 is set to have a hysteresis characteristic.

When the occurrence frequency of the error flag 1 is lower than the preset value Th2, the switch 81 is turned on. At this time, the outputs of the video decoding devices 79 and 80 are added by the adder 82, and are output to the output terminal 83 with high image quality. With this configuration, even a certain degree of transmission error can be received with low quality, and the service range of broadcasting can be expanded.

[0032]

In the conventional hierarchical coding system, the video coding device and the video decoding device are required for each of the layers, which is very uneconomical. An object of the present invention is to provide a layered coding transmission system and apparatus in which error countermeasures are strengthened and the required video coding apparatus and video decoding apparatus are reduced, and in particular, the hardware scale of the receiving side can be reduced. .

[0033]

SUMMARY OF THE INVENTION According to the present invention, a video signal is compression-encoded by a hybrid discrete cosine transform (DCT) method including motion prediction encoding to obtain compressed data, and the compressed data is important. When a plurality of streams are separated into layers according to the degree of difference and the compressed data of the respective streams are transmitted through transmission channels having different characteristics of error correction capability, when performing the compression coding process, the intra-frame is periodically used. The compressed data subjected to the compression process (hereinafter referred to as I data) is hierarchized as the most important data, and this I data is transmitted through the transmission channel having the best characteristic among the above transmission channels.

In the present invention, only one out of every N pieces of I data (I (N) data) is hierarchized as the most important data and is transmitted by a transmission channel having the best error correction capability. Is.

The present invention also provides the I data or I
(N) Multiplex data multiple times, layer as the most important data, and transmit on the transmission channel with the best characteristics,
The receiving side selects and decodes data received without error from the multiplexed data. Further, according to the present invention, the most important data is interleaved and transmitted.

[0036]

According to the above structure, the information source can be hierarchized only by the demultiplexer that separates only the forced refresh data. On the receiving side, the layered video can be decoded only by multiplexing the error flag and the compressed data for each layer. In addition, since the amount of important data transmitted can be reduced to 1 / N, a stronger FEC
Coding is available. Furthermore, by transmitting the data of high importance a plurality of times, the time rate of the transmission can be improved and the probability of correct reception can be increased. Also,
By interleaving and transmitting data of high importance, normal reception is possible even with only a part of the screen.

[0037]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 shows an embodiment in which the number of layers is 2, and shows a transmitting side and a receiving side. The video signal is input to the video encoding device 103 of the layered video encoding device 102 via the input terminal 101.

The compressed data Le compressed and encoded by the video encoder 103 is input to the demultiplexer 104, and the forced refresh data Le2 which is interframe compression-encoded by the forced refresh and the other data Le1.
And is input to the weighting transmitter 105 at the next stage. Since the forced refresh data Le2 is data of high importance, FE that performs FEC encoding with strong correction capability
It is input to the C encoder 107. Further, the data Le1 is input to the FEC encoder 106 that performs weaker FEC encoding. The data encoded by the encoders 106 and 107 are multiplexed by the multiplexer 108, and the modulator 10
The signal is modulated at 9, output to the output terminal 110, and sent to the transmission line.

On the receiving side, the signal input to the weighting receiver 202 via the input terminal 201 is the demodulator 203.
The demodulated data is input to the demultiplexer 204 and separated into data Le1 and Le2. The data Le1 and Le2 are input to the FEC decoders 205 and 206 and decoded. Corrected and decoded data Ld1, L
The d2 is converted into compressed data Ld by the multiplexer 209 and input to the video decoding device 210. The error flags 1 and 2 are also time-division multiplexed by the multiplexer 208 to become error compensation signals, which are input to the video decoding device 210.

FIG. 2 shows an example of timing for error compensation. The configuration of the video decoding device 210 is the configuration shown in FIG. 9, and the basic operation of the error compensation determination means is performed as described in FIG. If the error is large, the signal of the previous frame is used.

In FIG. 2, the forced refresh period R
An example is shown in which the transmission state gradually deteriorates to 1, R2, R3, and R4. There is a hierarchy in how the error flags 1 and 2 occur. That is, in the forced refresh period R1, only the data P12 has an error, so the data sequence after the video decoding after the error compensation is interpolated at P11 of the previous frame. In the period R2, the condition of the transmission line deteriorates further,
Data other than the data I2 will be wiped out. Therefore, the frame interpolation in the period R2 depends on the data I2. Period R3
Is similarly interpolated with the data I3.

In the period R4, the state of the transmission line is further deteriorated and the data I4 cannot be normally received. In this case, the error flag 2 will be generated. At this time, the interpolation signal in the period R4 is interpolated by the data I3 transmitted in the previous forced refresh period. Period R5
Shows that the state of the transmission line has improved a little and the data I5 can be normally received. In this case, the data I5 is received.
Interpolated by 5. At this time, the screen changes from the contents of the data I3 to the contents of the data I5. During the period R6, the condition of the transmission line is further improved, and the data I6, the data P61, and the data P62
Is received normally, and the data P62 indicates that interpolation is being performed.

As described above, hierarchical video decoding can be realized with the same structure of the video decoding device. The output data Le of the video encoding device 103 can be set to a fixed rate by the rate control by the buffer memory 19 and the quantizing circuit 17 in FIG. 8, but after being separated into the data Le1 and Le2, the respective rates are set. Fluctuates a little. Therefore, the weighted transmission device 105 needs to have some margin in the transmission rate of each layer.

(Second Embodiment) In the above embodiment, all the forced refresh data are transmitted in a layer having a good transmission error characteristic. However, the present invention is not limited to this. For example, the importance of the forced refresh data may be increased once in every two frames, and the data may be transmitted in a layer having a good transmission error characteristic.

Although the configuration of this embodiment is the same as that of FIG. 1, the demultiplexer 104 separates the forced refresh data into the data Le2 side once every two frames. Then, the transmission rate of the data Le2 becomes half as compared with the first embodiment. Then, the redundancy of the FEC encoder 107 can be increased, the coding rate can be halved, and stronger FEC coding can be used.

The operations of the demultiplexer 204 and the multiplexers 208 and 209 on the receiving side are also controlled so that the forced refresh data is separated and synthesized once every two times. In this case, compared with the first embodiment, the change point of the screen is reduced depending on the state of the transmission path, but the range of the broadcast service is expanded.

(Third Embodiment) FIG. 3 shows an example of processing timings on the transmitting side and the receiving side when data of high importance is transmitted a plurality of times (twice). The compressed data Le consists of forced refresh data (I data) and predicted data (P data). Demultiplexer 301 (FIG. 4A)
Shows the separation of P data and I data, but outputs I data twice. To this end, the demultiplexer 301 has a switch 302, as shown in FIG.
It has a P memory 303 for obtaining time adjustment of P data, an I memory 304 for obtaining time adjustment of I data, and a switch 305 for obtaining selection of I data. As a result, the P data and the I data are P as shown in FIG.
It is transmitted with I data arranged on both sides of the data.

On the receiving side, one of the I data sent twice is normally received (based on the error flag 2) and is multiplexed as the data Ld. The structure of the multiplexer 311 at this time is shown in FIG. Multiplexer 3
Reference numeral 11 denotes an I memory 312, a switch 313 to which I data is input, an output (I data) from the switch 313,
And a multiplexing unit 314 that multiplexes P data.

Since the P data is delayed in advance, a huge P memory is unnecessary and only I data is needed. The switch 313 selects the output of the I memory 312, for example, when an error flag 2 for I data sent later occurs. At this time, if the I data sent earlier is normally received, the correct I data is multiplexed on the data Ld.

FIG. 5 shows the multiplexers 301 and 31 described above.
1 shows a system with 1. The same parts as those in FIG. 1 are designated by the same reference numerals. When an error occurs in both, the multiplexer 311 of FIG. 5 outputs an error flag at the position of the I data.

Further, the I data may be transmitted a plurality of times with respect to the I data once every N times, as described in the second embodiment. In this case, (N-1) times of I data and N times of P data are included in a group of P data of FIG.

(Fourth Embodiment) FIG. 6 shows the processing timing when interleaving is performed. This timing chart is based on the two-time transmission method of I data shown in the third embodiment.
This is a combination of the interleave schemes.
Since there is an interleave delay and a delay of sending twice, the delay in the P memory needs to be double the delay in the third embodiment.

In interleaving, for example, I data is divided into an upper half (Ih) and a lower half (Ie) of the screen and dispersed on the time axis and transmitted. Il (lower half) and Ih (upper half) are transmitted twice as I data with P data interposed therebetween. Moreover, as shown in FIG. 5, the combination of half I data is not the same screen but the combination of the previous and current forced refresh data.

In the timing chart on the receiving side in FIG. 6, an example in which an error occurs in the portion marked with x is shown. in this case,
Even if the data corresponding to the two forced refresh cycles is erroneous, I1l, that is, the lower half of I1 can be correctly received, and in this example, only the lower half of the period R1 (even P data) can be decoded almost normally. become. The interleave processing and the deinterleave processing are performed using the I memory shown in FIG.

Furthermore, the interleaving / deinterleaving may be applied to the forced refresh data obviously once every N times. (Fifth Embodiment) FIG. 7 shows an example in which the present invention is applied to pyramid coding.

In this embodiment, the number of layers is three. Figure 11
When configuring hierarchical coding transmission by pyramid coding in which the number of layers is 3, the apparatus of 3 requires three video coding / decoding devices. By combining the present invention as shown in FIG. 7, the required number of video encoding / decoding devices can be set to two.

A video signal is input to the input terminal 401,
Video coding apparatus 403 of layered video coding apparatus 402
Is supplied to the subtractor 404. Video encoding device 403
Is output from the video decoding device 405 and the demultiplexer 40.
7 is supplied. The output of the video decoding device 405 is input to the subtractor 404 and subtracted from the source signal of the input terminal 401. The difference signal output from the subtractor 401 is input to the video encoding device 406. Video encoding device 406
The compressed data Le1 output from the weighted transmission device 4 is
It is input to the FEC encoder 409 of 08. The demultiplexer 407 separates the forced refresh data Le3 from the other data Le2, supplies the data Le2 to the FEC encoder 410, and outputs the forced refresh data Le3 to the FE.
It is supplied to the C encoder 411. Each FEC encoder 40
The outputs of 9, 410, and 411 are multiplexed by the multiplexer 413, modulated by the modulator 414, and sent to the transmission path via the output terminal 415.

The signal arriving through the transmission path is input to the demodulator 503 via the input terminal 501 and demodulated.
The demodulated data is input to the separator 504, and Le1, Le
2, separated into Le3 data. Data Le1, Le2, Le
3 is input to the FEC decoders 505, 506, 507, respectively, and decoded. The decoded data output from the FEC decoder 505 is input to the video decoding device 513 of the layered video decoding device 508 and the FEC decoders 506 and 507.
Each decoded data output from the layered video decoding device 5
It is input to the multiplexer 514 of 08. Also, FE
The error flag 1 output from the C decoder 505 is input to the determination unit 509, and the error flags 2 and 3 output from the FEC decoders 506 and 507 are the multiplexer 5
Input to 10. The output of the determination unit 509 can control ON / OFF of the switch 515 provided between the output of the video decoding device 513 and the adder 517. Further, the output of the multiplexer 510 is supplied to the video decoding device 516 as an error compensation signal. The video decoding device 516 is
The data Ld from the multiplexer 514 is decoded. The output of the switch 515 and the output of the video decoding device 516 are added by the adder 517, and are output to the output terminal 518.

According to the above system, as the state of the transmission line deteriorates, first the error flag 1 starts to occur, the switch 515 is turned off, the output of the video decoding device 513 is cut off, and the image quality of the video signal output is medium. It will be about. When the condition of the transmission line deteriorates further, an error flag 2 occurs,
The transmission process begins to work, and it becomes a pseudo movie in some places (low quality).
Further, when the error flag 3 occurs, the screen is updated only occasionally (the service limit is reached). Although the forced refresh signal is used to control the error compensation determination means 44 in FIG. 9 in the above embodiment, it may be connected and controlled as indicated by the dotted line.

[0060]

As described above, according to the present invention, a hierarchical transmission and reception system can be constructed with a simple structure. In addition, the video encoding / decoding device can be used almost as it is when it is not hierarchized.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram shown for explaining an example of an error compensation operation of the apparatus of FIG.

FIG. 3 is a diagram for explaining the basic operation of the third embodiment of the present invention.

FIG. 4 is a diagram showing an example of a demultiplexer and a multiplexer used in the present invention.

FIG. 5 is a diagram showing a configuration according to a third embodiment of the present invention.

FIG. 6 is a diagram for explaining the basic operation of the fourth embodiment of the present invention.

FIG. 7 is a diagram showing the configuration of a fifth embodiment of the present invention.

FIG. 8 is a diagram showing a high-efficiency compression encoding device used for video encoding.

FIG. 9 is a diagram showing a video decoding device.

FIG. 10 is a diagram for explaining a compensation operation of the video decoding device.

FIG. 11 is a diagram showing a conventional hierarchical encoding / decoding device.

[Explanation of symbols]

102 ... Hierarchical video coding device, 103 ... Video coding device, 104 ... Demultiplexer, 105 ... Weighting transmitting device, 106, 107 ... FEC encoder, 108 ... Multiplexer, 109 ... Modulator, 202 ... Weighting receiving device , 203 ... Demodulator, 204 ... Demultiplexer, 20
5, 206 ... FEC decoder, 207 ... Layered video decoding device, 208, 209 ... Multiplexer, 210 ... Video decoding device, 301 ... Demultiplexer, 311 ... Multiplexer.

Claims (12)

[Claims] 1. A video signal is subjected to compression coding processing by a hybrid discrete cosine transform (DCT) method including motion prediction coding to obtain compressed data, and the compressed data is divided into a plurality of streams depending on the importance. When the compressed data of each series is separated and hierarchized and transmitted through transmission channels having different characteristics of error correction capability, when the compression encoding process is performed, the compressed data obtained by periodically performing the intraframe compression process ( A hierarchical coding transmission method characterized in that (I data) is hierarchized as the most important data, and this I data is transmitted through the transmission channel having the best characteristic among the above transmission channels. 2. Only one of every N of the I data (I
2. The hierarchical coding transmission method according to claim 1, wherein (N) data is hierarchized as the most important data and is transmitted through a transmission channel having the best error correction capability. 3. The I data or I (N) data is multiplexed a plurality of times, hierarchized as the most important data, transmitted on a transmission channel having the best characteristics, and at the reception side, the multiplexed data 3. The hierarchical coding transmission system according to claim 1, wherein data received without error is selected and decoded. 4. The method according to claim 1 or 2, wherein the most important data is interleaved and transmitted.
Or the layered coding transmission method described in 3. 5. A video signal is subjected to compression coding processing by a hybrid discrete cosine transform (DCT) method including motion prediction coding to obtain compressed data, and the compressed data is divided into a plurality of streams depending on the importance. In a device that separates and hierarchizes the compressed data of each series through transmission channels having different characteristics of error correction capability, compressed data obtained by periodically performing the intraframe compression process when performing the compression coding process ( A demultiplexer for layering (I data) as the most important data, and a weighted transmission device which is supplied with the output from the demultiplexer and transmits the I data on the transmission channel having the best characteristic among the transmission channels. A hierarchical coding transmission device comprising: 6. The demultiplexer separates only one out of every N pieces of the I data (I (N) data) as the most important data and hierarchically separates it. Layered coding transmission device. 7. The hierarchical coding transmission device according to claim 5, wherein the demultiplexer includes a multiplexing circuit that multiplexes the I data or I (N) data a plurality of times. 8. The hierarchical coding transmission apparatus according to claim 5, wherein the demultiplexer includes an interleaving circuit that interleaves the most important data. 9. A video signal is subjected to compression coding processing by a hybrid discrete cosine transform (DCT) method including motion prediction coding to obtain compressed data, and the compressed data is divided into a plurality of sequences depending on the importance. When the compressed data of each series is separated into layers and transmitted by transmission channels having different characteristics of error correction capability, the compressed data subjected to cyclic intraframe compression processing (hereinafter, I data)
Is layered as the most important data, and the I-data receives a signal transmitted by a transmission channel having the best characteristic among the transmission channels, and a receiving unit for outputting the output of the receiving unit for each of the plurality of layers. Weighted decoding means for separating signals into respective layers and decoding signals of respective layers, first multiplexer means for multiplexing decoded I data and decoded data of other layers, and respective layers obtained from the weighted decoding means Second multiplexer means for multiplexing an error flag indicating the presence or absence of an error, and video decoding means for video decoding the data from the first multiplexer means by using the output from the second multiplexer means as an error compensation signal. A hierarchical coding receiving apparatus comprising: 10. As for the I data, only one for every N data (I (N) data) is hierarchized as the most important data and is transmitted by a transmission channel having the best error correction capability. And the first multiplexer means is
10. The layered coding receiver according to claim 9, wherein the I (N) data and the decoded data of another layer are multiplexed. 11. As the I data, the I data itself or the I (N) data is multiplexed a plurality of times, and hierarchized as the most important data. 11. The layered coding receiving apparatus according to claim 9, further comprising a switch unit for selecting data received without error among decoded data corresponding to the data multiplexed by times. 12. As the I data, the I data itself or the I (N) data is interleaved and multiplexed to be layered as the most important data, and the first multiplexer means 12. The hierarchical coding receiving apparatus according to claim 9, further comprising a selecting unit that selects data received without error from corrected and decoded data corresponding to the interleaved data.