JPH0724414B2 - Loopback test method - Google Patents

Description

DETAILED DESCRIPTION [Overview] A loopback test is provided with a random pattern detector on the receiving side of a loopback terminal and a random pattern generator on the transmitting side, and phase matching during loopback is performed with a simple configuration. To be realized.

[Industrial application field]

The present invention relates to a loopback test method in high-speed multiplex communication, and more specifically, it is performed for each channel returned at an arbitrary return terminal in a system in which a plurality of information channels are time-division multiplexed and bidirectionally transmitted. Regarding the improvement of the loopback test.

With the progress of digital communication technology, time division multiplex communication is widely used. A loopback test is an important function that must be provided in order to realize this digital multiplex communication.

In such a loopback test, one of the two-way signals is folded back to the other at each transmission terminal station for the purpose of isolation at the time of failure and check at the time of line opening, and whether the test signal sent from a certain station is correctly returned. It is done to check whether or not.

For example, as shown in FIG. 5, the PN signal (random pattern) is inserted from the tester 42 only in the information channel to be tested in the A station 41, and the R direction (A Return from station to station B) to direction S (station B to station A). Then, by separating the channel at the A station 41 and inputting it into the tester 42,
It is possible to check whether or not the transmitted PN signal is correctly returned.

The frame structure of the information transmitted between the stations is, for example, as shown in FIG.
It is assumed that each of the information channels (H _{0 to} Hn) and the housekeeping (H _K ) channel is included. The information channel is a high-speed signal of tens to hundreds of bits, and the H _K channel is used for a loopback instruction and transmission of terminal status.

At the station A, a command indicating which channel of H _{0 to} Hn is to be folded back is inserted into the H _K channel, and the station B receives it and executes the folding back as instructed.

As the information and communication services have become more sophisticated,
The need for it is increasing.

[Conventional technology]

Conventionally, as shown in FIG. 7, for example, the frame transmitted from the A station 41 is synchronized by the frame synchronization unit 1, and the pulse generator (PG) 2 is activated by this output. In addition, H _K channel decoder (H _K CH DEC) 3
Synchronizes with the pulse generator 2 and decodes the contents of the H _K channel. When the content of this decode 3 is a loopback command (for example, channel i), the decoder 3 causes the loopback pulse generator 4 to generate a loopback pulse (a pulse having a phase in the S direction of channel i), and causes the selector (SEL) 6 to SIN. To the variable delay memory 5, and the contents of the memory 5 are output as SOUT. For that purpose, the memory 5 includes the pulse generator 2
The channel information i transmitted from the A station 41 is taken in by the pulse from the pulse generator and the pulse generator (PG) 8 is input at the timing when the folding pulse from the folding pulse generator 4 is input.
It is controlled so that the channel information taken in the variable delay memory 5 is output in the corresponding channel time zone on the folding side in synchronization with the clock from (which is frame-synchronized by the frame synchronization unit 7).

Generally, the frame phases in the R direction and the S direction are arbitrary, and it is necessary to match the phases in order to return a certain specific channel in the R → S direction. In order to take this timing, the variable delay is performed in the above-described operation mode. The memory 5 is used.

In this case, it is necessary to consider the maximum delay amount for one frame.

[Problems to be solved by the invention]

In this conventional apparatus, when the number of frame bits per frame increases, a delay amount proportional to the number of bits is required, the variable delay memory has a large capacity, and the hardware becomes extremely large. For example, 8 KHz at a transmission rate of 140 Mb / s
In the case of frames, one frame has 17500 bits, which is very large birdware.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a loopback test method capable of performing a loopback test with a small amount of bird wear.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the loopback test method of the present invention.

In the figure, 3 is a decoder for decoding the channel to be looped back.

Reference numeral 4 represents a folded pulse generator.

10 detects a random pattern (PN) signal from the R side
It is a PN detector.

11 is a predetermined time series PN in response to the aliasing pulse
It is a PN generator that generates a pattern.

Reference numeral 9 is a PN generator 10 and a loopback control section for switching the input by a loopback pulse.

[Work]

The PN signal received by the return station is detected by the PN detector 10,
A detection signal is generated when it matches a predetermined time series pattern.

When the decoder 3 decodes the channel to be looped back and the folding pulse generator 4 generates a folding pulse, the folding control unit 9 switches the input to the PN generator 11 side and generates from the PN generator 11. The PN pattern to be transmitted is sent to the loopback test station.

In the present invention, the loopback test can be performed without using a delay memory by detecting the PN signal at the folding station and inserting the PN signal in the folding channel at a predetermined timing.

〔Example〕

FIG. 2 shows an embodiment of the present invention, in which the PN generator 11 uses the circuit of FIG. 3 and the PN detector 10 uses the circuit of FIG. Note that the same reference numerals are used for the same elements as those in FIG. 7, and thus redundant description will be omitted.

As shown in FIG. 3, the PN generator 11 includes an AND gate 111 that ANDs a clock CLK and a folding pulse, a shift register 112 that is shifted by the output of the gate 111, and NAND gates 113 and 114 that receive the output of the register 112 as inputs. Gate
NOR gate 115 which takes the logic of the outputs of 113 and 114, exclusive OR gate 116 which takes the exclusive OR of the output of the 7th stage and the output of the 15th stage of shift register 112, the logic of the outputs of gate 116 and gate 115 It is composed of a NOR gate 117, and generates a PN pattern signal represented by a generator polynomial (Y = X ¹⁵ + X ⁷ +1).

The PN detector 10 is, as shown in FIG. 4, an AND gate 101 that takes the logical product of a clock CLK and a channel pulse, a D-type flip-flop 102 that operates by data and the output of the gate 101, and an inverter that inverts the output of the gate 101. 103,
Exclusive OR gate 104, D-type flip-flop 105 that operates by the output of gate 104 and the output of inverter 103, AND gate 106 that takes the logical product of the output of gate 101 and the output of flip-flop 105, and the same configuration as in FIG. PN generator 107.

The PN signal sent from the tester via station A is the PN detector.
In 10, the contents are collated with the pattern of the PN generator 107, and when they match, a “0” level signal is output. At this time,
The channel to be detected by the decoder 3 is designated by the channel pulse CHP, and the folding pulse generator 4 designates the channel number to be folded back.
The folding pulse generator 4 receives this channel number and generates a folding pulse in the corresponding channel phase in the S direction based on the timing in the S direction from PG8.

The PN detector 10 outputs a "0" level signal, and the pulse generator 4
Outputs a "1" level signal (folding pulse), the AND gate 12 outputs a "1" level signal, and the selector 6
Switch to the PN generator 11 side. At this time, the above-mentioned folding pulse is given to the PN generator 11. The generation timing of the folding pulse coincides with the phase of the S-direction test target folding channel, and the PN pattern generated by the PN generator 11 has the same content as the PN pattern generated in the tester 42. Therefore, when the PN pattern sent to the SOUT line via the selector 6 is input to the tester 42 via the A station 41, it can be seen that the loop is functioning normally.

It should be noted that the same technique can be implemented for wireless channels as well.

〔The invention's effect〕

As described above, according to the present invention, it is possible to perform a loopback test with a simple configuration without using a variable delay memory. In particular, when targeting high-speed signals, the conventional delay memory configuration requires a very large capacity memory and is not suitable for LSI, etc., but the present invention requires less hardware, Easy LSI
There is an advantage that can be realized.

[Brief description of drawings]

1 is a block diagram showing the principle of the loopback test method of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, FIG. 3 is a detailed circuit diagram of a PN generator 11 according to the present invention, and FIG. Is a detailed circuit diagram of the PN detector 10 according to the present invention, FIG. 5 is an explanatory diagram showing an outline of a multiplex communication system, FIG. 6 is an explanatory diagram of a frame structure in multiplex communication, and FIG. 7 is a conventional loopback test. It is explanatory drawing of a system. In FIGS. 1 and 2, 1,7 is a frame synchronization unit, 2,8 is a pulse generator, 3 is a housekeeping channel decoder, 4 is a folding pulse generator, 6 is a selector, 10 is a PN detector, 11 Is a PN generator, and 12 is an AND gate.

Claims (1)

[Claims] 1. A method of performing a loopback test in units of channels between arbitrary transmission terminal stations of a multiplex communication system in which a plurality of information channels are time-division multiplexed and bidirectionally transmitted between the transmission terminal stations. A decoder (3) for decoding a channel to be processed, a pattern detector (10) for detecting a match between a received random pattern inserted in the channel obtained by the decoder (3) and a preset pattern. )
And a random pattern (PN) generator (11) for generating the same random pattern corresponding to the received random pattern by a return pulse indicating a return timing.
In response to the pattern detector (10) detecting that the patterns match each other, a random pattern from the random pattern generator (11) is applied to a folding channel to the test side with respect to the designated channel by a folding pulse. A loopback test method comprising a loopback test (9) for inputting to the test side and performing a loopback test for each channel.