JPH07240723A - Digital audio-memory communication system - Google Patents

Abstract

PURPOSE: To perform transmission and play-back at different speeds by providing a signal conversion circuit for converting digital data to analog data and a timing circuit for clock operating signals for indicating a voice message from a memory at a second data speed. CONSTITUTION: The receiver 14 of this digital voice storage system 10 receives an incoming signal to input it to a decoder 16 and the decoder 16 emit an enable signal when an input signal code matches with a decoder address. A control means 18 for switching, resetting and controlling the circuit of the system 10 controls and activates the system 10 in response to the enable signal from the decoder 16. The incoming signal is converted from analog to a digital format in a signal conversion means 20 and stored in the memory 22 and the means 18 calls the message from the memory 22, converts it from digital to analog for reproduction and outputs it through an audible amplifier 24 to a speaker. The decoder 16 is provided with a timer, ends the enable signal when the time set beforehand is ended in response to the timer and stores a new message in the memory 22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication system, and more particularly to transmitting an analog signal at a certain speed, converting the transmitted analog signal to digital for digital storage, and differentiating the transmitted data. It relates to a system for searching and reconverting such signals into analog format for playback at speed.

[0002]

BACKGROUND OF THE INVENTION The prior art is full of various types of paging and radio operated systems, where messages can be left for individuals who cannot be contacted directly for any reason. For example, many paging systems work with large complex central processing functions where messages are queued,
It is usually transmitted to the subscriber in digital form together with the subscriber's address code. A subscriber to a service has a paging unit pre-programmed to activate by receiving a message preceded by an address code for the paging unit. The pager emits an audible tone to inform the subscriber that the message has been received and stored for that person. The messages are placed in pager memory and the messages are typically retrieved in the form of display messages on an LED or LCD display screen. While such systems are effective and require very little air time to send digital messages, the messages transmitted always have a limited duration, and generally have the subscriber It is a type that requires you to go to the phone and call the message originator. In addition, alphanumeric messages require a special terminal to enter this alphanumeric message to be transmitted, unless the message to be transmitted is strictly numeric, that is, telephone numbers and the like. Types of paging systems require expensive computerized central message equipment.

Other paging systems are available which use a transmitter which transmits in a analogue form a voice message preceded by an address code which is received by a preprogrammed receiver. The message is played back as soon as it is received, and depending on the unit, the message can be recorded in a tape cassette for playback again. This type of pager is usually relatively cumbersome and requires substantially high power requirements to drive the mechanical parts of the tape recorder.

In the field of telephony, one or more is used to stream a message to a caller to inform them that the calling party is not available to answer the call and to record the message for later playback. Responsive devices provided with tape cassettes are available. Although answering machines are readily available with the use of single wires and their price is becoming less expensive, such devices are not normally available as part of the telephone circuit itself, and are more Most are bulky and require a substantial amount of tabletop space. Furthermore, answering machines are not readily available on multi-line business telephones and combined line records.

Another form of message service is the so-called voice memory retrieval system (VMS), in which voice messages are left in the central message storage facility and subscribers use specific codes to access the memory of the central computer. You can retrieve the message. These systems are expensive to operate in that they require a powerful computer at the central system facility to process and store messages, and because subscribers have to look for phones to receive messages. It is also inconvenient to use. Moreover, the recipient may inadvertently receive the message because the recipient inadvertently does not check the message.

In the field of two-way wireless communications, such as police and fire communications, emergency communications and the like, many systems are handheld when the recipient is sometimes away from the mobile unit. The use of a receiver, a walkie-talkie, is employed, which is applied to the mobile receiver so that the operator can receive incoming messages while away from the unit. Such devices are expensive and in many cases are completely unnecessary if reliable and inexpensive message storage systems are available at the mobile unit. Systems similar to telephone answering machines are also available for transmitting pre-recorded messages and for recording incoming messages when the operator is not at the mobile unit. These systems have been found to be bulky, unreliable, and inflexible in connecting to wireless communications.

A more sophisticated system is Burk.
e) and other U.S. Pat. No. 4,468,813 and Burk et al., U.S. Pat. No. 4,495,647. This system requires a base unit and sends a command program packet in digital form to the mobile unit, which is programmed to respond to the command program to receive messages in analog form. In response to the command program, the mobile unit converts the message into digital form for storage,
In response to the end command sent by the base unit in digital form, the mobile unit recording system is deactivated. The operator at the mobile unit can then play the digital message in analog form. The system disclosed in the aforementioned US patent requires a sophisticated coding system at the base transmitter and must be able to generate command program packets and termination code signals. Furthermore, the base transmitter must be able to transmit command packets in the manner described in the above patent. The mobile unit must be able to receive and decode the command program packet and transmit its command program packet back to the base unit. Mobile units used in such systems require two separate power sources,
This makes it unsuitable for portable handheld receivers such as pagers and the like.

Moreover, in the field of communications, especially in wireless communications, transmission times are preferably kept to a minimum. In wireless communication, the available channels are crowded, so there is considerable competition for transmission time. For this reason, most paging systems are involved in the transmission of messages in digital form, as digital formats require less time to transmit. However, the messages received are limited to short write messages that are displayed on the small LED and LCD display screens, and the messages are usually of the type that requires the subscriber to reach the phone and call the message originator. Is limited.
In addition to the limited messaging capabilities of such systems, the transmission components are expensive and typically require centralized computer messaging equipment to transmit digital data and store analog messages for subscribers. And

Therefore, an analog message is transmitted directly to the remote unit, which analog message is transmitted at a high rate to save transmission time, received and recorded at the remote unit to return the message to its audible state. It is highly desirable to provide a system that can be played back at a slower rate rate. Of course, it is also desirable to transmit specific analog data at a slower rate and play the message at a higher rate to return it to its audible format again. Such a transmission procedure is expediently performed in the transmission of music and other high fidelity analog data over telephone lines, which usually affects the fidelity of the transmitted data in a detrimental manner. In such cases, it is desirable to transmit the data at a slow rate to maintain fidelity and play at normal speed without loss of fidelity.

[0010]

SUMMARY OF THE INVENTION In accordance with the present invention, a digital voice storage communication system is provided, at least one transmission station for selectively addressing and transmitting a communication packet containing an address code followed by a voice message, and a corresponding predetermined predetermined station. At least two receiving stations having stored addresses stored therein, each of which is (1) a receiving circuit responsive to said communication packet; (2) a recording active connected to said receiving circuit and responsive to said communication packet. A decoder for generating a signal, and (3) a digital memory for storing the voice message of the communication packet in response to the recording active signal at a first data rate, the improvement being digital data to analog data. And a signal conversion circuit for converting to the first data rate Data representing the stored voice message from the digital memory at a second data rate, characterized in that it comprises a timing circuit for operation clock that.

In accordance with the present invention, there is provided an analog-to-digital data storage system which can be readily used in paging systems, telephones, multi-line telephones, cellular telephones, extension telephones, telemetry systems, two-way radio and the like. An analog signal, given a voice message, is transmitted at a first rate, received, converted to a digital format and stored in memory in a digital format, retrieved and reconverted to an analog format and played at a second rate. Be backed.

The data storage system is easily installed in existing telephones and wireless devices at low cost and operates with very low power requirements. Data storage systems include, for example, digital code, signal tones, dual tone multifrequency (DTMF).
It can be applied to be activated by any conventional analog or digital address encoder such as, and can also be voice activated (VOX). No specially modified transmitter is required for use of the system of the present invention. In addition, means for deactivating the circuit after receipt of the message are included in the data storage system itself, with the exception of the address code (which is preferred but not critical), and allows the receiving unit to receive and record the message. It is not necessary to transmit a packet of command data for control and an end code at the end of the message for deactivating the receiving unit.

In accordance with the invention, the analog-to-digital data storage system includes receiver means for receiving an incoming signal carrying analog components from a suitable transmitter.
The analog signal is preferably preceded by a designated address code that is unique to the particular data memory system. The system further includes active means activated by the incoming signal to issue an active signal (logical high) to activate system circuitry as described and illustrated below. The active means may include a decoder programmed to recognize an address code that is unique to a particular receiver or group of receivers. The active means can be activated by an incoming signal without an address code to emit an active signal, as in the case of a VOX circuit. The system includes conversion means for converting the incoming analog data into a digital format and memory means for storing the converted digital data. The conversion means further includes circuitry for reconverting the digital signal to analog format. The control means are provided for activating the conversion means and the digital memory storage means in response to the active signal from the decoder means. In the preferred embodiment, the control means also serves to deactivate the conversion means and the memory means upon completion of the message or after a predetermined period of time. Switching means are included for activating the conversion means and the memory means for playing back the stored message in analog format. The system includes switching means for manually activating record and playback modes,
Amplifier means for listening to the incoming analog signal and playing back the stored message.

The system of the present invention can be readily used in wire communication systems such as single and multi-line telephone systems, extension communication systems and wireless communication. Therefore, the system of the present invention is useful for paging systems, two-way wireless communications, cellular telephones, traditional telephone extension communication systems and telemetry systems. In a preferred form of the invention, the system receives such messages at a slow rate after being retrieved from memory in order to receive analog messages that are transmitted at high speed, and so that the messages can be understood by the mobile operator. Applied for playback. In this manner, air transit time is substantially reduced, which is in paging systems where the specified frequencies are limited and in areas where radio frequencies are congested, such as when there are many subscribers using the system. Critically important.

According to one embodiment of the invention, the system comprises transmitter means including a control terminal for inputting data and a transmission buffer in communication with the transmitter for sending analog messages. The system further includes a receiver group that includes a receiver compatible with the transmitter to receive the transmitted signal, a format that stores the received signal in memory and retrieves the signal from memory to use it. It includes a circuit for converting to. It is understood that the signal rate conversion can occur before storing the signal in memory, or after signal retrieval from memory but before playback. Further, the signal can be transmitted at a rate, recorded at a second rate, and played back at a third rate. Preferably, the coding means at the transmitter buffer codes an address code which can be recognized by a group of receivers so that the message can be sent to a particular receiver.

The system of the present invention is applicable for use in wireless communication as well as wire communication systems such as single and multi-line telephone systems and extension communication systems. The system is particularly useful for paging and telemetry systems, and also for systems that carry music and other data where high fidelity is required. The system of the present invention uses conventional transmitter and receiver devices, such as commercially available paging devices, and easily installed circuitry.

[0017]

Detailed Description of the Preferred Embodiment Referring to FIG.
An analog-digital data memory system, generally designated 10, is shown and constructed in accordance with the present invention including a power supply 12 and receiver means 14 for receiving an incoming signal. The receiver means 14 may include a wireless communication receiver such as used in an audible paging system or a two way wireless communication system, or may be a telephone or similar type device. As such, a transmitter (not shown) is included in system 10. The incoming signal received by the receiving means is transmitted from a compatible transmission device (not shown), which is specifically modified for use in the receiver means 14 of the audio storage system 10, as will be explained later. do not have to. Transmission media may be hardwire or wireless, eg wireless, infrared or fiber optic. Active means 16 are provided in the decoder circuit and compare the incoming signal with the decoder address to determine whether the incoming message signal is addressed to the system 10. The active means 16 can be adapted to monitor various types of coded addresses such as digital codes, tone codes, or dual tone multi-frequency (DTMF). When the received signal code matches the decoder address, the decoder 16 issues an active signal (pulse or continuous signal), which activates the record / store function of the voice storage system 10. The use of address codes with incoming messages is not critical, and may be a voice activation device that issues an active signal upon receipt of an audio message, if desired. In one embodiment of the invention, the decoder 16 is designed to emit a continuous active signal for the duration of the incoming analog signal, the signal ending at the end of the analog signal. The termination of the active signal from the decoder 16 is used for other parts of the circuit in the manner described in more detail below to deactivate the circuit of the system 10 and return it to the standby mode. In another embodiment of the invention, the decoder 16 issues a single pulse upon detecting an incoming message addressed to the system 10 and timer means are provided to allow a predetermined period of time from the first active pulse. And then put the system back into standby mode.

The control means 18 for switching, resetting and controlling the circuitry of the system 10 is the decoder 16
Responsive to active signals from the voice memory system 1
0 controls and activates various circuits. The incoming signal is passed to the signal conversion means 20, converted from analog to digital format, passed to the memory means 22 and stored in memory in digital format. Control means 18
Also includes switching circuitry to activate the voice storage system 10 independent of active signals to recall stored messages from memory and reconvert the messages from digital to analog format for playback.

Audio amplifier means 24 are provided to monitor incoming and retrieved voice messages from memory. Input means 17 is provided to put messages directly into the control means 18 for conversion and storage by the receiver operator.

Referring to FIG. 2, there is shown a schematic diagram of the circuitry used in the control means 18, the signal conversion means 20 and the memory means 22 of the data memory system 10 shown in FIG. As shown in FIG. 2, certain optional features of system 10 are shown in phantom, system 10 is operable without any features, and the selection of any particular feature incorporated into a circuit is: It should be understood that it is a matter of choice depending on the nature of the receiver in which the system is installed and the operating parameters selected for the system.

Power supply 12 includes any suitable source of power and preferably has a potential of at least 3 volts. The control means 18 includes a decoder 16 (not shown) via an input logic buffer 26 and a logic blocking circuit 56.
To communicate electrically with. Logic blocking circuit 56, which is a conventional diode design, distributes an active signal (logic high) to microprocessor 32 via start line 30 and record / play line 31. If the active means 16 is of the type that issues a continuous logic high for the duration of the analog signal, completion of the analog signal will automatically cause the system 10 to return to standby mode, as indicated by the end of the logic high. It is strongly preferred to include circuitry for. To this end, trailing edge detector 42 is connected to logic inverter 46, which is connected to microprocessor 32 via stop line 48, the purpose and operation of which will be described in more detail below. The output analog signal is routed through the analog output coupling 95 of conventional design to the microprocessor 32.
Is output from. Audio switch 66 is line 98
Connected to the microprocessor 32 to monitor incoming analog signals during the recording mode. A positive edge detector 36 may be included to automatically reset the system 10 so that the sender can record on top of the message already in memory, where a logic high is from the logic blocking circuit 56. It is conveyed by the line 34. Leading edge detector 36 is of conventional design and is connected to microprocessor 32 via reset switch 38, capacitor 39 and reset line 40.

The playback switch 58 is connected to the switching controller 60. The switching controller 60, shown more clearly in FIG. 3, includes a resistor 11 in a bistable (two steady state) circuit of conventional design.
It consists of an inverter 112 and an inverter 114 coupled by 6 and 118, the outputs on lines 102 and 160 of which are normally low until inverted by activation of switch 58 to initiate playback mode. The output of switching controller 60 remains high until reset switch 108 inverts it to its normal low.

Digital-to-analog conversion and analog-
Digital reconversion is accomplished by the microprocessor 32. Microprocessor 32 is of a commercially available design, such as manufactured by Toshiba as model number T6668, and is provided in the circuit for analog-to-digital conversion and digital-to-analog reconversion. Such conversion circuits are well known in the art and generate an internal time base to sample the analog signal input at some predetermined point in each time base segment, then sample taken during the sampling period. It works by producing a digital output that is responsive to the level. Up to 4 microprocessors 2
Applied to communicate with a 56K bit chip 78,
It has a total of 1024 Kbits of memory. In the embodiment of the invention shown in FIG. 2, using all four RAM chips 78, the system 10 can store up to 128 seconds of voice messages at a bit rate of 8K bps. Additional memory banks may be added as desired or needed, especially if the receiver operator is to make large amounts of message recording, for example when system 10 is used as a dictation unit.

In operation, analog messages, audio or data are transmitted from a transmitter (not shown) to receiver means 14 (shown in FIG. 1). The message may be transmitted by any suitable means such as wire or wireless and is preferably by a designated address code of commonly used type such as tone, DTMF, digital or the like. Is preceded by. The analog signal received by the receiver means 14 is transmitted to the active means 16 and an active signal (logic high) is passed through the input logic buffer 26 if the appropriate designation code is present or if the active means 16 is a VOX circuit. Issue to logic blocking circuit 56. In the embodiment of the invention described thus far, the decoder 1
6 is of the type that emits a continuous logic high for the duration of the incoming analog signal. A logic high goes through the logic blocking circuit 56 to the start line 30 and record / write.
It is conveyed from the playback line 31 to the microprocessor 32. In addition, the logic blocking circuit 56 conveys a logic high on line 34 to the leading edge detector 36 and pulses to close the reset switch 38. In the closed state, the reset switch 38 completes the circuit and discharges the capacitor 39, momentarily pulling the reset line 40 to a logic low, initializing the microprocessor 32 to receive a new message and resetting the memory. . Incoming analog signals, described as voice messages for purposes of illustration, are transmitted to analog-to-digital conversion circuitry of microprocessor 32 via input audio coupling 96. After the analog signal is converted to digital format, the converted signal is then transferred to RAM chip 78.
And is stored in the memory. When the analog signal ceases to be received, active terminates the logic high and activates the trailing edge detector 42, making it a logic low. A logic low is shown on line 44 to logic inverter 46 which inverts the low to a logic high which is conveyed to microprocessor 32 via stop line 48 to complete the conversion and recording process. The end of a logic high returns the start line 30 and the record / play line 31 to their original standby logic low state, placing the system 10 in a standby mode, which requires very little power.

To retrieve and play back the digital message stored in RAM 78, the receiver operator activates playback switch 58 and switching controller 60 drives a logic high to line 160,
Issue to microprocessor 32 via logic blocking circuit 100, line 104 and start line 30 to activate the playback reproduction function.

At the same time, system controller 60 outputs a logic high on line 102 to simultaneously switch 6
Close 2 and 66. The signal reconverted to analog format is from the microprocessor 32 by line 98 via the audio switch 66 and output audio coupling 95 to the amplifier means 24 (shown in FIG. 1).
Directed to. Upon completion of message reproduction and playback, microprocessor 32 sends a logic high to reset switch 108 via line 110. Reset switch 108 resets switching controller 60 to its original state and returns its output to a logic low, returning switches 66 and 62 to the open state. At this point, system 10 is in standby mode and is ready to receive new incoming signals for conversion and storage.

It is understood that in the embodiments of the invention described so far, there is no means for protecting the messages in memory, and upon receipt of an appropriately addressed incoming signal, the system will automatically reset. , The incoming signal is converted and stored on top of the message or data already in memory. However, by the addition of a memory address selection circuit, by a selective reset circuit or a manual reset circuit that must be activated to start the message recording and conversion mode after the memory is full of unplayed messages or data. And with memory expansion, the system 10 is easily adapted for recording successive messages in memory and protecting stored messages.

As shown in FIG. 2, the positive edge detector 36
Is removed from the system 10 and the reset switch 38 is reset in the manner previously described to reset the memory for recording over material already stored in the memory,
Manually activated to re-initialize microprocessor 32. Up to 3 additional RAM chips 78 (R
AM 2, RAM 3, and RAM 4) can be added to the extended memory. A memory address selector 50, which is a standard 4-bit code counter circuit, is connected to the microprocessor 32, as shown most clearly in FIG. 3, to allow selection of 16 different 4-bit address combinations. However, it is understood that other address selector circuits such as 2-bit counter circuits or manual selectors can be used, as is well known in the art. Message address selector 50 is connected to start line 30 to receive a logic high from logic blocking circuit 56. System 1
0 requires no further reset to record multiple messages until each memory bank is full, until a stop activity occurs in the microprocessor 32 and the memory for that bank is reset. Be protected. A manual reset switch 75 is provided to reset the message address to its initial address setting for playback of the message stored in memory. Message playback occurs in the manner previously described, but without the leading edge detector 36 in the circuit, resets the microprocessor 32 to receive the new incoming analog signal and record it on top of the message already in RAM. In order to do so, the reset switch 38 must be manually activated to discharge the reset line 40 in the manner previously described.

In an alternative form of the invention (shown in FIG. 3), system 10 may optionally use a timer 52 in place of trailing edge detector 42. The use of a timer is especially necessary when the decoder 16 is of the kind that issues a single pulse in response to an appropriately addressed incoming signal.

The timer 52 is started by a logic high by connecting line 53 to line 43 to receive a logic high from the input logic buffer 26, and when the predetermined period of time expires, the timer 52 turns on the logic inverter 46. Issue a negative pulse, which issues a logic high on stop line 48, placing system 10 in standby mode in the manner previously described.

As shown in FIG. 2, the system 10 may include a message indicator 54 which may indicate the arrival of signals and may also indicate that the memory space is full. The message indicator 54 is a light or LED
Alternatively, it may be a device for generating an audible signal sound. Such devices are well known in the art and as such do not form part of the invention.

The system 1 shown in FIGS. 2 and 3.
The 0 embodiment optionally includes a record / playback speed circuit, which allows the system to receive, convert and record a message at a 1-bit transmission rate and play the message back at a different bit transmission rate. The maximum bit rate per second is determined by the particular microprocessor used in the system.

As most clearly shown in FIG.
The speed circuit includes inverters 68 and 70, which are connected to the microprocessor 32 by lines 74 and 76, respectively. The speed selector 72 including the speed selector switches 72a and 72b is connected to the inverters 68 and 70. As best seen in FIG. 3, speed selector 72 is connected by line 79 to the output of switching controller 60 on line 160 for control of playback speed.

As shown, the speed selector switch 7
Both 2a and 72b are open, producing low inputs and high outputs at inverters 68 and 70 so that both lines 74 and 76 are high. In this state, the microprocessor has the same speed, in this case 3
Record and play back at 2K bps. When playback switch 58 (shown in FIGS. 2 and 3) is closed, the high output from switching controller 60 is passed to the speed selector via line 79,
This activates and closes the speed selector switch 72a, causing the inverter 68 to output a high. In this configuration, the output of inverter 68 is low and line 74
Low, while the output of inverter 70 is high, causing line 76 to go high. With this configuration, the microprocessor plays back the message at a rate of 16K bps. The bit rate output is selected by a 2-bit code and during recording and playback the rate selector switches 72a and 72b (lines 79 and 81).
Four speeds are selectable depending on the positioning of the.

At any point to manually control the operating mode of the system 10 so that the receiver operator can play back the message and return the system 10 to the standby mode to receive additional messages or data. Playback can be interrupted.

Referring to FIG. 6, a typical design capacitive memory circuit 300 includes a capacitor 301 and a resistor 3
It consists of 02. Capacitive memory circuit 300 includes line 16
The playback switch 58 causes the output of 0 to change state with each momentary closure of the switch 58.
Is connected to the switching controller 60. When the playback switch 58 is closed, the line 160 of the switching controller 60 goes high and the line 10
4 and line 30 logic high to microprocessor 3
2 (shown in FIG. 2) to activate the system in playback mode. The second closure of switch 58 causes a high to low line transition which is conveyed to trailing edge detector 42. The trailing edge detector 42 initiates a signal to the logic inverter 46 which inverts the signal to a logic high which is conveyed to the microprocessor 32 via the stop line 48 to terminate the record and data conversion mode and to terminate the system 10. Return to the standby mode in the manner described above.

As mentioned above, the system of the present invention allows the operator to send messages to memory either for playback by the operator or for subsequent broadcasts when the system is used in two-way communication. Useful as an "electronic scratch pad" so that it can be dictated. The manual recording function is provided by the second capacitive memory circuit 300 ', which is the manual recording switch 5
9, the second switching controller 60 ', and the second
Connected to the reset switch 108 '. As shown, the manual recording circuit complements the manual playback circuit. However, closing the manual record switch causes the switching circuit to issue a high signal on line 34 to the leading edge detector 36 which initiates a pulse which causes the microprocessor to send a message as previously described. Cause it to be initialized to receive. The message is input by the microphone 17 (shown in FIG. 1), which communicates with the control circuit 18.

FIG. 7 is a block diagram of a preferred configuration of RAM 78 of system 10. RAM 78 includes four banks 311, 312, 313 and 314, each containing four RAM chips of conventional design. However, adding additional RAM banks to increase memory capacity is understood as well as additional RAM chips can be added to the RAM banks. Counter circuit 320 and RAM bank selector 330 are provided for addressing incoming data and messages in RAM and recalling material stored from RAM.

The counter circuit 320 shown is an up-down counter whose binary output is the bank selector 330.
Be combined with. Bank selector 330 is connected to the microprocessor on the CAS1 line (line 332) and is also connected to RAM banks 311, 312, 313 and 3 by lines 341, 342, 343 and 344, respectively.
14 is connected. Additional CAS lines 333,334
And 335 may be configured in an additional RAM bank selector for memory expansion in the same manner as the CAS1 line (line 332).

In the preferred embodiment, counter 320
Is configured to generate an up count in response to the recording and conversion mode and a down count in response to the playback function. With such a configuration, the last recorded message is the message reproduced first in the playback. Thus, during a recording and converting operation, the counter 320 receives a pulse from the control circuit 18 at the beginning of the recording and converting mode, which causes the counter 320 to count up with a binary code in response to each received pulse. The binary code count is conveyed to the bank selector 330, and in response, the bank selector 330 selects the first RAM bank 311 according to each count from the counter 320 and outputs the second R bank.
The AM bank 312 follows. At the start of playback mode, the counter receives a pulse at the down input terminal, which causes the counter 320 to count down with a binary code,
This is conveyed to the bank selector 330. The RAM bank selection for playback begins with the last RAM bank that receives the message. CAS1 line 332 of microprocessor 32 during record or playback function
Are switched to the designated RAM bank.

In operation, multiple messages can be stored in each memory of each bank. The microprocessor used may be of the static or dynamic type. Preferably, the static version of the microprocessor comprises static versions of RAM and the dynamic version of the microprocessor comprises dynamic versions of RAM.

Referring to FIG. 5, a telephone system incorporating an analog-to-digital data storage system according to the present invention is shown. In the example shown, generally 202
And two transmitters / receivers, designated as 202 ', are connected to wire 204 and common ground 20 for interconnection.
Connected by 5. Each transmitter / receiver 202 and 202 'includes a power supply 212, a receiver means 214 and a transmitter means 210, like a conventional telephone. A send / receive switch 216 (depressed for a call) is provided on each transmitter / receiver 202 and 202 'to form a transmitter circuit during transmission and to transmit the message while receiving a message.
22 is turned off to complete the circuit to the receiver 214. The transmit / receive switch 216 is shown only for purposes of illustration and is a complete dual extension communication system, telephone system and telephone extension that does not require such a switch for extension or operation of the telephone system. It is understood that the system is available.

The encoder 218 and encoder switch 219 are connected to the transmitter 210 via line 240. Encoder 218 may be of any type previously described, preferably the DTMF type used in most telephone systems. Receiver transmitters 202 and 202 'include a decoder 220 connected to an analog-to-digital data storage system 222 of the type previously described in connection with FIGS. 1, 2 and 3 above. Sender / receivers 202 and 202 'include a message indicator 224 that is activated to indicate that a message has been received and placed in memory. A playback switch 226 and a reset switch 228 are provided for each circuit 222 and a security switch 230 is provided at the receiver of the transmitter / receiver 202 and 202 'so that the recorded message is not heard during recording. It serves to switch 214 out of the circuit. The playback switch 226 replaces an extra active output (not shown) so that the playback function is activated by entering a personal identification code through the telephone keypad (not shown). May be.

The operation of the extension communication system is shown in FIG. 5, where the transmitter / receiver 202 is set to transmit at switch 216 and is transmitted via wire 204 to the transmitter / receiver.
Transmitter 210 and transmitter / receiver 202 'of receiver 202
Complete the circuit between the receivers 214 of. The transmitter / receiver 202 'has a transmit / receive switch 216 on line 217.
From the wire 204 via the analog-digital storage circuit 2
Complete the circuit to 22 and are in receive mode. Transmitter / receiver 202 to transmitter / receiver for recording messages
To send to the receiver 202 ', the sender activates the encoder switch 219 of the transmitter / receiver 202 to activate the encoder 218 and issue a code for transmission to the transmitter / receiver 202'. To do. As described above, the encoder switch 219 is configured such that the transmitter side is the transmitter / receiver 20.
A telephone keypad of a similar device is preferably provided so that a pre-programmed code for 2'can be entered. The transmitter / receiver 202 'is a transmitter / receiver.
A receive switch shuts off the transmitter circuit to form the receiver circuit and is set for reception. As shown, the security switch 230 is in the open state and the message received at the circuit 222 is not played back at the receiver 214, but only recorded in the manner described below.

Active 220 senses the message address and, if addressed to transmitter / receiver 202 ', issues a logic high to transmit to data storage circuit 222 via active line 221. Circuit 222 is activated in the manner described in connection with FIGS. 2 and 3. The conversion and recording of the analog message into digital form is performed by the circuit 222 in the manner described above in connection with FIGS. 2 and 3. At the end of the message, line 110 returns to its normal high state,
Switch 230 is closed to reconfigure the receiver circuit.
The message can be played back by activating the playback switch 226, which initiates the playback circuit to reconvert the message in memory to analog form for output to the receiver 214.

As long as the user of the remote unit is given the appropriate code to activate 220, the message will be sent / received by the transmitter / receiver 202 from any remote unit.
It is understood that it can also be transmitted, stored, and played back at 202 '. As mentioned above, transmitter /
It is understood that receivers 202 and 202 'may also include two-way wireless communication or other wireless transmitters / receivers such as those that operate optically, and are shown in connection with FIGS. 1-3. Also, as explained, the voice storage system 10 can be easily installed in such a transmitter / receiver.

As described herein, the voice storage system of the present invention can be incorporated into various communication systems such as two-way wireless communication, telephone, extension communication, mobile telephone and the like. The voice storage system of the present invention is
In addition to paging systems, you will find applications in medical records, industrial monitors, such as electronic notepads and the like. The system of the present invention may be readily incorporated into various receivers and transmitters / receivers at the time of manufacture, or as an additional item, may be incorporated into existing conventional receivers and transmitters / receivers. The system of the present invention has low power requirements, small and lightweight remote receivers, and is particularly suitable in paging systems with necessarily limited power supplies.

Referring to FIG. 8, an analog communication system is shown for transmitting data in analog form at one rate and receiving and playing back messages at different rates. The system includes a transmitter group 350 with a control terminal 352 for the input of data, including address data and message rate data, message modulation and code generation means 354, and transmitter means 356. Data is input from the control terminal 352 to the message modulation and code generation means 354, where the input message is temporarily stored, address and rate code data is generated, and the analog message is modulated to the selected transmission rate. . A transmission packet containing a modulated analog message, preceded by an address code and a code for controlling the storage and playback speed of the message, is sent to the transmitter means 356 for transmission. The transmitter means 356 can be wireless, such as for transmission at radio frequencies, infrared or visible frequencies, or hardwire, such as a telephone.

The transmitted data is captured by a receiver group 358 which includes receiver means 14 capable of receiving the signal from transmitter means 356. When the signal is received it is conveyed to the decoding and modulation means 16,
The recording and playback speed codes are processed and the transmitted address code is compared with the pre-programmed address code. When the transmitted address code data matches the preset address code of the receiver group 358, the speed code is input to the speed memory for later control of recording and reproducing speed. The receiver group 358 as described above includes amplifier and speaker means 24 for playback of the recorded data.
including.

The coding, decoding and signal modulation functions for both transmitter group 350 and receiver group 358 are similar, but the signal input and control commands for transmitter group 358 are derived from control terminal 352 and the receiver The signal inputs for the groups are derived from the receiver 14 and the control commands are derived from the circuitry of the decoding and modulation means 16.
Since the coding circuitry of transmitter group 350 is of conventional design, various code generators such as digital code generators, tone code or dual tone multi-frequency (DTMF) code generators have been successful. Then used. It is only important that the decoder circuit of receiver group 358 is compatible with the code generator circuit of transmitter group 350. As mentioned above, the transmitted code may include an address entered from the control terminal 352 so that the message may be received and stored at a particular designated receiver group 358. However, the use of the address code with the transmitted signal is not critical, and receiver group 358 may function as a voice activation device that activates the recording circuitry of receiver group 358, as previously described. it can.

The operation of transmitter group 350 is best understood in connection with FIG. 9 where message modulation and code generation circuit 354 is shown schematically as including the circuits of message modulation processor 354a and code generator 354b. . The control terminal 352, which may be a computer with some paging messages in the queue, issues analog messages to the modulation processor 354a and address and speed codes to the code generator 354b. Message is modulation processor 3
While held at 54a, code generator 354b generates the appropriate code for recording and speed and issues it to transmitter 356 for transmission. The control terminal 352 issues a command to the modulation processor 354a to determine the rate at which the analog message is transmitted, and shortly after the transmission of the address and playback rate code, the analog message is transmitted for transmission at the specified rate. Be transported to a container. As best seen in FIG. 10, receiver group 358 receives the address code transmitted by receiver 14 and conveys it to decoder circuit 16 which, if the address code matches, sends an activate command to modulation processor 354a. To publish. The decoder circuit 16 modulates the signal corresponding to the recording speed command by the modulation processor circuit 354a.
To control the recording speed. The transmitted analog message signal is carried from receiver 14 to modulation processor 354a, where the data is preferably converted to digital format and stored in memory. Upon activation of the playback function by the receiver group operator, the playback speed command is issued by the decoder 16 in a manner as described below, the message is recalled from memory, reformatted to analog format, the amplifier and It is reproduced at the command speed via the speaker means 24.

Modulation Processor 3 of Transmitter Group 350
54a and modulation processor 3 of receiver group 358
54a is very similar and operates in substantially the same manner, whether used for transmission or reception. The circuit essentially performs three functions: circuit control and switching, memory conversion, and signal conversion. As shown in FIG. 11, the modulation processor circuit includes a memory 22, a control circuit 1 for performing switching, reset and control functions in response to control logic commands.
8 and a signal conversion circuit 20 for converting the data contained in the signal from analog to digital for storage and for converting from digital to analog for transmission or playback as described in detail above. Including.

Referring to FIGS. 12 and 13, the modulation processor circuit 35 shown in FIGS. 9 and 10.
A schematic diagram of the circuits used in the control means 18, signal conversion means 20 and memory means 22 of 4a is shown. "voice"
Although the term is used everywhere to specify the data to be processed, the invention is not limited to the transmission of voice messages only, as other data types and forms of playback may be used in the system as well. It is understood that you are told.

The modulation processor circuit 354 of the transmitter group 350, as shown in FIGS.
A specific function not used in a is the receiver group 35.
8 modulation processor circuits 354a. The following description of the modulation processor circuit is described in connection with modulation processor 354a of receiver group 358. However, unless otherwise specified, the description applies equally to the circuitry of modulation processor 354a of transmitter group 350.

The previously described playback speed circuit, which allows the system to receive, record and play back messages at different bit rates, is shown most clearly in FIG. 12 and is described in more detail below. Explained. The speed circuit includes speed switches (inverters) 68 and 70 connected to the microprocessor 32 by lines 74 and 76. Speed selector 72 is operated by the outputs of inverters 68 and 70. The speed selector 72 controls the playback speed by
Connected to the output of switching controller 60 by lines 79 and 81. In the modulation processor 354a of the transmitter group 350, the playback rate (which is the transmission rate) is under the control of the control terminal 352,
Therefore, the inverters 68 and 70, the speed selector 7
2 and related circuits are not used.

Messages are always transmitted at the same rate,
Decoder 16 can be preset to issue a fixed recording and playback speed code, as if the recording and playback speed could be fixed. But for maximum flexibility, the same group of receivers will receive different messages transmitted at different rates,
The decoder 16 is preferably adapted to issue different recording and playback speed codes so that they can be recorded and played back.

In operation, the data to be transmitted is input to the memory 22 of the modulation processor 354a of the transmitter group 350 and kept awaiting a transmission command.
The transmit command includes an address code and a speed code, which is sent to code generator 354b and then to transmitter 356. Immediately after the speed code and the transmit command, the command is sent to the microprocessor 32,
The message is retrieved from memory 22 and played back to the transmitter at the commanded playback rate. It is understood that in the signal conversion circuit 20 used to store message data in memory in digitized format, the same circuit is used to reconvert the data to analog format before it is conveyed to the transmitter 356. To be done.

The voice or data analog message is transmitted to the receiver 14 by the transmitter 356. The message is preceded by a designated address code of a commonly used type such as tone, DTMF, digital or the like, includes a speed code and may also include a message end code.

With reference to FIG. 13 where the same numbers refer to the same parts, the provision of a speed memory 370 with which the decoder 16 communicates by lines 371 to 374 results in different recording and playing for each individual message stored in the memory. A decoder 16 is used to issue the back speed code. Line 371 is the active line and activates speed memory 370 to receive the playback speed code output from decoder 16 via lines 373 and 374. The playback speed code is the speed memory 370 specified by the counter 320.
Of the RAM 78, which also selects the corresponding sector of RAM 78 to store the message. When the playback speed code is decoded and stored in memory 370, line 371 is disabled and line 372 is activated. The decoder 16 decodes the recording speed rate and this command is coupled to the recording speed memory sector of the speed memory 370 via lines 373 and 374. Line 372 is then disabled and line 381 from decoder 16 is activated. Line 381 activates the recording and playback circuitry of the system via the input logic buffer 26 which functions as shown in connection with FIG. Line 380 activates speed memory 370 to active line 3
Coupled to 81, activates speed memory 370 to select a recording speed from memory when line 381 is activated. The recording speed code is carried from the memory via bus 390 to the speed input of the microprocessor 32. Line 381 is disabled when a record command is issued by decoder 16 as previously described.

For playback, counter 320 selects the appropriate sector from RAM 78 in the manner previously described, along with the corresponding playback speed code from speed memory 370. During playback, line 380 is disabled, causing speed memory 370 to generate a playback speed code which, via line 390, causes the microprocessor 32 speed circuit to set the playback speed. Be transported.

The playback speed code is stored in the sector of speed memory 370 corresponding to the sector of RAM 78 and the message associated with the code is stored. In this way, the message will be played at the proper speed,
The stored message is matched with the corresponding playback speed code.

Modulation processor 354a of the transmitter group
No memory addressing circuit is required for, since the message storage is under the control of the control terminal 352.

The ability to transmit and play back at different rates substantially reduces transmission time and makes analog message paging practical. Furthermore, data that must be transmitted over the telephone line can be transmitted at a slower rate to maintain message fidelity and later played back at normal speed without loss of fidelity.

Having described the invention in connection with certain preferred embodiments, it is understood that many modifications and variations are possible, all falling within the true spirit and scope of the invention.

[Brief description of drawings]

FIG. 1 is a block diagram of a digital voice storage system according to the present invention.

FIG. 2 is a schematic diagram of the audible conversion, switching and control circuit of FIG.

FIG. 3 is a schematic diagram showing a switching circuit in more detail.

FIG. 4 is a schematic diagram of a portion of the switching portion of FIG. 2 showing a message rate control circuit.

FIG. 5 is a block diagram of an extension communication system using the voice storage memory system of the present invention.

FIG. 6 is a second diagram showing a circuit for manually activating the recording function.
It is a schematic diagram of the switching circuit of the figure.

FIG. 7: Increased random access memory (RAM)
3 is a schematic diagram of a circuit similar to FIG. 2 showing FIG.

FIG. 8 is a block diagram of an analog message paging system incorporating the variable rate transmission and playback features of the present invention.

FIG. 9 is a block diagram of a transmission group according to the present invention.

FIG. 10 is a block diagram of a receiver group according to the present invention.

FIG. 11 is a block diagram of a modulation processor circuit used by both a transmitter group and a receiver group.

FIG. 12 is a schematic diagram of a circuit of a modulation processor.

FIG. 13 is a schematic diagram of a receiver group decoder circuit.

[Explanation of symbols]

 350 transmission station 10,358 receiving station 14,214 receiver circuit 16,220 decoder circuit 78 digital memory 20,222 signal conversion circuit

Claims (17)

[Claims] 1. A digital voice storage communication system, wherein at least one transmitting station selectively addressing and transmitting a communication packet comprising an address code followed by a voice message, and a corresponding predetermined stored store. At least two receiving stations, each having a different address, each a. A receiver circuit for receiving an incoming signal carrying the communication packet; b. A decoder circuit responsive to the receiver circuit for generating a record active signal responsive to the communication packet carried by the incoming signal, the decoder circuit comprising another record active signal from the transmitter. Irrespective of the above, including a comparator for comparing the predetermined stored address with the communication packet address code and automatically generating the recording active signal in response to the comparison; and c. A digital memory for storing the voice message of the communication packet in response to the recording active signal; d. A digital voice storage communication system, comprising: a signal conversion circuit for converting digital data in the digital memory into analog data for reproduction. 2. The digital voice storage communication system according to claim 1, wherein the decoder circuit further includes a circuit for deactivating the digital memory when the recording active signal stops. 3. The digital memory records a new voice message in response to the receiving circuit and sensing an edge of the recording active signal to automatically reset and start the digital voice storage communication system. The digital voice storage communication system according to claim 1, further comprising an edge detector that enables: 4. The memory address selector of claim 1, further comprising a memory address selector for storing information indicative of available memory space to protect the memory from being recorded over previously stored messages. Digital voice storage communication system. 5. The digital voice storage communication system according to claim 2, wherein the decoder circuit terminates the active signal upon sensing completion of a message. 6. A timer is further included, said decoder responsive to said timer to terminate said active signal upon expiration of a preset period of time, thereby enabling said digital memory to record a new voice message. The digital voice storage communication system according to claim 2, wherein 7. The digital voice storage communication system of claim 1, wherein the decoder circuit continuously generates the recording active signal for the duration of the incoming voice message. 8. The decoder circuit is voice activated,
The digital voice storage communication system of claim 1, wherein the recording active signal is generated in response to the incoming voice message. 9. The digital voice storage communication system according to claim 1, wherein the voice conversion circuit converts the voice message of the communication packet from an analog format to a digital format. 10. The digital voice of claim 1, wherein the communication packet further includes command data, the address code and the command data being followed by the voice message of the communication data packet with substantially no delay. Memory communication system. 11. The digital voice storage communication system according to claim 1, wherein the communication packet includes a voice message having a variable length. 12. The digital voice storage communication system according to claim 11, wherein the digital memory sequentially stores digital voice messages having different lengths. 13. The digital voice storage communication system according to claim 1, wherein the signal conversion circuit operates during the recording active signal. 14. The digital voice storage communication system according to claim 1, further comprising an operator activated playback switch for extracting the voice message stored in the digital memory and activating the signal conversion circuit. . 15. The digital voice storage communication system according to claim 14, further comprising a switch for selecting the voice message from the digital memory for conversion by the signal conversion circuit. 16. The digital voice storage communication of claim 4, wherein the memory address selector produces a signal for erasing a recorded voice message that resides in the digital memory longer than other stored messages. system. 17. The digital voice storage communication system according to claim 1, wherein the digital memory records the voice signal unvoiced.