JPH07240640A - Semiconductor differential amplifier - Google Patents

Abstract

PURPOSE:To perform offset compensation (suppression) with a small circuit by detecting a voltage less than a prescribed reduced cut-off frequency from the differential output signals of a differential amplifier part and adjusting an input DC bias corresponding to the voltage. CONSTITUTION:This differential amplifier (main body) OP is operated by two power sources VDD and VSS, a coupling capacitor CA1 is connected between the noninverted input terminal and a signal input terminal, and the coupling capacitor CB1 of the same capacity is connected between an inverted input terminal and a ground terminal. Also, impedanre circuits ZA1 and ZA2 for setting an input bias are connected to the noninverted input terminal, and the impedance circuits ZB1 and ZB2 are connected to the inverted input terminal similarly. Then, by two low-pass filters constituted of feedback resistors RAF and RBF and capacitors CAF and CBF, the voltage less than the prescribed reduced cut-off frequency is detected from the differential output signals outputted from the differential amplifier OP, and the input DC bias is adjusted corresponding to the voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor differential amplifier having an offset compensating circuit for compensating offset.

[0002]

2. Description of the Related Art For example, a semiconductor amplifier incorporated in a repeater or a transmitter / receiver in an optical communication network will be described. In order to realize high-speed transmission, an ECL type semiconductor differential amplifier to which a bipolar transistor is applied or a compound is used. A SCFL type semiconductor differential amplifier to which a semiconductor device is applied is used. However, these ECL format and SCFL format semiconductor differential amplifiers have a small effective logic amplitude, and therefore it is necessary to increase the operation margin so as to surely operate for an input signal of a small amplitude. Is
In particular, it is effective to provide an offset compensation circuit for reducing the output offset voltage.

A conventional example of a semiconductor differential amplifier including such an offset compensation circuit will be described with reference to FIGS.
First, as shown in FIG. 3, a voltage amplification factor (open loop gain) is provided without providing an offset compensation circuit and a feedback circuit.
When the voltage is directly amplified by the differential amplifier OP of G ECL or SCFL type, for example, the input signal S _in is operated by the power supply voltage in the relationship of V _SS <V _DD and the coupling capacitor C _in and Input bias setting resistor R ₁ ,
It is supplied to the non-inverting input terminal of the differential amplifier OP through a circuit composed of R _2, and a circuit equivalent to the above circuit is connected to the other inverting input terminal, and the coupling capacitor C _in on the inverting input terminal side is connected. The input end of is connected to the ground terminal. In such a semiconductor differential amplifier, ideally,
With respect to the input signal S _in , a differential output signal whose voltage is amplified to 2 GS _in is generated between the inverting and non-inverting output terminals.

However, in the actual differential amplifier OP, there are manufacturing variations in the transistors and resistors that form the internal circuit.
In particular, since the input offset voltage V _IS exists due to the characteristic variation of the transistors in the differential input stage, the actual amplitude of the differential output signal becomes 2 G (S _in + V _IS ), and the output offset voltage V _OS (= 2GV _IS ) raises the problem of multiplies.

Therefore, conventionally, a semiconductor differential amplifier having an offset compensation circuit as shown in FIG. 4 has been used. In FIG. 4, the input signal S _in is supplied to the non-inverting input terminal of the differential amplifier (main body portion) OP via the coupling capacitor C _A1 , and the inverting input terminal thereof has the same capacitance as the capacitor C _A1. It is connected to the ground terminal via the capacitor C _B1 . Also, the differential amplifier O
Between the non-inverting input terminal of P and the inverting output terminal, a feedback resistor R _A1
And R _A2 are connected in series, and a feedback capacitor C _A2 is connected between the connection contact of the feedback resistors R _A1 and R _A2 and the ground terminal. Further, feedback resistors R _B1 and R _B2 are similarly connected in series between the inverting input terminal and the non-inverting output terminal, and the feedback capacitor C _B2 is connected between the connection contact of the feedback resistors R _B1 and R _B2 and the ground terminal. Are connected. The resistors R _A1 and R _B1 , the resistors R _A2 and R _B2 , and the capacitors C _A2 and C _B2 are set to have the same resistance value or capacitance value. Therefore, such an offset compensation circuit includes a low-pass filter including resistors R _A1 and R _A2 and a capacitor C _A2 and a resistor R _{A2.
By having B1} and R _B2 and a low-pass filter composed of the capacitor C _B2 , the DC voltage component (output offset voltage) generated at the inverting and non-inverting output terminals is negatively fed back.

When this offset compensation circuit is provided, the output offset voltage V _IS relative to the input offset voltage V _{IS.
The OS} is V _OS = {2G / (1 + 2G)} V _IS , so
This is a significant reduction compared to the circuit shown in FIG.

[0007]

However, in the conventional semiconductor differential amplifier including the offset compensating circuit as shown in FIG. 4, the capacitors C _A2 and C _B2 having a large capacity are used.
However, there is a problem in that the size becomes large.

This problem will be described in more detail. First, a conventional semiconductor differential amplifier including an offset compensation circuit (see FIG. 4).
The low frequency cut-off frequency f _c of (see) is f _c = (C _A1 + C _A2 ) / (2πR _A1 C _A1 C _A2 ) = (C _B1 + C _B2 ) / (2πR _B1 C _B1 C _B2 ), while The low-frequency cutoff frequency f _c ′ of the semiconductor amplifier (see FIG. 3) not provided with the offset compensation circuit is f _c ′ = 1 / {2πR ₁ R ₂ / (R ₁ + R ₂ ) C ₁ }. This means that the coupling capacitors C ₁ and C
When equally designed capacitance values of _A1 is about low cut-off frequency f _c is the low band cut-off frequency f _{c '(C A1} +
C _A2 ) / C _A2 . Therefore, in order to lower the low frequency cut-off frequency f _c in order to compensate only the offset without affecting the input signal S _in , the capacitors C _A2 and C _B2 having a large capacitance are required. In particular, when the semiconductor amplifier of FIG. 4 is formed by the semiconductor device technology, capacitors C _A2 and C ₂ in the semiconductor chip are formed.
_Since the occupied area of _B2 is larger than that of other transistors and the like, it has been a serious problem when implemented as a semiconductor integrated circuit device (IC, LSI, etc.).

The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor differential amplifier which realizes offset compensation (suppression) with a small circuit.

[0010]

In order to achieve such an object, the present invention provides a semiconductor differential amplifier including a differential amplifier for differentially amplifying an input signal inputted via a coupling capacitor, A low-pass filter that detects a voltage equal to or lower than a predetermined low-pass cutoff frequency from the differential output signal output from the differential amplifier, and the differential according to the voltage output from the low-pass filter. An offset compensating circuit having a bias adjusting circuit for adjusting the input DC bias of the amplifying unit is provided.

[0011]

According to the semiconductor differential amplifier having the offset compensating circuit having such a configuration, even if the output offset voltage is generated from the differential amplifier due to the input offset voltage existing in the differential amplifier, The pass filter detects this output offset voltage, and further, the bias adjusting circuit adjusts the input DC bias of the differential amplifier according to the increase / decrease of the output offset voltage. That is, when the output offset voltage increases, the voltage level of the input DC bias is lowered to adjust the input DC bias in the direction of reducing the input offset voltage, so that the output offset voltage is automatically suppressed. Further, by increasing the internal impedance of the bias adjusting circuit, the input stage of the differential amplifier and the low pass filter can be effectively separated, and the coupling capacitor and the low pass filter can be configured. A required capacitor can be made small in capacity, and as a result, a small semiconductor differential amplifier can be realized.

[0012]

The first embodiment of the present invention will be described together with the principle of the present invention. First, the circuit configuration will be described with reference to FIG.
The differential amplifier (main body) OP has two power supplies V _DD and V _SS (V _SS <V
_DD ), the coupling capacitor C _AI is connected between the non-inverting input terminal and the signal input terminal, and the coupling capacitor C _BI is connected between the inverting input terminal and the ground terminal. . In addition, each capacitance value is
There is a relationship of C _AI = C _BI .

Further, a first impedance circuit (or impedance element, the same applies hereinafter) Z _A1 and a second impedance circuit Z _A2 for setting an input bias are connected to the non-inverting input terminal, and an inverting input is made. Similarly, the third impedance circuit Z _B1 and the fourth impedance circuit Z _B2 for setting the input bias are also connected to the terminals. Furthermore, between the non-inverting input terminal and the ground terminal,
_A first variable current source I _A whose current changes according to a first feedback signal V _AF described later is connected, and a current flows between the inverting input terminal and the ground terminal by a second feedback signal V _BF described later. A changing second variable current source I _B is connected. The first and second impedance circuits Z _A1 , Z
It is realized by a circuit configuration or element in which _B1 is the same, the third and fourth impedance circuits Z _A2 and Z _B2 are the same, and the first and second variable current sources I _A and I _B are the same. Further, in FIG. 1, the input offset voltage V _IS is shown as applied to the non-inverting input terminal side.

_A first feedback resistor R _AF and a feedback capacitor C _AF are connected in series between the non-inverting output terminal Q _{A of the} differential amplifier OP and the ground terminal, and their connecting contacts x
Signal V _AF of voltage generated in the _A is supplied to the first variable current source I _A, likewise, between the inverted output terminal Q _B and the ground terminal, a second feedback resistor R _BF and feedback capacitor C _BF The signals V _BF of the voltages generated at these connection contacts x _B are connected in series and are supplied to the second variable current source I _B. The feedback resistors R _AF and R _BF are both equal, and the feedback capacitors C _AF and C _BF are both set to the same resistance value or capacitance value.

Next, the operation of the differential amplifier having such a configuration will be described. First, the DC component of the input signal S _in is cut by the coupling capacitor C _AI , the DC signal is biased by the first and second impedance circuits Z _A1 , Z _A2 , and the input signal S _in is supplied to the non-inverting input terminal of the differential amplifier OP. It Here, the DC bias voltage at the connection contact of the first and second impedance circuits Z _A1 and Z _A2 has the respective impedances Z
If the current values of _A1 , Z _A2 and the first variable constant current source I _A are I _A , then {Z _A2 / (Z _A1 + Z _A2 )} V _DD −Z _A1 I _A , and the feedback signal V Amplification factor of current I _{A to AF} g _mA
If expressed using (= I _A / V _AF ), {Z _A2 / (Z _A1 + Z
_A2 )} V _DD -Z _A1 g _mA V _AF . Therefore, the voltage signal (denoted as V ₊ ) input to the non-inverting input terminal is the input signal S _in having only the AC component, the DC bias voltage, and
Since it is the sum of the input offset voltage V _IS , it can be expressed by the relational expression of V ₊ = S _in + {Z _A2 / (Z _A1 + Z _A2 )} V _DD −Z _A1 g _mA V _AF + V _IS (1) it can.

On the other hand, the third and fourth impedance circuits Z
The DC bias voltage at the connection contact of _B1 and Z _B2 has impedances Z _B1 and Z _B2 , respectively, and a second variable constant current source I
_If the current value of _B is I _B , {Z _B2 / (Z _B1 + Z _B2 )}
V _DD −Z _B1 I _B , and further expressed using the amplification factor g _mB (= I _B / V _BF ) of the current I _B with respect to the feedback signal V _BF ,
{Z _B2 / (Z _B1 + Z _B2 )} V _DD −Z _B1 g _mB V _BF .
Therefore, the input voltage of the inverting input terminal (V _- a)
Can be expressed by the following relational expression: V ₋ = {Z _B2 / (Z _B1 + Z _B2 )} V _DD −Z _B1 g _mB V _BF (2)

_A differential output signal ( _denoted as S _out ) generated between the non-inverting output terminal Q _A and the inverting output terminal Q _B of the differential amplifier OP having a voltage gain (open loop gain) G.
By applying the above formulas (1) and (2), S _out = 2G (V ₊ −V ₋ ) = 2G [[S _in + {Z _A2 / (Z _A1 + Z _A2 )} V _DD −Z _A1 g _mA V _AF + V _IS ] − [{Z _B2 / (Z _B1 + Z _B2 )} V _DD −Z _B1 g _mB V _BF ]]. Further, as described above, since the respective circuits connected to the non-inverting input terminal and the inverting input terminal are realized by the components having the same characteristics, the elements of the circuit connected to the non-inverting input terminal side When the above equation is simplified by using a constant, it is represented by S _out = 2G {S _in −Z _A1 g _mA (V _AF −V _BF ) + V _IS } (3).

Here, the voltage V _AF in the above equation (3) is a DC voltage generated by the low pass filter composed of the feedback resistor R _AF and the capacitor C _AF , and the voltage V _BF is the feedback resistor. R _BF (having the same resistance value as R _AF ) and capacitor C
Since the DC voltage generated by the constructed low pass filter _BF (C _AF and the capacitance value are equal), these voltage differences (V _AF -V _BF), an output terminal Q _A, between Q _B It is equal to the generated output offset voltage V _OS . Therefore, paying attention to the output offset voltage V _OS in the above equation (3), V
_OS = 2G (−Z _A1 g _mA V _OS + V _IS ), and the output offset voltage V _OS is V _OS = {2G / (1 + 2GZ _A1 g _mA )} V _IS = 1 / {(1 / 2G) + Z _A1 g _mA } V _IS (4), and since 1 << 2 G, the input offset voltage V _IS is reduced to almost 1 / Z _A1 g _mA .

Further, according to this embodiment, the problem of increasing the size of the capacitor in the conventional semiconductor differential amplifier (see FIG. 4) is improved. First, in the present embodiment shown in FIG. 1, the coupling capacitor C _AI and the impedance circuits Z _A1 and Z _A2 provided on the input side of the differential amplifier OP.
Since the impedance of the variable constant current source I _A and the input impedance of the differential amplifier OP are extremely high, the low-frequency cutoff frequency f _cin determined by the variable constant current source I _A and the variable constant current source I _A is almost coupled with the impedance circuits Z _A1 and Z _A2. since determined by the capacitor C _AI, a _{f cin = 1 / {2πC AI} Z A1 Z A2 / (Z A1 + Z A2)} ... (5), likewise, the coupling capacitor C _BI and the impedance circuit Z _B1, Z _B2 The low-frequency cutoff frequency determined by the variable constant current source I _B is also equal to f _cin .

Further, the high cutoff frequency f _cAF determined by the feedback resistor R _AF and the capacitor C _AF is f _cAF = 1 / 2πC _AF R _AF (6), which is determined by the feedback resistor R _BF and the capacitor C _BF . The high cutoff frequency f _cBF is also equal to f _cAF .

On the other hand, the low cutoff frequency f _{c of the} input signal determined by the coupling capacitor C _A1 , the resistor R _A1 and the feedback capacitor C _A2 provided on the input side of the conventional differential amplifier shown in FIG. is as described _{above, f c = (C A1 +} C A2) / (2πR A1 C A1 C A2) ... (7). Then, as is apparent from the equation (7), in the conventional differential amplifier, the coupling capacitor C _A1
And the feedback capacitor C _{A2 have} the same capacitance value (C _A1
= C _A2 ), it is possible to minimize these capacitors, and in that case, the low cutoff frequency f
_c becomes _{f c = 1 / πC A1 R} A1 ... (8).

Therefore, if the above equations (5) and (8) are compared, R _A1 = Z _A1 Z _A2 without increasing the size of the circuit.
Since it is clear in the semiconductor manufacturing technology that it is easy to determine the resistance value of the impedance circuit so as to have the relationship of / (Z _A1 + Z _A2 ), in this embodiment, the coupling capacitor C _AI is compared with the conventional one. 1/2 (ie C _AI = C
It can be _A1 / 2).

In this embodiment, the low cutoff frequency f _cin and the high cutoff frequency f _cAF are set under, for example, a commonly used condition in order to obtain sufficient isolation between input and output. Based on f _cin = 10
Even if it is set to × f _cAF , Z _A1 Z _A2 / (Z _A1 +
Since the resistance value of Z _A2 ) is usually about 50Ω and the feedback resistance R _AF can be normally set to about 50 kΩ, the values of the feedback capacitor C _AF and the coupling capacitor C _AI are C _AF = 0.01. It becomes about C _AI .

As a result, according to this embodiment, both the feedback capacitor C _AF and the coupling capacitor C _AI can be made smaller than in the conventional technique (see FIG. 4).

As described above, according to this embodiment, the coupling capacitor C _AI and the feedback capacitor C _AF for offset compensation can be made small in capacity, so that a small semiconductor differential amplifier having an offset compensation circuit is provided. Can be provided. In particular, in the case of making into an IC or an LSI, the size of the semiconductor chip can be reduced, so that an extremely excellent effect is exhibited.

Next, a second embodiment will be described with reference to FIG. It should be noted that this embodiment is a more specific example based on the first embodiment shown in FIG. 1 and is a semiconductor differential amplifier of SCFL type formed by GaAs MESFETs. Moreover, FIG.
In the figure, the same or corresponding parts as in FIG.

First, the differential amplifier (main body) OP of FIG.
2 will be described. In FIG. 2, two high power type diodes D _p1 and D _p2 are forward-connected to the power supply V _DD , and a GaAs MESFET forming a differential pair is formed.
The drains of q ₁ and q ₂ (hereinafter referred to as FETs) are connected to the cathode of the diode D _p2 via load resistors R _L1 and R _L2 . The common source contact of the FETs q ₁ and q ₂ is the drain / source path of the FET q ₃ or the resistance r.
_The constant current I connected to the power supply V _SS via ₁ and the constant current I _CS determined by the constant voltage V _CS applied to the gate of the FET q ₃ at all times.
FET that constitutes the differential pair by flowing _c1
It has set a DC bias of q _1, q ₂ and the load resistor R _L1, R _L2.

The signal S generated at the drain of the FET q _1.
L1 is a source follower type first level shift circuit formed by FETs q ₄ , q ₅ and diodes D ₁ , D ₂ and a resistor r _{2, and} is formed by FETs q ₆ , q ₇ and a resistor r ₃ . Source follower format first
Is output to the inverting output terminal Q _B via the output stage of

That is, in the first level shift circuit, the FET q ₄ and the diode D are _driven by the constant current I _c2 flowing through the FET q ₅ whose gate is applied with the constant voltage V _CS.
Since the DC bias of ₁ and D ₂ is set, the signal S
_L1 is power-amplified by the FET q ₄ , and level-shifted by the forward voltage of the diodes D ₁ and D ₂ and supplied to the gate of the FET q ₆ of the first output stage. In the first output stage, the FET q ₇ is supplied with the constant current I _c3 flowing through the FET q ₇ whose constant voltage V _CS is applied to the gate.
Since the DC bias of q ₆ is set,
q ₆ power-amplifies the signal supplied to the gate and outputs the amplified signal to the inverting output terminal Q _B.

On the other hand, the signal S _L2 generated at the drain of the FET q ₂ is the FETs q ₈ and q ₉ and the diodes D ₃ and D.
₄ and a second level shift circuit source follower type which is formed by resistors _{r 4, FET q 10, q} 11 and via a second output stage of the source follower type, which is formed by the resistor r ₅ noninverting It is output to the output terminal Q _A.

That is, in the second level shift circuit, the FET q ₈ and the diode D are _driven by the constant current I _c4 flowing through the FET q ₉ whose gate is applied with the constant voltage V _CS.
Since the DC bias of ₃ and D ₄ is set, the signal S
_L2, together with electric power is amplified by the FET q _8, is a forward voltage amount corresponding level shifting diodes D _3, D _4, is supplied to the gate of FET q ₁₀ of the second output stage. In the second output stage, the constant current I _c5 flowing through the FET q ₁₁ to which the constant voltage V _CS is applied to the gate causes the FET
Since the DC bias of q ₁₀ is set,
q ₁₀ power-amplifies the signal supplied to the gate and outputs the amplified signal to the non-inverting output terminal Q _A.

As described above, the differential amplifier (main body portion) of this embodiment has the FETs q _{1 to} q ₁₁ and the diodes D _p1 , D.
is constituted by _p2, D ₁ ~D _4, and resistors _{R L1, R L2, r 1} ~r 5.

Next, a structure corresponding to a part of the input bias setting circuit and the offset compensation circuit connected to the input side of the differential amplifier OP in FIG. 1 will be described. In FIG. 2, resistors R _A1 and R _A2 and diodes D _{A1 to} D _A6 connected in series between the power supply V _DD and the ground terminal are used to connect the first and second impedance circuits (see FIG. 1) Z _A1 and Z _A2.
Are similarly formed, and resistors R _B1 and R _B2 and diodes D _{B1 to} D _B are similarly connected in series between the power supply V _DD and the ground terminal.
_B6 forms third and fourth impedance circuits (see FIG. 1) Z _B1 and Z _B2 . The cathode of the diode D _A4 is connected to the gate of the FET q ₁ (corresponding to the non-inverting input terminal) and is also connected to the input terminal of the input signal S _in via the coupling capacitor C _AI . The cathode of the diode D _B4 is FET q ₂
Is connected to the gate (corresponding to the inverting input terminal) of and is also connected to the ground terminal via the coupling capacitor C _BI .

Further, the first and second variable constant current sources (see FIG. 1) are _constituted by the FETs q _A , q _B , q _AB and the resistor r _AB .
I _A and I _B are formed. That is, in FIG. 2, FET q _A constituting a differential pair, a common source contact of q _B is connected to the power source V _SS through a drain source path to the resistance r _AB of FET q _AB, the drain of the FET q _A is It is connected to the cathode of diode D _A2 , and FET q
The drain of _B is connected to the cathode of diode D _B2 . The constant voltage V _CS is applied to the gate F
The constant current I _AB flowing by ET q _AB causes FETs q _A , q
_While the DC bias of _B is set, FET q _A ,
The drain currents I _A and I _{B of} q _B flow according to feedback voltages V _AF and V _BF input to the gates via a feedback circuit described later.

Next, the circuit configuration corresponding to the portion corresponding to the feedback circuit in FIG. 1 (the remaining portion of the offset compensation circuit) will be described. _A feedback resistor is provided between the inverting output terminal Q _B and the gate of the FET q _A. R _AF and low-pass filter consisting of a feedback capacitor C _AF is connected, the feedback voltage V _AF to be generated at the connection contact point x _a of the resistor R _AF and the capacitor C _AF is FE
While being supplied to the gate of T q _A, a low pass filter including a feedback resistor R _BF and a feedback capacitor C _BF is connected between the non-inverting output terminal Q _A and the gate of the FET q _B , and this resistor R _BF is connected. The feedback voltage V _BF generated at the connection contact x _B between the capacitor C _BF and the capacitor C _BF is supplied to the gate of the FET q _B.

The feedback resistors R _AF and R _BF are _½ of the resistance values R _AF / 2 and R _AF / 2 and the resistance value R _BF /, respectively.
A small-capacity condenser C _cup is connected between the middle point of 2 and R _BF / 2. The reason for providing such a capacitor C _cup is as follows. When the semiconductor differential amplifier of this embodiment is formed on the same semiconductor chip such as an IC or an LSI to form a high frequency amplifier, the wire inductance of the wiring itself and the gate capacitance of the FETs q _A and q _B are determined. Due to this, there may be a resonance point in the gigahertz (GHz) band, which may cause a phenomenon such as oscillation. By providing such a capacitor C _cup in the feedback circuit, a signal component in the gigahertz (GHz) band is generated. To prevent the occurrence of oscillations. In the case of manufacturing by the compound semiconductor process, the capacitor C _cup can be realized by the MIM capacity.

Next, the operation of this embodiment will be described. The voltage gain (open loop gain) G of the differential amplifier (main body portion) is expressed by g _m which is the mutual conductance of the FETs q _A and q _B , and _RL which is the resistance value of the load resistors R _L1 and R _L2 . Approximately G = g _{m RL} . The input signal S _in , after the predetermined DC component is removed by the coupling capacitor C _AI , is DC _biased by the resistors R _A1 , R _A2 and the diodes D _{A1 to} D _A6 , input to the gate of the FET q ₁ , and amplified. The generated differential output signal is output between the output terminals Q _A and Q _B.

The output offset voltage V _OS in the differential output signal generated between the output terminals Q _A and Q _B passes through the feedback circuit formed by the feedback resistors R _AF and R _BF and the capacitors C _AF and C _BF , feedback voltage V _A, FET q _A as V _B, q _B
Is supplied to the gate. Then, FET q _A, the gate input voltage V _A of q _B, V _B versus drain current I _A, g _mA ratio of each of I _B, when expressed as g _mB (= g _mA), the also in this embodiment Expression (4) is satisfied, and the output offset voltage V _OS is reduced. Furthermore, based on the principle described in the first embodiment, the capacities of the coupling capacitors C _AI and C _BI and the feedback capacitors C _AF and C _BF can be reduced, so that, for example, an IC or an LSI is formed. When the above is performed, the semiconductor chip can be made smaller.

In this embodiment, the impedance circuit on the input side is realized by a plurality of diodes.
It may be formed by a T or other device.

[0040]

As described above, according to the present invention, in the semiconductor differential amplifier provided with the differential amplifier for differentially amplifying the input signal inputted through the coupling capacitor, the differential amplifier is A low-pass filter that detects a voltage equal to or lower than a predetermined low-pass cutoff frequency from the output differential output signal, and an input DC bias of the differential amplifier according to the voltage output from the low-pass filter. Since the offset compensation circuit having a bias adjustment circuit for adjusting the above is provided, even if an output offset voltage is generated from the differential amplification section due to the input offset voltage existing in the differential amplification section, A low-pass filter detects this output offset voltage, and the bias adjustment circuit further detects the input DC voltage of the differential amplifier according to the increase / decrease of the output offset voltage. To adjust the astigmatism. That is, when the output offset voltage increases, the voltage level of the input DC bias is lowered to adjust the input DC bias in the direction of reducing the input offset voltage, so that the output offset voltage is automatically suppressed. Further, by increasing the internal impedance of the bias adjusting circuit, the input stage of the differential amplifier and the low pass filter can be effectively separated, and the coupling capacitor and the low pass filter can be configured. The required capacitor can be made small,
As a result, a small semiconductor differential amplifier can be provided.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment according to the present invention.

FIG. 2 is a circuit diagram showing a second embodiment according to the present invention.

FIG. 3 is a circuit diagram for explaining a problem in a conventional semiconductor differential amplifier.

FIG. 4 is a circuit diagram for further explaining a problem in a conventional semiconductor differential amplifier.

[Explanation of symbols]

OP ... Differential amplifier (main body part), Z _A1 , Z _A2 , Z _B1 , Z
_B2 ... impedance circuit, C _AI, C _BI ...... coupling capacitor, I _A, I _B ... variable current source circuit, R _AF, R _BF
... Feedback resistance, C _AF , C _BF ... Feedback capacitor, q ₁ ~
q ₁₁ , q _A , q _B , q _AB ... FET, D _p1 , D _p2 , D ₁ ~
D ₃ , D _{A1 to} D _A6 , D _{B1 to} D _B6 ... Diodes, R _L1 , R
_L2 ... load resistance, r _{1 to} r ₅ , r _AB , R _A1 , R _A2 , R _B1 ,
R _B2 ... Resistor, C _cup ... Capacitor.

Claims (3)

[Claims] 1. A semiconductor differential amplifier including a differential amplifier for differentially amplifying an input signal input via a coupling capacitor, wherein a differential output signal output from the differential amplifier is lower than a predetermined value. Offset compensation having a low-pass filter that detects a voltage equal to or lower than a band cut-off frequency, and a bias adjustment circuit that adjusts an input DC bias of the differential amplification unit according to the voltage output from the low-pass filter. A semiconductor differential amplifier comprising a circuit. 2. A semiconductor differential circuit comprising: a DC bias circuit for biasing an input signal input via a coupling capacitor to a predetermined DC bias; and a differential amplifier section for differentially amplifying a signal generated in the DC bias circuit. In the amplifier, a low-pass filter that detects a voltage equal to or lower than a predetermined low-pass cutoff frequency from a differential output signal output from the differential amplification unit, and a voltage that is output from the low-pass filter according to the low-pass filter. A semiconductor differential amplifier, comprising: an offset compensation circuit having a DC bias voltage of the DC bias circuit and a bias adjustment circuit having an internal impedance higher than that of the DC bias circuit. 3. The semiconductor differential amplifier according to claim 1, wherein the semiconductor differential amplifier is formed of a GaAs compound semiconductor device.