JPH07240630A - Frequency multiplier circuit and frequency mixing circuit - Google Patents

Abstract

PURPOSE:To provide a frequency multiplier circuit and a frequency mixer circuit in constitution suitable for an MOS integrated circuit. CONSTITUTION:In two differential pairs (M1, M2) and (M3, M4) driven by the constant current source I0 of an approximately equal value, differential output pairs are constituted by connecting the output terminals of the M1 and the M3 and the output terminals of the M2 and the M4 each other in common respectively and the offset voltage VK of the approximately equal value is interposed respectively between the input terminals of the M1 and the M4 and between the input terminals of the M2 and the M3. A VRF is directly impressed to the input terminal of the M1 and it is superimposed on the VK and impressed to the input terminal of the M4. A VLO is directly impressed to the input terminal of the M3, and it is superimposed on the VK and impressed to the input terminal of the M2. Since the product VRFVLO is included in a differential output current, the components of the sum and the difference of two frequency are obtained, and this frequency mixing circuit is attained. Also, at the time of VRF=VLO, this frequency multiplying circuit is attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency multiplying circuit and a frequency mixer circuit, and more particularly to a frequency multiplying circuit and a mixer circuit having a configuration suitable for MOS integrated circuit.

[0002]

2. Description of the Related Art As a frequency multiplier circuit suitable for semiconductor integrated circuit, a bipolar transistor structure shown in FIG. 8 has been known. This was previously filed by the present inventor (Kimura) (Japanese Patent Laid-Open No. 4-795).
No. 04 publication). The outline will be described below.

In FIG. 8, (Q1, Q2) and (Q3,
The differential pair Q4) is driven by an equal constant current source I ₀ , and each differential pair is composed of bipolar transistors having different capabilities. That is, the emitter size ratios of Q1 and Q2 and Q3 and Q4 are Q2: Q1 = Q3: Q4 =
1: K (K> 1). Note that K is an initial of the inventor (Kimura).

Between these two differential pairs, Q1
And Q3 and Q2 and Q4 form a differential input terminal to which the input terminals are commonly connected and to which the input signal VIN is applied. The output terminals of Q1 and Q4 and Q2 and Q3 are commonly connected to each other to form a differential output terminal for outputting the output signal VOUT. A constant current source a {(K-1) / (K + 1)} I ₀ is connected to one output terminal (a common connection output terminal of Q1 and Q4). This is to make the operating voltage appropriate.

In the above structure, when α _F is the direct current amplification factor of the transistor, the collector currents (I _C1 , I _C2 , I _C3 , I _C4 ) of the respective transistors are expressed by the formula 1. However, in Formula 1, V _T is expressed as V _T = kT / q using the Boltzmann constant k, absolute temperature T, and unit electron charge q, and V _K is expressed by Formula 2 using V _T Can be expressed as

[0006]

[Equation 1]

[0007]

(2) V _K = V _T lnK

From Equation 1, since I _C1 -I _C2 (= ΔI ₁ ) is Equation 3 and I _C3 -I _C4 (= ΔI ₂ ) is Equation 4, the differential output current ΔI is obtained as Equation 5.

[0009]

[Equation 3]

[0010]

[Equation 4]

[0011]

[Equation 5]

Since tanhx can be expanded in series as shown in Expression 6, the differential output current can be expanded by using this to become Expression 7, which includes the square term of the input signal V _IN .

[0013]

[Equation 6] tanhx = x− (1/3) x ³

[0014]

[Equation 7]

Therefore, if the input signal V _{IN is given} by Equation 8,
The square term of the input signal V _IN can be found from Equation 9 and it can be seen that the frequency is doubled.

[0016]

[Formula 8] V _IN = | V _IN | cos (2πft)

[0017]

[Equation 9]

Next, a frequency mixer circuit using a Gilbert cell is known, and it is constructed on a bipolar integrated circuit. If it is constructed on a MOS integrated circuit, it is shown in FIG. Like In FIG. 9, this frequency mixer circuit has two differential pair transistors {(M11, M12), (M1) between input terminal pairs (1, 2).
3, M14)} and drives each of the two sets of differential pair transistors between the input terminal pair (3, 4) 1
Arrange the differential pair transistors (M15, M16),
This one differential pair transistor is driven by one constant current source I ₀₀ .

That is, two sets of differential pair transistors {(M1
1, M12), (M13, M14)}, the drains of one transistor (M11, M13) and the drains of the other transistor (M12, M14) are commonly connected to each other, and the differential pair transistor (M11, M1) is connected.
2) The gate of one transistor M11 and the other transistor M1 of the differential pair transistors (M13, M14)
4 is commonly connected to one input terminal 1 of the input terminal pair (1, 2), and is connected to the differential pair transistor (M11, M
12) The gate of the other transistor M12 and one transistor M of the differential pair transistors (M13, M14)
The gate of 13 is commonly connected to the other input terminal 2 of the input terminal pair (1, 2).

One differential pair transistor (M1
5, M16), the drain of one transistor M15 is connected to the sources of the differential pair transistors (M11, M12) and the gate is connected to one input terminal 3 of the input terminal pair (3, 4). The other transistor M16
The drain is a differential pair transistor (M13, M14)
Of the input terminal and the gate is connected to one input terminal 4 of the input terminal pair (3, 4). Input terminal pair (1, 2)
A second AC signal (voltage V _Lo ) is applied between them, and a first AC signal (voltage V _RF ) is applied between the pair of input terminals (3, 4).

Hereinafter, it will be shown that the circuit shown in FIG. 9 operates as a frequency mixer circuit. In FIG. 9, the ratio (W / L) of the gate width W and the gate length L of the transistors (M11, M12, M13, M14) is equal (W / L).
₁ , the transistor mobility is μ _n , and the gate oxide film capacitance per unit area is C _OX , the transconductance parameter β ₁ can be expressed as Formula 10. Therefore, the threshold voltage is V _T and the gate-source voltage is V V. _{If GSi} (i = 11 to 14), drain current (I
_d11 , I _d12 , I _d13 , and I _d14 ) are represented by Formulas 11 to 14.

[0022]

[Equation 10]

[0023]

## _EQU11 ## I _d11 = β ₁ (V _GS11 −V _T ) ²

[0024]

## _EQU12 ## I _d12 = β ₁ (V _GS12 −V _T ) ²

[0025]

( _Equation 13) I _d13 = β ₁ (V _GS13 −V _T ) ²

[0026]

## _EQU14 ## I _d14 = β ₁ (V _GS14 −V _T ) ²

Here, I _d15 , I _d16 , I ₀₀ , and V _LO are equations 1
5 to 18 can be set.

[0028]

[ _Equation 15] I _d11 + I _d12 = I _d15

[0029]

## _EQU16 ## I _d13 + I _d14 = I _d16

[0030]

[ _Expression 17] I _d15 + I _d16 = I ₀₀

[0031]

[ _Equation 18] V _GS11 −V _GS12 = V _GS14 −V _GS13 = V _LO

Next, assuming that the ratio of the gate width and the gate length of M15 and M16 is (W / L) ₂ , the transconductance parameter β ₂ can be expressed by Formula 19, so that the drain currents I _d15 and I _d16 can be _calculated by Formula 11 ~ It can be expressed in the same manner as in the above-mentioned 14, and becomes as in the mathematical expressions 20 and 21. Further, the first AC signal (voltage V _RF ) is expressed by Equation 22.

[0033]

[Formula 19]

[0034]

[ _Equation 20] I _d15 = β ₂ (V _GS15 −V _T ) ²

[0035]

[ _Expression 21] I _d16 = β ₂ (V _GS16 −V _T ) ²

[0036]

[ _Equation 22] V _GS15 −V _GS16 = V _RF

Solving the equations (17) and (20) to (22), I _{VRF
Calculating} = I _d15 −I _{d16 yields} Equation 23, so I
_d15 and I _d16 are obtained as in Equations 24 and 25.

[0038]

[Equation 23]

[0039]

[ _Equation 24] I _d15 = (1/2) (I ₀₀ + I _VRF ).

[0040]

(25) I _d16 = (1/2) (I ₀₀ −I _VRF ).

If I _VLO is set as in Equation 26,
The input voltage V _LO can be expressed as in Expression 27.

[0042]

[Equation 26]

[0043]

[Equation 27]

Then, ΔI = I ₃₁ −I ₃₂ becomes
It becomes like 8.

[0045]

[Equation 28]

Then, in Expression 28, | V _Lo | << √
If (I ₀₀ / β ₁ ), ΔI can be approximated as in Expression 29.

[0047]

[Equation 29] ΔI ≒ (1 / I ₀₀ ) I _VRF · I _VLO

[0048] Here, I _VLO corresponds to the differential output current of the differential amplifier which is driven by a constant current source I _00/2 with respect to the input voltage V _LO. I _VRF represents the differential output current of the differential amplifier driven by the constant current source I ₀₀ with respect to the input voltage V _RF as shown in Equation 23.

[0049] Therefore, the I _VLO nearly proportional to the input voltage V _LO, since I _VRF is approximately proportional to the input voltage V _RF, the smaller the input voltage V _RF and the V _LO, the circuit shown in FIG. 9 multiplier Becomes

Further, by further expanding the formula 28 into a series, Δ
Since I becomes Equation 30, Equation 31 can be obtained by ignoring the second-order and higher-order terms of the input voltages V _LO and V _RF .

[0051]

[Equation 30]

[0052]

[Equation 31]

Here, the input voltage V _LO and the input voltage V _RF are expressed by Equation 3
2 and 33, when the product of the two is taken,
As shown in, the sum and difference components of the two frequencies are obtained.

[0054]

[Expression 32] V _LO = | V _LO | cos 2πf _LO t

[0055]

[Expression 33] V _RF = | V _RF | cos 2πf _RF t

[0056]

[Formula 34] V _LO · V _RF = (1/2) | V _LO ｜| V _RF ｜
[Cos {2π (f _LO + f _RF ) t} + cos {2π (f _LO −
f _RF ) t}]

Since I ₃₁ and I ₃₂ are differential currents, they can be expressed by equations 35 and 36, respectively,
Including (1/2) ΔI. Therefore, the Gilbert cell shown in FIG. 9 is a frequency mixer circuit.

[0058]

(35) I ₃₁ = (1/2) (I ₀₀ + ΔI)

[0059]

(36) I ₃₂ = (1/2) (I ₀₀ −ΔI)

[0060]

The above-mentioned conventional frequency multiplier circuit is capable of low voltage operation, but one of the transistors of the differential pair has an emitter size of K times (K> 1). There is a problem that the size becomes large and the frequency characteristic deteriorates.

Further, if the frequency mixer circuit is constructed by using Gilbert cells as shown in FIG. 9, it becomes a vertically stacked circuit, so that the power supply voltage becomes high. Further, since the number of elements is large, the NF (noise figure) is deteriorated and the circuit current is also increased.
Further, since the multiplier characteristics are approximated only when both input voltages (V _L0 , V _RF ) are small, the operation at a large input is handled by manipulating the value of the emitter resistance, so that third-order distortion occurs. I have a problem.

It is an object of the present invention to provide a frequency multiplier circuit and a frequency mixer circuit which are suitable for MOS integrated circuits and which can operate at low voltage and operate at high frequency.

[0063]

In order to achieve the above object, the frequency multiplication circuit and frequency mixer circuit of the present invention have the following configurations. That is, in the frequency multiplying circuit or the frequency mixer circuit of the first invention, the AC signal or the first AC signal is applied to the input end of one transistor, and the AC signal or the second AC signal is offset to the input end of the other transistor. The differential pair is applied by superimposing it on the voltage.

The frequency multiplying circuit or the frequency mixer circuit of the second invention is provided with one differential pair; an AC signal or a sum signal or a difference signal of the first AC signal and the second AC signal as an input, and the differential pair. A circuit for forming an offset voltage between the input terminals of two transistors, which outputs an input signal to the input terminal of one transistor and outputs the input signal to the input terminal of the other transistor by superimposing the input signal on the offset voltage. And an offset voltage forming circuit for

The frequency multiplying circuit of the third invention is two differential pairs driven by a constant current source having an approximately equal value, and between the two differential pairs, one of the differential pairs is connected. The output terminals of the transistors and the output terminals of the other transistor are commonly connected to each other to form a differential output pair, and a substantially equal value is provided between the input terminals of one transistor and the other transistor of each differential pair. The offset voltage is formed with the same polarity on the input side of the transistors whose output terminals are commonly connected.An AC signal is applied to one of the input terminals and an AC signal is applied to the other input terminal as an offset voltage. It is applied in a superimposed manner;

The frequency multiplying circuit of the fourth aspect of the invention is two differential pairs driven by a constant current source having substantially the same value. Between the two differential pairs, one of the differential pairs is connected. Two differential pairs that form a differential output pair by commonly connecting the output terminals of the transistors and the output terminals of the other transistor; and input terminals of one transistor and the other transistor of each differential pair. It is a circuit that forms a substantially equal offset voltage by making the polarities of the input ends of transistors whose output ends are commonly connected to each other, and outputs an input signal to one input end between the input ends. On the other hand, the other input terminal is provided with two offset voltage forming circuits for superimposing an input signal on the offset voltage and outputting it.

In the frequency multiplying circuit according to the fourth aspect of the invention; the two offset voltage forming circuits have a case where an AC signal is applied between their input terminals and a case where an AC signal is applied to the input terminal of one circuit. The input terminal of the other circuit may be AC-grounded in some cases.

The frequency mixer circuit of the fifth aspect of the invention is two differential pairs driven by constant current sources having substantially equal values.
Between the two differential pairs, the output terminals of one transistor of each differential pair and the output terminals of the other transistor are commonly connected to form a differential output pair. Substantially equal offset voltages are formed between the input terminals of the transistor and the other transistor, with the same polarity on the input terminal side of the transistors with the output terminals commonly connected, and at one input terminal between the one input terminals. The first AC signal is applied, the first AC signal is applied to the other input terminal by being superimposed on the offset voltage, the second AC signal is applied to one input terminal between the other input terminals, and the first AC signal is applied to the other input terminal. 2 AC signals are applied superimposed on the offset voltage;
It is characterized by that.

The frequency mixer circuit according to the sixth aspect of the present invention comprises two differential pairs driven by constant current sources having substantially equal values.
Two differential pairs that form a differential output pair by commonly connecting the output terminals of one transistor and the output terminals of the other transistor of each differential pair between the two differential pairs; A circuit that forms an offset voltage of substantially equal value by making the polarities of the input ends of transistors whose output ends are commonly connected between the input ends of one transistor and the other transistor of each differential pair, Two offset voltage forming circuits for outputting an input signal to one input terminal between the respective input terminals and for outputting the input signal by superimposing the input signal on the offset voltage are output to the other input terminal. It is what

In the frequency mixer circuit according to the sixth aspect of the invention; the two offset voltage forming circuits have one circuit for receiving the first AC signal and the other circuit for receiving the second AC signal; There is a case where the circuit inputs the sum signal or the difference signal of the first AC signal and the second AC signal and the input end of the other circuit is AC-grounded.

The offset voltage is formed by the voltage difference between the two transistors forming the offset voltage forming circuit, and the resistance interposed on the current source side of one transistor forming the offset voltage forming circuit. It may be formed by a voltage drop due to.

[0072]

Next, the operation of the frequency multiplication circuit and frequency mixer circuit of the present invention constructed as described above will be explained. The frequency multiplying circuit and the frequency mixer circuit of the present invention have the same configuration, except that there is one type or two types of AC input signals, and both circuits have the same configuration and both inputs of one differential pair. A DC output that has different DC bias voltages at its ends to realize the square characteristic, and the output ends of two differential pairs are cross-connected to form a differential output pair, and the input ends are connected via an offset voltage. It has a square connection and a square characteristic.

The frequency multiplying circuit and the frequency mixer circuit of the present invention are composed of MOS transistors, but even if there are two differential pairs, they are arranged in a so-called horizontal row, so that low voltage operation is possible in principle. In addition, since the minimum unit transistor is used, high-frequency operation is possible without increasing the circuit scale.

[0074]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a frequency multiplier circuit according to an embodiment of the present invention. This frequency multiplier circuit has a constant current source I of almost equal value.
Two differential pairs driven by ₀ {(M1, M2) (M3,
M4)}, the output terminal (drain) is cross-connected between the two differential pairs, that is,
The output terminals (drains) of M1 and M4 and the output terminals (drains) of M2 and M3 are commonly connected to form a differential output pair, and the input terminals (gates) have offset voltages V _K of substantially equal value. Through a stack, ie, M
A substantially equal offset voltage V _K is interposed between the input terminals (gates) of 1 and M3 and between the input terminals (gates) of M2 and M4 with the same polarity on the input terminal side of the transistors whose output terminals are commonly connected. There is.

Therefore, in the example of FIG. 1, the differential type in which the input signal (voltage V ₁ ) is applied between the input terminals of M1 and M4, this input signal is offset at the input terminals of M2 and M3. The voltage V _K is superimposed and applied. The offset voltage V _K may be generated using a battery, but may be generated using a transistor as shown in FIGS. 4 and 5.

In the above configuration, the differential pair (M1, M
The differential output current ΔI ₁ of 2) is calculated by the following formula 37, and formula 3
It can be written as 8.

[0077]

[Equation 37]

[0078]

ΔI ₁ = I ₀ sgn (V ₁ −V _K ) (| V ₁
−V _K | ≧ √ (I ₀ / β))

Similarly, the differential output current ΔI ₂ of the differential pair (M3, M4) is obtained by the equation 39 and can be represented by the equation 40.

[0080]

[Formula 39]

[0081]

ΔI ₂ = I ₀ sgn (V ₁ + V _K ) (│V ₁
+ V _K | ≧ √ (I ₀ / β))

Therefore, the differential output current ΔI obtained by striking the two differential pairs can be expressed by Equation 41, but Equation 3
7 can be approximated by the following Expression 42. The approximation error at this time is that the input voltage range is | V ₁ −V _K | ≦ √ (I ₀ / β)
In the range of, it is within 3%. Similarly, Expression 39 can be approximated by the following Expression 43.

[0083]

(41) ΔI = ΔI ₁ −ΔI ₂

[0084]

[Equation 42]

[0085]

[Equation 43]

That is, as is clear from the equations 42 and 43, since the term of the square of the input voltage V ₁ is included, the circuit of FIG. 1 is a doubler circuit. The transfer characteristic of this frequency multiplier circuit is shown in FIG. 2, and the transconductance characteristic is shown in FIG.

The frequency multiplication circuit of FIG.
It goes without saying that it can be also used as a single type in which an AC signal is applied to one input end of 4 and the other input end is grounded in an AC manner.

Next, FIGS. 4 and 5 show specific examples of the configuration of a frequency multiplication circuit in which an offset voltage forming circuit and an output circuit are added to the configuration of FIG. First, in FIG. 4, M5
And M6 and M7 and M8 form an offset voltage forming circuit, and M9 and M10 are active loads forming an output circuit.

The offset voltage forming circuit of this embodiment is
It is composed of two transistors driven with different current values, and the offset voltage V _K is formed by the voltage difference between these two transistors. That is, M5 and M8 are transistors that perform a source follower operation with I ₀₀ as a drive current and M6 and M7 as KI ₀₀ as a drive current. A signal (voltage V ₁ ) is applied, and the source of M5 is M3
Input terminal (gate) is connected, and the source of M6 is M1
Input terminal (gate) is connected, and M4 source is M4
Input terminal (gate) is connected, and M2 is connected to the source of M8.
Input terminal (gate) of is connected.

Therefore, the voltage difference (offset voltage) between M5 and M6 is applied between the input terminals of M1 and M3, and M4 and M6 are applied.
A voltage difference (offset voltage) between M8 and M7 is applied between the two input terminals. The input signal is directly applied to the input terminals of M1 and M4, but is applied to the input terminals of M3 and M2 while being superimposed on the offset voltage.

As a method of forming the offset voltage by the voltage difference between the two transistors, in addition to the method in which the driving current value is different, the driving current value is the same and the ability of the two transistors (the gate length and gate (Defined by the width ratio), a method of making both the drive current value and the ability different (hybrid system), and the like. In particular, in the hybrid system, the parameters can be selected according to weighting such as whether the chip size is emphasized or the current reduction is emphasized, so that the flexibility is excellent in the design and the circuit scale can be easily reduced.

FIG. 5 shows an example in which the offset voltage generating circuit is composed of one transistor (M11, M12), and the offset voltage is formed by the voltage drop of the resistor R ₁ inserted in each source. M11 and M12 are respectively a driven source follower operation substantially at constant current source I ₀₀ of equality, but the input terminals of the connected current source side to the input terminal of the source side of the resistor R ₁ inserted into M11 the source of M3 is M1 Respectively connected to. Similarly, the source side of the resistor R ₁ inserted in the source of M12 is connected to the input end of M2, and the current source side is connected to the input end of M4.

It goes without saying that the frequency multiplier circuits shown in FIGS. 4 and 5 can also be used as a single type.

Next, FIG. 6 shows a frequency mixer circuit according to an embodiment of the present invention. This frequency mixer circuit is composed of one differential pair (M1, M2) driven by a constant current source I ₀ , and the first AC signal (voltage V _RF ) is applied to the input terminal (gate) of M1. , M2 has a second input terminal (gate)
An alternating current signal (voltage V _LO ) is superimposed on the offset voltage V _K and applied.

In the above configuration, assuming that M1 and M2 operate in the saturation region, the drain current I _d1 is given by
4, the drain current I _d2 can be expressed by Equation 45, and the sum of both currents is the constant current source I ₀ (Equation 46).

[0096]

(44) I _d1 = β (V _GS1 −V _T ) ²

[0097]

(45) I _d2 = β (V _GS2- V _T ) ²

[0098]

(46) I _d1 + I _d2 = I ₀

Since the differential input voltage V _in can be expressed by the equation 47, the differential output current ΔI ₁ can be calculated from the equations 44 to 47 as follows.
Expressions 48 to 50 are obtained according to the range of the input voltage. However, in Expressions 48 to 50, Vμ is Vμ = √ (I
₀ / β).

[0100]

V _RF −V _LO −V _K = V _in

[0101]

[Equation 48]

[0102]

[Equation 49]

[0103]

[Equation 50]

The expression 48 can be approximated by the following expression 51.

[0105]

[Equation 51]

In the equation 51, the error is within 3% within the range of the input voltage | V _in | ≦ Vμ with respect to the equation 48 obtained from the square law of the MOS transistor and the equation 48. Then, comparing the current characteristic of the MOS transistor with the simulation value using the SPICE model represented by Shockley's equation, Equation 48 and SP
Equation 51 and S rather than the relationship with the ICE simulation value
The relation with the PICE simulation value has a better approximation relation. For the SPICE simulation value, the error is within 3% within the range of the input voltage | V _in | ≦ Vμ with respect to Formula 48.

Therefore, it can be said that the expression 51 is at a very good level as an approximate expression representing the input / output characteristics of the differential pair. When this formula 51 is expanded, it becomes a formula 52.

[0108]

[Equation 52]

[0109] The equation 51, the product of V _RF and V _LO V _RF V
_{Since LO} is included, the sum and difference components of the two frequencies can be obtained by Expressions 32, 33, and 34. Here, since I _d1 and I _d2 are differential currents, I _d1 is expressed by Formula 53 and I _d2 is expressed by Formula 54. Each contains ± (1/2) ΔI ₁ . Therefore, if ΔI ₁ or I _d1 and I _d2 are converted into a voltage, a frequency mixer circuit is obtained.

[0110]

(53) I _d1 = (I ₀ + ΔI ₁ ) / 2

[0111]

(54) I _d2 = (I ₀ −ΔI ₁ ) / 2

As described above, the offset voltage V _K can use the voltage difference between the two transistors whose input terminals (gates) are commonly connected, or the voltage drop of the resistor interposed between the sources of one transistor. However, in this case, the input signal to the transistor is the first AC signal and the second AC signal.
It may be a sum signal or a difference signal with the AC signal.

Then, as is clear from the above description,
If V _RF = V _LO , a frequency multiplication circuit is obtained.

Next, FIG. 7 shows a frequency mixer circuit according to another embodiment of the present invention. The frequency mixer circuit, two differential pairs are driven at substantially the constant current source I ₀ of equality {(M
1, M2) (M3, M4)}, and the output terminals (drains) of M1 and M3 and the output terminals (drains) of M2 and M4 are commonly connected between the two differential pairs. To form a differential output pair, between the input terminals (gates) of M1 and M4, and between the input terminals (gate) of M2 and M3.
Offset voltages V _K having substantially the same value are formed between the input terminals of the transistors whose output terminals are commonly connected with the same polarity. The above configuration is substantially the same as the configuration of FIG.

In this frequency mixer circuit, the first AC signal (voltage V _RF ) is applied to the input terminal of M1 and is applied to the input terminal of M4 while being superimposed on the offset voltage V _K , and the second AC signal (voltage V _LO ) Is applied to the input terminal of M3 and is applied to the input terminal of M2 while being superimposed on the offset voltage V _K.

In the above configuration, the differential output current ΔI can be calculated by the equation 55.

[0117]

[Equation 55]

[0118] In this equation 55, the product of V _RF and V _LO V _RF V
_{Since LO} is included, the sum and difference components of the two frequencies can be obtained by Expressions 32, 33, and 34. Here, since I ₁ and I ₂ are differential currents, I ₁ is expressed by Formula 56 and I ₂ is expressed by Formula 57. Each includes ± (1/2) ΔI. Therefore, a frequency mixer circuit can be obtained by converting ΔI or I ₁ and I ₂ into voltage.

[0119]

(56) I ₁ = I ₀ + ΔI / 2

[0120]

[Equation 57] I ₂ = I ₀ −ΔI / 2

In both the configurations of FIGS. 6 and 7, the first AC signal and the second AC signal are applied to different input terminals, so that the two signals are separated and a differential pair is formed. Since the transistor can be configured with the minimum size, the high frequency characteristics are not significantly deteriorated. In the MOS transistor, the input voltage range can be arbitrarily determined in consideration of the balance between √ (β / I ₀ ) and √ (βI ₀ ) = g _m . This point is essentially different from the bipolar transistor.

Further, in the configuration of FIG. 7, one signal input terminal may be provided, and the sum signal or the difference signal of the first AC signal and the second AC signal may be applied to the signal input terminal. Further, if one kind of AC signal is applied to the one signal input terminal, a frequency multiplication circuit is formed. The method of forming the offset voltage has been described above.

[0123]

As described above, the frequency multiplying circuit and the frequency mixer circuit of the present invention are different in that the AC input signals are of one type or of two types, and both circuits have the same configuration. There are two types of DC bias voltage at both input terminals of one differential pair, which realizes square characteristic.
The differential output pair is constructed by connecting the output ends of two differential pairs to each other, and the squared characteristic is realized by connecting the input ends to each other through an offset voltage.

Therefore, the frequency multiplication circuit and the frequency mixer circuit of the present invention are composed of MOS transistors,
Even when there are two differential pairs, they are arranged in a so-called horizontal row so that low voltage operation is possible in principle, and since the minimum unit transistor is used, the circuit scale does not increase and high frequency operation is possible. effective.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a frequency multiplication circuit according to a first embodiment of the present invention.

FIG. 2 is a transfer characteristic diagram of the frequency multiplication circuit of the present invention.

FIG. 3 is a transconductance characteristic diagram of the frequency multiplier circuit of the present invention.

FIG. 4 is a circuit diagram of a frequency multiplication circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a frequency multiplication circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram of a frequency mixer circuit according to the first embodiment of the present invention.

FIG. 7 is a circuit diagram of a frequency mixer circuit according to a second embodiment of the present invention.

FIG. 8 is a circuit diagram of a conventional frequency multiplication circuit.

FIG. 9 is a circuit diagram of a frequency mixer circuit including a Gilbert cell.

[Explanation of symbols]

I ₀ constant current source M1 to M16 MOS transistor V ₁ , V _LO , V _RF input voltage

Claims (8)

[Claims] 1. A differential circuit in which an AC signal or a first AC signal is applied to an input terminal of one transistor, and the AC signal or a second AC signal is applied to an input terminal of the other transistor in a state of being superimposed on an offset voltage. A frequency multiplication circuit or a frequency mixer circuit. 2. A differential pair; an AC signal, or
A circuit for inputting a sum signal or a difference signal of a first AC signal and a second AC signal to form an offset voltage between the input terminals of two transistors of the differential pair, wherein the input signal is input to the input terminal of one transistor. And an offset voltage forming circuit for outputting an input signal to the input terminal of the other transistor by superimposing the input signal on the offset voltage, and outputting the offset voltage forming circuit. 3. Two differential pairs driven by a substantially equal constant current source, between the output terminals of one transistor of each differential pair and the other between the two differential pairs. The output ends of the transistors are commonly connected to form a differential output pair, and an offset voltage of approximately equal value is shared between the input ends of one transistor and the other transistor of each differential pair. The input terminals of the connected transistors are formed to have the same polarity, and an AC signal is applied to one input terminal between the respective input terminals and an AC signal is applied to the other input terminal while being superimposed on the offset voltage; A frequency multiplier circuit characterized by the above. 4. Two differential pairs driven by a substantially constant current source, and between the two differential pairs, the output terminals of one transistor of each differential pair and the other. Two differential pairs that form a differential output pair by commonly connecting the output terminals of the respective transistors to each other; an output terminal being common between the input terminals of one transistor and the other transistor of each differential pair. Two circuits which form offset voltages of substantially equal value with the same polarity on the input side of the connected transistors, wherein an AC signal is applied to the input terminals of the two circuits, respectively, or An AC signal is applied to the input terminal and the other input terminal is grounded in an AC manner, the input signal is output to one input terminal between the respective input terminals, and the input signal is applied to the other input terminal by the offset voltage. Superimposed on and output Frequency multiplying circuit comprising the; two and the offset voltage forming circuit that. 5. Two differential pairs driven by a substantially equal constant current source, between the output terminals of one transistor of each differential pair and the other between the two differential pairs. The output ends of the transistors are commonly connected to form a differential output pair, and an offset voltage of approximately equal value is shared between the input ends of one transistor and the other transistor of each differential pair. The input terminals of the connected transistors are formed to have the same polarity, and the first AC signal is applied to one input terminal between the input terminals and the first AC signal is superimposed on the offset voltage at the other input terminal. A frequency mixer circuit characterized in that the second AC signal is applied to one input terminal between the other input terminals and the second AC signal is applied to the other input terminal while being superimposed on the offset voltage. 6. Two differential pairs driven by substantially equal constant current sources, wherein between the two differential pairs, the output terminals of one of the transistors of each differential pair and the other. Two differential pairs that form a differential output pair by commonly connecting the output terminals of the respective transistors to each other; an output terminal being common between the input terminals of one transistor and the other transistor of each differential pair. Two circuits that form offset voltages of substantially equal value with the same polarity on the input end side of the connected transistors, one of the two circuits receiving the first AC signal and the other circuit The second AC signal is input, or one circuit receives a sum signal or a difference signal of the first AC signal and the second AC signal, and the input end of the other circuit is AC-grounded, and One input end between each input end Frequency mixer circuit comprising the; outputs an input signal, the other input terminal and two offset voltage generating circuit for outputting an input signal superimposed on the offset voltage. 7. The frequency multiplier circuit or frequency mixer circuit according to claim 2, wherein the input terminals of the offset voltage forming circuit are commonly connected, and the offset voltage forming circuit is driven by different currents. It consists of two transistors,
Alternatively, two transistors having input terminals commonly connected and driven by substantially equal currents and having different capabilities, or two transistors connected commonly to the input terminals and driven by different currents. A frequency multiplier circuit or a frequency mixer circuit, wherein the offset voltage is formed by a voltage difference between the two transistors themselves. 8. The frequency multiplying circuit or frequency mixer circuit according to claim 2, said offset voltage forming circuit comprising one transistor; A frequency multiplier circuit or a frequency mixer circuit, which is formed by a voltage drop due to a resistance interposed between two transistors on the current source side.