JPH07240143A - Supersmall-sized field emission device improved with breakdown prevention insulated gate electrode and its accomplishment method - Google Patents
Supersmall-sized field emission device improved with breakdown prevention insulated gate electrode and its accomplishment methodInfo
- Publication number
- JPH07240143A JPH07240143A JP5198095A JP5198095A JPH07240143A JP H07240143 A JPH07240143 A JP H07240143A JP 5198095 A JP5198095 A JP 5198095A JP 5198095 A JP5198095 A JP 5198095A JP H07240143 A JPH07240143 A JP H07240143A
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- conductive layer
- layer
- cavity
- electron emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
- H01J9/02—Manufacture of electrodes or electrode systems
- H01J9/022—Manufacture of electrodes or electrode systems of cold cathodes
- H01J9/025—Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J3/00—Details of electron-optical or ion-optical arrangements or of ion traps common to two or more basic types of discharge tubes or lamps
- H01J3/02—Electron guns
- H01J3/021—Electron guns using a field emission, photo emission, or secondary emission electron source
- H01J3/022—Electron guns using a field emission, photo emission, or secondary emission electron source with microengineered cathode, e.g. Spindt-type
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Cold Cathode And The Manufacture (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、一般に真空超小型電界
放出デバイス(vacuum microelectronic field emission
device)に関し、より詳細には、改良電界放出デバイス
およびその実現方法に関する。FIELD OF THE INVENTION The present invention generally relates to vacuum microelectronic field emission devices.
device), and more particularly, to an improved field emission device and its implementation method.
【０００２】[0002]
【従来の技術】真空超小型電界放出デバイスは周知であ
る。電界放出デバイスの実現および動作の従来の方法
は、電子を放出する電子エミッタをキャビティ内に配置
された実質的に円錐(conical) ／くさび形(wedge) の構
造として形成すること，およびキャビティの周辺に配置
された導電性加速電極を設けることを含む。加速電極
（ゲート電極）と電子エミッタとの間に適切な電位を印
加すると、電子エミッタからの電子放出が誘導される。
実際には、この電界放出デバイスの電子エミッタは、電
子を捕集するために遠端に配置されたアノードであっ
て、これらの間に介在領域を形成するアノードと協調し
て動作する。放出された電子がアノードに到達し、それ
によって捕集されるために、電界放出デバイスは１０ー7
ないし１０ー9トル(Torr)台の真空環境で動作する。残留
圧力がそれより高いと、電子放出の存在下で、気体分子
の実質的なイオン化が起きることがある。さらに、電子
エミッタおよび加速電極の表面の汚染物質の脱離は、キ
ャビティの領域内の局部的残留ガス圧を著しく増加する
ことがある。そのように局部的に増加した残留ガスは、
アーク放電として観察される電界放出デバイスの破壊的
ブレークダウンを引き起こし、その結果しばしば、電界
放出デバイスの短絡を招き、必ず電子エミッタの破壊を
生じることは、既知の真空超小型電界放出デバイスの共
通した欠点である。Vacuum microminiature field emission devices are well known. Conventional methods of realization and operation of field emission devices include forming an electron emitting electron emitter as a substantially conical / wedge structure located within the cavity, and Providing a conductive accelerating electrode disposed at. When an appropriate potential is applied between the acceleration electrode (gate electrode) and the electron emitter, electron emission from the electron emitter is induced.
In practice, the electron emitter of this field emission device works in concert with the anode located at the far end to collect the electrons, forming an intervening region between them. Since the emitted electrons reach the anode and are thereby collected, the field emission device has a capacity of 10 −7.
To operate at 10 -9 Torr (Torr) stand a vacuum environment. Higher residual pressures can result in substantial ionization of gas molecules in the presence of electron emission. Moreover, desorption of contaminants on the surface of the electron emitter and acceleration electrode can significantly increase the local residual gas pressure in the region of the cavity. Such locally increased residual gas is
It is common to known vacuum micro field emission devices to cause destructive breakdown of the field emission device observed as an arc discharge, often resulting in a short circuit of the field emission device and always to destruction of the electron emitter. It is a drawback.
【０００３】[0003]
【発明が解決しようとする課題】したがって、少なくと
もこれらの欠点の幾つかを克服する超小型電界放出デバ
イス装置およびその実現方法に対する要求が存在する。Therefore, there is a need for microminiature field emission device arrangements and methods of implementation thereof that overcome at least some of these drawbacks.
【０００４】したがって、本発明の目的は、ゲートと電
子エミッタ間の破壊的放電の可能性を除去または実質的
に減少する絶縁ゲート電界放出デバイスを提供すること
である。Accordingly, it is an object of the present invention to provide an insulated gate field emission device that eliminates or substantially reduces the potential for destructive discharge between the gate and the electron emitter.
【０００５】本発明のさらなる目的は、まだ、既知では
ない電界増強機構（electric fieldenhancement mechan
ism）を設けた絶縁ゲート電界放出デバイスを提供する
ことである。A further object of the invention is an electric field enhancement mechanism which is not yet known.
ism) is provided.
【０００６】[0006]
【課題を解決するための手段】これらの要求やその他お
よび上述の目的やその他は、電子エミッタ，および周辺
に配置されたゲート抽出電極であって、これらの間に自
由空間領域を形成するゲート抽出電極を有する電界放出
デバイスを設け、前記ゲート抽出電極をその上に配置さ
れた絶縁層によって自由空間領域から実質的に絶縁する
ことによって、実質的に満たされる。Means for Solving the Problems These requirements and others and the above-mentioned objects and others are an electron emitter and a gate extraction electrode arranged in the periphery thereof, and a gate extraction for forming a free space region therebetween. It is substantially filled by providing a field emission device having an electrode, the gate extraction electrode being substantially insulated from the free space region by an insulating layer disposed thereon.
【０００７】この要求やその他および上述の目的やその
他は、主表面(major surface) を有する支持基板を設け
る段階，および前記支持基板の前記主表面上に第１絶縁
層を沈積し、前記第１絶縁層の上に導電層を沈積し、か
つ前記導電層の上に第２絶縁層を沈積する段階を含む電
界放出デバイスの形成方法を提供することによって、さ
らに満たされる。マスク層を第２絶縁層の上に沈積して
選択的にパターン化し、第１方向エッチングを実行し
て、キャビティが形成されるように第１および第２絶縁
層の材料の一部および導電層の材料の一部を除去し、そ
の後、マスク層を除去する。実質的に共形の絶縁層の沈
積を実行し、この絶縁層は残った第２絶縁層と共に第３
絶縁層を構成する。第２方向エッチング(second direct
ed etch)を実行して、第３絶縁層の材料の一部を除去
し、支持基板の主表面の一部を露出させ、その後、電子
エミッタをキャビティ内で支持基板の主表面上にそれと
動作可能に結合するように沈積し、第３絶縁層の残った
材料が導電層を、導電層と電子エミッタとの間に形成さ
れた自由空間領域から実質的に絶縁するようにする。This requirement and others and the above-mentioned purposes and others are provided by providing a supporting substrate having a major surface, and depositing a first insulating layer on the major surface of the supporting substrate, It is further satisfied by providing a method of forming a field emission device, comprising depositing a conductive layer on an insulating layer and depositing a second insulating layer on the conductive layer. A mask layer is deposited on the second insulating layer and selectively patterned and a first direction etch is performed to partially form the material of the first and second insulating layers and the conductive layer so that a cavity is formed. A part of the material is removed, and then the mask layer is removed. A substantially conformal deposition of an insulating layer is carried out, this insulating layer being the third with the remaining second insulating layer.
It constitutes an insulating layer. Second direction etching (second direct
ed etch) to remove a portion of the material of the third insulating layer and expose a portion of the major surface of the supporting substrate, and then move the electron emitter in the cavity onto the major surface of the supporting substrate. Deposited in a bondable manner such that the remaining material of the third insulating layer substantially insulates the conductive layer from the free space region formed between the conductive layer and the electron emitter.
【０００８】[0008]
【実施例】本発明による超小型電界放出デバイス１００
の一実施例の断面図を、図１に示す。主表面を有する支
持基板１０１が設けられる。基板１０１の主表面上に第
１絶縁層１０２が配置され、第１絶縁層１０２の上に導
電層１０３が配置される。導電層１０３は導電性材料ま
たは半導体材料のどちらでも形成することができ、「導
電性(conductive)」という用語は、この開示全体を通し
てどちらかを示すのに用いられることを理解されたい。
導電層は、後で説明するように、ゲート抽出電極１０３
として利用される。絶縁層１０２および導電層（電極１
０３）は、その中を貫通して形成された開口部（キャビ
ティ）１０５を有する。導電層（電極１０３）の上、お
よび絶縁層１０２および支持基板１０１の主表面の一部
の上のキャビティ１０５内に、第２絶縁層１０４が配置
される。電子エミッタ１０６はキャビティ１０５内に、
および支持基板１０１の主表面上にこれと動作可能に結
合されて配置される。アノード１０７は、電子エミッタ
１０６に対し遠端に配置され、これらの間に空間領域１
０８を形成する。EXAMPLE Microminiature field emission device 100 according to the present invention
A cross-sectional view of one embodiment is shown in FIG. A support substrate 101 having a main surface is provided. First insulating layer 102 is arranged on the main surface of substrate 101, and conductive layer 103 is arranged on first insulating layer 102. It is to be understood that the conductive layer 103 can be formed of either a conductive material or a semiconductor material, and the term “conductive” is used to indicate either throughout this disclosure.
The conductive layer is formed on the gate extraction electrode 103 as described later.
Used as. Insulating layer 102 and conductive layer (electrode 1
03) has an opening (cavity) 105 formed so as to penetrate therethrough. The second insulating layer 104 is disposed in the cavity 105 on the conductive layer (electrode 103) and on the insulating layer 102 and a part of the main surface of the supporting substrate 101. The electron emitter 106 is inside the cavity 105,
And operably coupled to and disposed on the major surface of support substrate 101. The anode 107 is arranged at the far end with respect to the electron emitter 106, and the space region 1 is provided between them.
08 is formed.
【０００９】ここに示した実施例では、超小型電界放出
デバイス１００を真空環境内に置き、そこに適切な電位
を動作可能に結合することによって、動作が実行され
る。図１に示すように、第１外部設置電位源１１０は、
ゲート電極１０３と基準電位（ここでは接地基準として
図示）との間に動作可能に接続され、第２外部電位源１
２０は、アノード１０７と基準電位との間に動作可能に
接続される。さらに、支持基板１０１は、基準電位に動
作可能に接続される。In the illustrated embodiment, operation is performed by placing the microminiature field emission device 100 in a vacuum environment and operatively coupling an appropriate electrical potential thereto. As shown in FIG. 1, the first externally installed potential source 110 is
The second external potential source 1 is operably connected between the gate electrode 103 and a reference potential (illustrated here as a ground reference).
20 is operably connected between the anode 107 and a reference potential. Further, the support substrate 101 is operably connected to the reference potential.
【００１０】図には示さないが予想される実施例とし
て、超小型電界放出デバイス１００は、基板１０１の主
表面上に配置された導電層を採用し、電子エミッタ１０
６を導電層上に配置し、導電層を基準電位に動作可能に
結合することができる。また、多数の電界放出デバイス
を配列として一般に採用し、電界放出デバイス装置を実
現することが知られる。この開示の図は、多数の電界放
出デバイスのそうした配列を表わす。As a possible embodiment, not shown, the microminiature field emission device 100 employs a conductive layer disposed on the major surface of the substrate 101 to allow the electron emitter 10
6 can be disposed on the conductive layer and operably coupled to the reference potential. It is also known that a large number of field emission devices are generally adopted as an array to realize a field emission device device. The figures in this disclosure represent such an array of multiple field emission devices.
【００１１】絶縁層１０４は、ゲート抽出電極１０３の
周囲に効果的分子不浸透エンベロープを提供する。した
がって、脱離した表面汚染物質および真空排気されなか
った雰囲気ガスによって部分的に構成され、ゲート抽出
電極１０３と電子エミッタ１０６との間に形成される自
由空間領域内に一般に存在する残留ガス成分は、キャビ
ティ１０５内のゲート抽出電極１０３付近に存在するこ
とができない。絶縁層１０４は、ゲート抽出電極１０３
と電子エミッタ１０６との間の破壊的アーク放電を防止
する障壁を効果的に確立する。The insulating layer 104 provides an effective molecular impervious envelope around the gate extraction electrode 103. Therefore, the residual gas component which is partially constituted by the desorbed surface contaminants and the ambient gas which has not been evacuated and which is generally present in the free space region formed between the gate extraction electrode 103 and the electron emitter 106 is , Cannot exist near the gate extraction electrode 103 in the cavity 105. The insulating layer 104 is the gate extraction electrode 103.
Effectively establishes a barrier that prevents destructive arcing between the emitter and the electron emitter 106.
【００１２】超小型電界放出デバイス１００は、曲率半
径の小さい幾何学的不連続を呈する電子エミッタ１０６
の一領域における電界増強の原理に基づいて作動する。
本開示の電界放出デバイス１００の場合、そのような領
域とは、円錐／くさび形電子エミッタ１０６の頂部であ
る。電界放出デバイス１００の様々な電極に印加される
電位によって得られる電界は、電子エミッタ１０６の形
状によって増強される。１より大きい比誘電率を有し、
厚みのある絶縁層１０４をキャビティ１０５内に設ける
ことによって、電子エミッタ１０６付近の電界はさらに
比例的に増大され、まだ既知ではない増大電界増強機構
が得られる。The micro field emission device 100 has an electron emitter 106 that exhibits a geometric discontinuity with a small radius of curvature.
It operates on the principle of electric field enhancement in one area.
For the field emission device 100 of the present disclosure, such a region is the top of the cone / wedge electron emitter 106. The electric field obtained by the potentials applied to the various electrodes of the field emission device 100 is enhanced by the shape of the electron emitter 106. Has a relative permittivity greater than 1,
By providing a thick insulating layer 104 within the cavity 105, the electric field near the electron emitter 106 is further proportionally increased, providing an as-yet-unknown enhanced electric field enhancement mechanism.
【００１３】本発明による絶縁ゲート抽出電極２０３を
採用した改良電界放出デバイスの別の実施例の断面図
を、図２に示す。図２では、前に図１に関連して述べた
特徴に対応する図面の特徴は、“２”で始まる同様の符
号を用いて参照する。図２はさらに、ゲート抽出電極２
０３の上に配置された第３絶縁層２３０，および絶縁層
２３０の上に配置された第２導電層２３１を示す。第３
外部設置電位源２４０は、導電層２３１と基準電位との
間に動作可能に接続される。A cross-sectional view of another embodiment of the improved field emission device employing the insulated gate extraction electrode 203 according to the present invention is shown in FIG. In FIG. 2, features in the drawing that correspond to features previously described in connection with FIG. 1 are referred to with like numerals starting with “2”. FIG. 2 further shows the gate extraction electrode 2
03 shows the third insulating layer 230 arranged on the insulating layer 230 and the second conductive layer 231 arranged on the insulating layer 230. Third
The externally installed potential source 240 is operably connected between the conductive layer 231 and the reference potential.
【００１４】超小型電界放出デバイス２００の動作は、
前に図１に関連して述べた超小型電界放出デバイス１０
０と同様である。第２導電層２３１を設けることによ
り、空間領域２０８を横断した後アノード２０７で捕集
される放出電子の好適な偏向が得られる。The operation of the microminiature field emission device 200 is as follows.
The microminiature field emission device 10 previously described in connection with FIG.
The same as 0. By providing the second conductive layer 231, a suitable deflection of the emitted electrons collected at the anode 207 after traversing the spatial region 208 is obtained.
【００１５】前に述べたように、第２絶縁層２０４を設
けることにより、ゲート抽出電極２０３は残留ガス成分
から遮断され、ゲート抽出電極２０３と電子エミッタ２
０６との間の破壊的アーク放電の可能性が除去される。
絶縁層２０４は比誘電率が１より大きいために、電子エ
ミッタ２０６の頂部で増強された電界の大きさをさらに
比例的に増大する。As described above, by providing the second insulating layer 204, the gate extraction electrode 203 is shielded from the residual gas component, and the gate extraction electrode 203 and the electron emitter 2 are separated.
The possibility of a destructive arc discharge to and from 06 is eliminated.
The insulating layer 204 has a relative permittivity of greater than 1 and thus further proportionally increases the magnitude of the enhanced electric field at the top of the electron emitter 206.
【００１６】図３ないし図６は、本発明による超小型電
界放出デバイスの一実施例を形成する方法の様々な段階
を実行することによって実現される部分構造の断面図で
ある。FIGS. 3-6 are cross-sectional views of substructures implemented by performing various steps of a method of forming an embodiment of a microminiature field emission device according to the present invention.
【００１７】図３は、主表面を有する支持基板３０１を
示す。主表面上に第１絶縁層３０２を沈積し、絶縁層３
０２の上に導電層３０３を沈積する。導電層３０３の上
に第２絶縁層３０４を沈積する。絶縁層３０４の上に、
選択的にパターン化されたマスク層３０５を沈積する。
層３０２ないし３０５の沈積は、例えば化学蒸着（ＣＶ
Ｄ），電子ビーム蒸着(electron-beam evaporation) ，
スパッタリング，プラズマ・エンハンスＣＶＤ，イオン
・ビーム蒸着，およびスピンオン蒸着の幾つかを含む多
くの周知の技術のいずれかによって実行することができ
る。FIG. 3 shows a supporting substrate 301 having a main surface. The first insulating layer 302 is deposited on the main surface to form the insulating layer 3
02, a conductive layer 303 is deposited. A second insulating layer 304 is deposited on the conductive layer 303. On top of the insulating layer 304,
Deposit selectively patterned mask layer 305.
Deposition of layers 302-305 may be performed, for example, by chemical vapor deposition (CV).
D), electron-beam evaporation,
It can be performed by any of a number of well-known techniques, including some of sputtering, plasma enhanced CVD, ion beam evaporation, and spin-on evaporation.
【００１８】図４は、図３に関連して述べた構造に本方
法の追加段階を実行した後の断面図を示す。この追加段
階は、第１方向エッチング段階を実行して、第１および
第２絶縁層３０２，３０４の材料の一部，および導電層
３０３の材料の一部を選択的に除去し、支持基板３０１
の主表面の一部を露出させ、キャビティ３０６を形成す
ることを含む。この方向エッチング段階は、例えば反応
性イオン・エッチング（ＲＩＥ：reactive ion etch ）
など周知の技術によって達成することができる。FIG. 4 shows a cross-sectional view after performing the additional steps of the method on the structure described in connection with FIG. In this addition step, a first direction etching step is performed to selectively remove a part of the material of the first and second insulating layers 302 and 304 and a part of the material of the conductive layer 303, and the supporting substrate 301.
Exposing a portion of the major surface of the substrate to form a cavity 306. This directional etching step can be performed, for example, by reactive ion etching (RIE).
It can be achieved by a well-known technique.
【００１９】図５は、図４に関連して述べた構造に本方
法の追加段階を実行した後の断面図を示す。この追加段
階は、マスク層３０５を除去すること，および実質的に
共形の絶縁層の沈積を実行することを含む。この絶縁層
は、残った第２絶縁層３０４と共に第３絶縁層３０８を
構成する。図に示すように、絶縁層３０８は導電層３０
３，絶縁層３０２の一部分，および支持基板３０１の主
表面の露出部分の上に沈積される。FIG. 5 shows a cross-sectional view after performing the additional steps of the method on the structure described in connection with FIG. This additional step includes removing the mask layer 305 and performing a substantially conformal insulating layer deposition. This insulating layer constitutes the third insulating layer 308 together with the remaining second insulating layer 304. As shown, the insulating layer 308 is the conductive layer 30.
3, deposited on a portion of the insulating layer 302 and an exposed portion of the main surface of the support substrate 301.
【００２０】図６は、図５に関連して前に述べた構造に
本方法の追加段階を実行した後の断面図を示す。この追
加段階は、第２方向エッチング（例えば、ＲＩＥなど）
を実行して絶縁層３０８の一部を除去し、支持基板３０
１の主表面の一部分を露出させることを含む。ここで、
実質的な追加量または厚さの絶縁層３０８を導電層３０
３の上部表面上に設けることにより、導電層３０３の上
部表面上に充分な厚さの絶縁層を維持しながら、第２方
向エッチングを実行することができる点に注意された
い。第２方向エッチング段階の後、電子エミッタ３１０
をキャビティ３０６内に、支持基板３０１の主表面上に
これと動作可能に結合するように沈積する。FIG. 6 shows a cross-sectional view after performing the additional steps of the method on the structure previously described in connection with FIG. This additional step is a second direction etch (eg, RIE, etc.)
To remove a part of the insulating layer 308 to remove the supporting substrate 30.
Exposing a portion of one of the major surfaces. here,
A substantially additional amount or thickness of insulating layer 308 is added to conductive layer 30.
Note that by providing it on the upper surface of No. 3, the second direction etching can be performed while maintaining an insulating layer of sufficient thickness on the upper surface of the conductive layer 303. After the second direction etching step, the electron emitter 310
Is deposited in the cavity 306 on the major surface of the support substrate 301 so as to be operatively associated therewith.
【００２１】図３ないし図６に関連して述べた本方法の
段階を実行することによって、絶縁ゲート抽出電極（導
電層３０３）を有する超小型電界放出デバイスが実現さ
れる。結果的に得られる絶縁ゲート電界放出デバイス
は、ゲートと電子エミッタ間の破壊的放電の可能性が除
去され、まだ既知ではない電界増強機構が設けられるの
で、先行技術に対する改良である。By carrying out the steps of the method described in connection with FIGS. 3 to 6, a microminiature field emission device having an insulated gate extraction electrode (conductive layer 303) is realized. The resulting insulated gate field emission device is an improvement over the prior art because it eliminates the possibility of a destructive discharge between the gate and the electron emitter and provides a field enhancement mechanism that is not yet known.
【００２２】図７ないし図１２は、本発明による超小型
電界放出デバイスの別の実施例を形成する別の方法の様
々な段階を実行することによって実現される部分構造の
断面図である。FIGS. 7-12 are cross-sectional views of substructures implemented by performing various steps of another method of forming another embodiment of a microminiature field emission device according to the present invention.
【００２３】図７は、主表面を持つ支持基板７０１を示
す。支持基板７０１の主表面上に第１絶縁層７０２を沈
積し、絶縁層７０２の上に第１導電層７０３を沈積す
る。導電層７０３の上に第２絶縁層７０４を沈積する。
絶縁層７０４の上に第２導電層７０５を沈積する。選択
的にパターン化されたマスク７０７を導電層７０５の上
に配置する。層７０２ないし７０７の沈積は、例えば化
学蒸着（ＣＶＤ），電子ビーム蒸着，スパッタリング，
プラズマ・エンハンスＣＶＤ，イオン・ビーム蒸着，お
よびスピンオン蒸着の幾つかをはじめとする多くの周知
の技術のいずれかによって実行することができる。FIG. 7 shows a supporting substrate 701 having a main surface. First insulating layer 702 is deposited on the main surface of support substrate 701, and first conductive layer 703 is deposited on insulating layer 702. A second insulating layer 704 is deposited on the conductive layer 703.
A second conductive layer 705 is deposited on the insulating layer 704. A selectively patterned mask 707 is placed over the conductive layer 705. Deposition of layers 702-707 can be performed, for example, by chemical vapor deposition (CVD), electron beam evaporation, sputtering,
It can be performed by any of a number of well-known techniques, including some of plasma enhanced CVD, ion beam deposition, and spin-on deposition.
【００２４】図８は、図７に関連して述べた構造に本方
法の追加段階を実行した後の断面図を示す。この追加段
階は、例えば反応性イオン・エッチングなどの第１方向
エッチングを実行して、導電層７０５および絶縁層７０
４の材料の一部を除去し、それによってそこを貫通する
第１開口部７０８を形成し、導電層７０３の一部分を露
出させる。FIG. 8 shows a cross-sectional view after performing the additional steps of the method on the structure described in connection with FIG. This additional step involves performing a first direction etch, such as a reactive ion etch, to conduct the conductive layer 705 and the insulating layer 70.
4 of the material is removed, thereby forming a first opening 708 therethrough, exposing a portion of the conductive layer 703.
【００２５】図９は、図８に関連して前に述べた構造に
本方法の追加段階を実行した後の断面図を示す。この追
加段階は、マスク層７０７を除去すること，および実質
的に共形の第３絶縁層７０９を導電層７０５の上，およ
び少なくとも部分的に開口部内部で、絶縁層７０４およ
び導電層７０３の露出部の上に沈積することを含む。図
１０は、図９に関連して最初に述べた構造に本方法の追
加段階を実行した後の状態を示す。この追加段階は、第
２方向エッチングを実行して絶縁層７０９の一部を除去
し、開口部７０８の内部の側壁だけを残すことを含む。
第２方向エッチングの後、例えば、金，クロム，および
アルミニウムの中の一つまたはそれ以上をはじめとする
材料から成るハード・マスク７１５を選択的に沈積す
る。次に、例えば、ＲＩＥなどの第３方向エッチングを
実行して、導電層７０３の材料の一部，および絶縁層７
０２の材料の一部を除去し、支持基板７０１の主表面の
少なくとも一部分を露出させる。第３方向エッチング段
階は、キャビティ７０８と実質的に同軸であるが、支持
基板７０１の主表面まで伸長するキャビティ７１６を形
成する。ハード・マスク７１５の選択的沈積は、例え
ば、低角材料蒸着（low angle material evaporation）
によって実行される。材料は実質的に導電層７０５およ
び絶縁層７０９の一部分の上にだけ沈積され、開口部８
０８内部には実質的に沈積されない。FIG. 9 shows a cross-sectional view after performing the additional steps of the method on the structure previously described in connection with FIG. This additional step includes removing the mask layer 707 and removing the substantially conformal third insulating layer 709 over the conductive layer 705 and at least partially within the opening of the insulating layer 704 and conductive layer 703. Including depositing on exposed areas. FIG. 10 shows the structure after the additional steps of the method have been carried out on the structure initially described in connection with FIG. This additional step includes performing a second direction etch to remove a portion of insulating layer 709, leaving only sidewalls inside opening 708.
After the second direction etch, a hard mask 715 of, for example, a material including one or more of gold, chromium, and aluminum is selectively deposited. Then, for example, a third direction etching such as RIE is performed to partially etch the material of the conductive layer 703 and the insulating layer 7.
A part of the material of 02 is removed to expose at least a part of the main surface of the supporting substrate 701. The third direction etching step forms a cavity 716 that is substantially coaxial with the cavity 708 but extends to the major surface of the support substrate 701. Selective deposition of hard mask 715 may be performed, for example, by low angle material evaporation.
Executed by Material is deposited substantially only over a portion of conductive layer 705 and insulating layer 709, opening 8
It is not substantially deposited inside 08.
【００２６】図１１は、図１０に関連して上述した構造
に本方法の追加段階を実行した後の状態を示す。この追
加段階は、ハード・マスク７１５を除去すること，およ
び実質的に共形の絶縁材料の第２沈積を実行することを
含み、この絶縁材料は絶縁層７０９と共に第４絶縁層７
２０を構成する。絶縁層７２０は、導電層７０５，絶縁
層７０９，導電層７０３，絶縁層７０２，および支持基
板７０１の露出主表面上にキャビティ７１６内で沈積さ
れる。FIG. 11 shows the structure after performing the additional steps of the method on the structure described above in connection with FIG. This additional step includes removing the hard mask 715 and performing a second deposition of a substantially conformal insulating material, which together with the insulating layer 709 is the fourth insulating layer 7.
Make up 20. Insulating layer 720 is deposited in cavity 716 on exposed major surfaces of conductive layer 705, insulating layer 709, conductive layer 703, insulating layer 702, and support substrate 701.
【００２７】図１２は、図１１に関連して前に述べた構
造に本方法の追加段階を実行した後の状態を示す。この
追加段階は、第３方向エッチングを実行して絶縁層７２
０の材料の一部を除去し、支持基板７０１の主表面の一
部分を露出させることを含む。第３方向エッチング段階
の後、キャビティ７１６内および支持基板７０１の主表
面上にこれと結合するように電子エミッタ７３０を沈積
する。FIG. 12 shows the structure after performing the additional steps of the method on the structure described above in connection with FIG. In this additional step, the third direction etching is performed to perform the insulating layer 72.
Removing a portion of the zero material to expose a portion of the major surface of support substrate 701. After the third direction etching step, an electron emitter 730 is deposited in the cavity 716 and on the main surface of the supporting substrate 701 so as to be bonded thereto.
【００２８】図７ないし図１２に関連して述べた方法の
段階を実行することによって、一体的に形成された電子
ビーム偏向電極（導電層７０５）を含み、絶縁ゲート抽
出電極（導電層７０３）を有する超小型電界放出デバイ
スが実現される。本発明の絶縁ゲート電界放出デバイス
は、ゲートと電子エミッタ間の破壊的放電の可能性が除
去され、まだ既知ではない電界増強機構が設けられるの
で、先行する電界放出デバイスに対する改良である。By carrying out the steps of the method described in connection with FIGS. 7-12, an integrally formed electron beam deflection electrode (conductive layer 705) and an insulated gate extraction electrode (conductive layer 703) are included. A micro-field emission device having is realized. The insulated gate field emission device of the present invention is an improvement over the preceding field emission device because the possibility of a destructive discharge between the gate and the electron emitter is eliminated and a field enhancement mechanism not yet known is provided.
【図１】本発明による絶縁抽出電極を有する改良電界放
出デバイスの一実施例の側面断面図である。1 is a side cross-sectional view of one embodiment of an improved field emission device having an insulated extraction electrode according to the present invention.
【図２】本発明による絶縁抽出電極を有する改良電界放
出デバイスの別の実施例の側面断面図である。FIG. 2 is a side cross-sectional view of another embodiment of the improved field emission device having an insulated extraction electrode according to the present invention.
【図３】本発明による絶縁抽出電極を有する改良電界放
出デバイスの一実施例を形成する方法の様々な段階を実
行することによって、実現される部分構造の側面断面図
である。FIG. 3 is a side cross-sectional view of a substructure realized by performing various steps of a method of forming an embodiment of an improved field emission device having an insulated extraction electrode according to the present invention.
【図４】本発明による絶縁抽出電極を有する改良電界放
出デバイスの一実施例を形成する方法の様々な段階を実
行することによって、実現される部分構造の側面断面図
である。FIG. 4 is a side cross-sectional view of a substructure realized by performing various steps of a method of forming an embodiment of an improved field emission device having an insulated extraction electrode according to the present invention.
【図５】本発明による絶縁抽出電極を有する改良電界放
出デバイスの一実施例を形成する方法の様々な段階を実
行することによって、実現される部分構造の側面断面図
である。FIG. 5 is a side cross-sectional view of a substructure realized by performing various steps of a method of forming an embodiment of an improved field emission device having an insulated extraction electrode according to the present invention.
【図６】本発明による絶縁抽出電極を有する改良電界放
出デバイスの一実施例を形成する方法の様々な段階を実
行することによって、実現される部分構造の側面断面図
である。FIG. 6 is a side cross-sectional view of a substructure realized by performing various steps of a method of forming an embodiment of an improved field emission device having an insulated extraction electrode according to the present invention.
【図７】本発明による絶縁抽出電極を有する改良電界放
出デバイスの一実施例を形成する別の方法の様々な段階
を実行することによって、実現される部分構造の側面断
面図である。FIG. 7 is a side cross-sectional view of a substructure realized by performing various steps of another method of forming an embodiment of an improved field emission device having an insulated extraction electrode according to the present invention.
【図８】本発明による絶縁抽出電極を有する改良電界放
出デバイスの一実施例を形成する別の方法の様々な段階
を実行することによって、実現される部分構造の側面断
面図である。FIG. 8 is a side cross-sectional view of a substructure realized by performing various steps of another method of forming an embodiment of an improved field emission device having an insulated extraction electrode according to the present invention.
【図９】本発明による絶縁抽出電極を有する改良電界放
出デバイスの一実施例を形成する別の方法の様々な段階
を実行することによって、実現される部分構造の側面断
面図である。FIG. 9 is a side cross-sectional view of a substructure realized by performing various steps of another method of forming an embodiment of an improved field emission device having an insulated extraction electrode according to the present invention.
【図１０】本発明による絶縁抽出電極を有する改良電界
放出デバイスの一実施例を形成する別の方法の様々な段
階を実行することによって、実現される部分構造の側面
断面図である。FIG. 10 is a side cross-sectional view of a substructure realized by performing various steps of another method of forming an embodiment of an improved field emission device having an insulated extraction electrode according to the present invention.
【図１１】本発明による絶縁抽出電極を有する改良電界
放出デバイスの一実施例を形成する別の方法の様々な段
階を実行することによって、実現される部分構造の側面
断面図である。FIG. 11 is a side cross-sectional view of a substructure realized by performing various steps of another method of forming an embodiment of an improved field emission device having an insulated extraction electrode according to the present invention.
【図１２】本発明による絶縁抽出電極を有する改良電界
放出デバイスの一実施例を形成する別の方法の様々な段
階を実行することによって、実現される部分構造の側面
断面図である。FIG. 12 is a side cross-sectional view of a substructure realized by performing various steps of another method of forming an embodiment of an improved field emission device having an insulated extraction electrode according to the present invention.
１００ 超小型電界放出デバイス １０１ 支持基板 １０２ 第１絶縁層 １０３ 導電層（電極） １０４ 第２絶縁層 １０５ キャビティ １０６ 電子エミッタ １０８ 空間領域 １１０ 第１外部電位源 １２０ 第２外部電位源 ２００ 改良電界放出デバイス ２０３ 絶縁ゲート抽出電極 ２０４ 第２絶縁層 ２０６ 電子エミッタ ２０７ アノード ２０８ 空間領域 ２３０ 第３絶縁層 ２３１ 第２導電層 ２４０ 第３外部電位源 100 Microminiature field emission device 101 Support substrate 102 First insulating layer 103 Conductive layer (electrode) 104 Second insulating layer 105 Cavity 106 Electron emitter 108 Spatial region 110 First external potential source 120 Second external potential source 200 Improved field emission device 203 Insulated gate extraction electrode 204 Second insulating layer 206 Electron emitter 207 Anode 208 Spatial region 230 Third insulating layer 231 Second conductive layer 240 Third external potential source
Claims (7)
置されたゲート抽出電極（１０３）によって構成され、
両者間に自由空間領域（１０５）が形成される電界放出
デバイス（１００）であって、前記ゲート抽出電極がそ
の上に配置された絶縁層（１０４）によって前記自由空
間領域から実質的に絶縁されることを特徴とする電界放
出デバイス。1. An electron emitter (106) and a gate extraction electrode (103) arranged in the periphery,
A field emission device (100) having a free space region (105) formed therebetween, the gate extraction electrode being substantially insulated from the free space region by an insulating layer (104) disposed thereon. A field emission device characterized in that
記主表面の上に配置された第１絶縁層（１０２）；前記
第１絶縁層の上に配置された導電層（１０３）；前記導
電層（１０３）および前記第１絶縁層（１０２）を介し
て形成され、前記支持基板（１０１）の主表面の一部分
を露出させるキャビティ（１０５）であって、前記導電
層（１０３）内にゲート抽出電極を形成する前記キャビ
ティ（１０５）；前記導電層（１０３），前記第１絶縁
層（１０２）の一部分，および前記支持基板（１０１）
の露出された主表面の上に配置された第２絶縁層（１０
４）；および前記キャビティ（１０５）の内部および前
記支持基板（１０１）の前記主表面の上にこれと動作可
能に結合するように配置された電子を放出するための電
子エミッタ（１０６）であって、前記第２絶縁層（１０
４）が前記導電層（１０３）を、前記ゲート抽出電極
（１０３）と前記電子エミッタ（１０６）との間の自由
空間領域（１０５）から実質的に絶縁して、破壊的アー
ク放電の発生を防止すると共に、前記電子エミッタに増
大した電界増強の機構を設けて成る電子エミッタ；によ
って構成されることを特徴とする電界放出デバイス（１
００）。2. A supporting substrate (101) having a main surface; a first insulating layer (102) arranged on the main surface; a conductive layer (103) arranged on the first insulating layer; A cavity (105) which is formed through a conductive layer (103) and the first insulating layer (102) and exposes a part of the main surface of the supporting substrate (101) in the conductive layer (103). The cavity (105) forming a gate extraction electrode; the conductive layer (103), a portion of the first insulating layer (102), and the supporting substrate (101).
A second insulating layer (10) disposed over the exposed major surface of the
4); and an electron emitter (106) for emitting electrons arranged inside the cavity (105) and on the major surface of the support substrate (101) so as to be operatively coupled thereto. The second insulating layer (10
4) substantially insulates the conductive layer (103) from the free space region (105) between the gate extraction electrode (103) and the electron emitter (106) to prevent destructive arcing. A field emission device (1) which is configured to prevent the above-mentioned electron emitter from being provided with an increased electric field enhancement mechanism;
00).
供する段階；前記支持基板（３０１）の前記主表面の上
に第１絶縁層（３０２）を沈積する段階；前記第１絶縁
層（３０２）の上に導電層（３０３）を沈積する段階；
前記導電層（３０３）の上に第２絶縁層（３０４）を沈
積する段階；前記第２絶縁層（３０４）の上にマスク層
（３０５）を沈積し、選択的にパターン化する段階；第
１方向エッチングを実行して、前記第１および第２絶縁
層（３０２，３０４）の材料の一部，および前記導電層
（３０３）の材料の一部を除去し、キャビティ（３０
６）を形成する段階；前記マスク層（３０５）を除去す
る段階；実質的に共形の絶縁層の沈積を実行して、前記
残った第２絶縁層（３０４）と共に第３絶縁層（３０
８）を形成する段階；第２方向エッチングを実行して、
前記第３絶縁層（３０８）の材料の一部を除去し、前記
支持基板（３０１）の主表面の一部分を露出させる段
階；および前記キャビティ（３０６）の内部および前記
支持基板（３０１）の主表面の上にこれと動作可能に結
合するように電子エミッタ（３１０）を沈積する段階で
あって、それによって前記第３絶縁層（３０８）の残っ
た材料が前記導電層（３０３）を、前記導電層（３０
３）と前記電子エミッタ（３１０）との間に形成される
自由空間領域（３０６）から実質的に絶縁させる段階；
によって構成されることを特徴とする電界放出デバイス
の形成方法。3. Providing a supporting substrate (301) having a major surface; depositing a first insulating layer (302) on the major surface of the supporting substrate (301); Depositing a conductive layer (303) on top of 302);
Depositing a second insulating layer (304) on the conductive layer (303); depositing a mask layer (305) on the second insulating layer (304) and selectively patterning; One-way etching is performed to remove a portion of the material of the first and second insulating layers (302, 304) and a portion of the material of the conductive layer (303) to remove the cavity (30
6); removing the mask layer (305); performing a deposition of a substantially conformal insulating layer to form a third insulating layer (30) with the remaining second insulating layer (304).
8) forming step; performing second direction etching,
Removing a portion of the material of the third insulating layer (308) to expose a portion of the major surface of the support substrate (301); and the interior of the cavity (306) and the major portion of the support substrate (301). Depositing an electron emitter (310) on the surface so as to be operatively associated therewith, whereby the remaining material of the third insulating layer (308) causes the conductive layer (303) to move to the conductive layer (303). Conductive layer (30
3) substantially isolating from the free space region (306) formed between the electron emitter (310);
A method of forming a field emission device, comprising:
に配置された第１絶縁層；前記第１絶縁層の上に配置さ
れた第１導電層；前記第１導電層の上に配置された第２
絶縁層；前記第２絶縁層の上に配置された第２導電層；
前記第２導電層，前記第２絶縁層、前記第１導電層，お
よび前記第１絶縁層を介して形成されるキャビティであ
って、前記支持基板の前記主表面が前記キャビティ内で
露出し、前記キャビティは前記第１導電層にゲート抽出
電極を形成し、かつ前記第２導電層に電子偏向電極を形
成して成るキャビティ；前記第２絶縁層，前記第１導電
層，前記第１絶縁層，および前記支持基板の露出された
主表面の一部分の上に前記キャビティ内に配置された第
３絶縁層；および前記キャビティの内部および前記支持
基板の主表面の上にこれと動作可能に結合するように配
置された電子を放出するための電子エミッタであって、
前記第３絶縁層が前記第１導電層を、前記ゲート抽出電
極と前記電子エミッタとの間の自由空間領域から実質的
に絶縁して、前記破壊的アーク放電の発生を防止すると
共に、前記電子エミッタに増大した電界増強の機構を設
けて成る電子エミッタ；によって構成されることを特徴
とする電界放出デバイス。4. A support substrate having a main surface; a first insulating layer arranged on the main surface; a first conductive layer arranged on the first insulating layer; arranged on the first conductive layer. The second done
An insulating layer; a second conductive layer disposed on the second insulating layer;
A cavity formed through the second conductive layer, the second insulating layer, the first conductive layer, and the first insulating layer, wherein the main surface of the support substrate is exposed in the cavity, The cavity is formed by forming a gate extraction electrode on the first conductive layer and forming an electron deflection electrode on the second conductive layer; the second insulating layer, the first conductive layer, the first insulating layer. , And a third insulating layer disposed in the cavity over a portion of the exposed major surface of the support substrate; and operably coupled to the interior of the cavity and over the major surface of the support substrate. An electron emitter for emitting electrons arranged as
The third insulating layer substantially insulates the first conductive layer from a free space region between the gate extraction electrode and the electron emitter to prevent the destructive arc discharge from occurring and to prevent the electrons from being generated. A field emission device comprising an electron emitter comprising an emitter provided with an increased electric field enhancement mechanism.
れたアノードであって、前記電子エミッタと前記アノー
ドとの間に空間領域が形成されて成るアノードをさらに
含むことを特徴とする請求項４記載の電界放出デバイ
ス。5. The anode further arranged distally to the electron emitter, the anode further comprising a space region formed between the electron emitter and the anode. 4. The field emission device according to 4.
動作可能に結合された第１外部設置電位源；前記アノー
ドと前記基準電位との間に動作可能に結合された第２外
部設置電位源；前記電子偏向電極と前記基準電位との間
に動作可能に結合された第３外部設置電位源；および第
２，第３，および第１外部設置電位源によってそれぞれ
前記アノード，電子偏向電極，およびゲート抽出電極に
適切な電位が印加されると、電子が前記電子エミッタか
ら放出され、前記空間領域の範囲を横断し、その後前記
アノードに捕集されるように設けた前記支持基板の基準
電位への動作可能な接続；によってさらに構成されるこ
とを特徴とする請求項５記載の電界放出デバイス。6. A first external ground potential source operably coupled between the gate extraction electrode and a reference potential; a second external ground potential operably coupled between the anode and the reference potential. A source; a third externally placed potential source operably coupled between the electron deflection electrode and the reference potential; and a second, third, and first externally placed potential source for the anode, the electron deflection electrode, respectively. And an appropriate potential is applied to the gate extraction electrode, electrons are emitted from the electron emitter, traverse the area of the spatial region, and are then provided with a reference potential of the supporting substrate arranged to be collected by the anode. 6. The field emission device of claim 5, further comprising an operable connection to.
階；前記主表面の上に第１絶縁層を沈積する段階；前記
第１絶縁層の上に第１導電層を沈積する段階；前記第１
導電層の上に第２絶縁層を沈積する段階；前記第２絶縁
層の上に第２導電層を沈積する段階；前記第２絶縁層の
上にマスク層を沈積し、選択的にパターン化する段階；
第１方向エッチングを実行して、前記第２導電層の材料
の一部，および前記第２絶縁層の材料の一部を除去し、
それらを介し第１導電層の一部を露出させる開口部を形
成する段階であって、前記開口部によってさらに前記第
２導電層に電子偏向電極が形成される段階；前記マスク
層を除去する段階；前記第２導電層，前記第２絶縁層，
および前記第１導電層の前記露出部分の上に実質的に共
形の第３絶縁層を沈積する段階；第２方向エッチングを
実行して、前記第３絶縁層の材料の一部を除去する段
階；前記第２導電層および前記第３絶縁層の一部分の上
にハード・マスクを選択的に沈積する段階；前記ハード
・マスクを利用して第３方向エッチングを実行し、前記
第１導電層および前記第１絶縁層の材料の一部を除去し
て、前記支持基板の主表面の一部分を露出させ、前記開
口部と整列するキャビティを形成する段階であって、前
記キャビティによって前記第１導電層にゲート抽出電極
が形成される段階；前記ハード・マスクを除去する段
階；実質的に共形の絶縁材料の第２沈積を実行する段階
であって、前記絶縁材料は前記第３絶縁層と共に、前記
第２導電層，前記第２絶縁層，前記第１導電層，前記第
１絶縁層、および前記支持基板の主表面の露出部分の上
に前記キャビティ内に沈積された第４絶縁層を構成する
段階；第３方向エッチングを実行して、前記第４絶縁層
の材料の一部を除去し、前記支持基板の主表面の一部分
を前記キャビティ内に露出させる段階；および前記キャ
ビティの内部および前記支持基板の主表面の上にこれと
動作可能に結合するように電子エミッタを沈積する段階
であって、それによって前記第３絶縁層の残った材料が
前記ゲート抽出電極を、前記導電層と前記電子エミッタ
との間に形成される自由空間領域から実質的に絶縁させ
る段階；によって構成されることを特徴とする電界放出
デバイスの形成方法。7. A support substrate having a major surface; a first insulating layer deposited on the major surface; a first conductive layer deposited on the first insulating layer; 1
Depositing a second insulating layer on the conductive layer; depositing a second conductive layer on the second insulating layer; depositing a mask layer on the second insulating layer and selectively patterning Stage of doing;
Performing a first direction etching to remove a portion of the material of the second conductive layer and a portion of the material of the second insulating layer,
Forming an opening exposing a part of the first conductive layer through them, forming an electron deflection electrode in the second conductive layer by the opening; removing the mask layer The second conductive layer, the second insulating layer,
And depositing a substantially conformal third insulating layer on the exposed portion of the first conductive layer; performing a second direction etch to remove a portion of the material of the third insulating layer. Selectively depositing a hard mask on a portion of the second conductive layer and a portion of the third insulating layer; performing a third direction etch using the hard mask, and etching the first conductive layer. And removing a portion of the material of the first insulating layer to expose a portion of the main surface of the support substrate to form a cavity aligned with the opening, the first conductive layer being formed by the cavity. Forming a gate extraction electrode in the layer; removing the hard mask; performing a second deposition of a substantially conformal insulating material, the insulating material together with the third insulating layer , The second conductive layer, the second Forming a fourth insulating layer deposited in the cavity on the edge layer, the first conductive layer, the first insulating layer, and the exposed portion of the main surface of the supporting substrate; performing third-direction etching Removing a portion of the material of the fourth insulating layer and exposing a portion of the major surface of the support substrate into the cavity; and this within the cavity and on the major surface of the support substrate. Depositing an electron emitter to operatively couple with the remaining material of the third insulating layer to form the gate extraction electrode between the conductive layer and the electron emitter. A method of forming a field emission device, the method comprising: substantially insulating from a free space region.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/200,036 US5442193A (en) | 1994-02-22 | 1994-02-22 | Microelectronic field emission device with breakdown inhibiting insulated gate electrode |
| US200036 | 1994-02-22 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07240143A true JPH07240143A (en) | 1995-09-12 |
| JP3216688B2 JP3216688B2 (en) | 2001-10-09 |
Family
ID=22740055
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5198095A Expired - Fee Related JP3216688B2 (en) | 1994-02-22 | 1995-02-17 | Improved micro field emission device having insulated gate electrode for preventing breakdown and method of realizing the same |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5442193A (en) |
| EP (1) | EP0668603B1 (en) |
| JP (1) | JP3216688B2 (en) |
| DE (1) | DE69506456T2 (en) |
| TW (1) | TW366589B (en) |
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| US6018215A (en) * | 1996-11-22 | 2000-01-25 | Nec Corporation | Field emission cold cathode having a cone-shaped emitter |
| US6369496B1 (en) | 1997-12-03 | 2002-04-09 | Nec Corporation | Micro cold cathode with shield member |
| KR100413815B1 (en) * | 2002-01-22 | 2004-01-03 | 삼성에스디아이 주식회사 | Carbon nano tube field emitter device in triode structure and its fabricating method |
| JP2006127794A (en) * | 2004-10-26 | 2006-05-18 | Canon Inc | Image display device |
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| US5731228A (en) * | 1994-03-11 | 1998-03-24 | Fujitsu Limited | Method for making micro electron beam source |
| EP0696042B1 (en) * | 1994-08-01 | 1999-12-01 | Motorola, Inc. | Field emission device arc-suppressor |
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| US5844370A (en) | 1996-09-04 | 1998-12-01 | Micron Technology, Inc. | Matrix addressable display with electrostatic discharge protection |
| US5719406A (en) * | 1996-10-08 | 1998-02-17 | Motorola, Inc. | Field emission device having a charge bleed-off barrier |
| US5760535A (en) * | 1996-10-31 | 1998-06-02 | Motorola, Inc. | Field emission device |
| JP3044603B2 (en) * | 1997-01-08 | 2000-05-22 | 双葉電子工業株式会社 | Method of manufacturing field emission device |
| US5866978A (en) * | 1997-09-30 | 1999-02-02 | Fed Corporation | Matrix getter for residual gas in vacuum sealed panels |
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| JP2000235832A (en) * | 1998-07-23 | 2000-08-29 | Sony Corp | Cold cathode field electron emission device, cold cathode field electron emission type display device and these manufacture |
| GB2339961B (en) * | 1998-07-23 | 2001-08-29 | Sony Corp | Processes for the production of cold cathode field emission devices and cold cathode field emission displays |
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Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2012192A1 (en) * | 1970-03-14 | 1971-10-07 | Philips Nv | Electrical discharge tubes with a cathode consisting of an insulating layer lying between two conductive layers, and a method for producing a cathode intended for such a discharge tube |
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| US5079476A (en) * | 1990-02-09 | 1992-01-07 | Motorola, Inc. | Encapsulated field emission device |
| FR2663462B1 (en) * | 1990-06-13 | 1992-09-11 | Commissariat Energie Atomique | SOURCE OF ELECTRON WITH EMISSIVE MICROPOINT CATHODES. |
| US5030895A (en) * | 1990-08-30 | 1991-07-09 | The United States Of America As Represented By The Secretary Of The Navy | Field emitter array comparator |
-
1994
- 1994-02-22 US US08/200,036 patent/US5442193A/en not_active Expired - Fee Related
-
1995
- 1995-01-05 TW TW084100044A patent/TW366589B/en active
- 1995-02-16 EP EP95102137A patent/EP0668603B1/en not_active Expired - Lifetime
- 1995-02-16 DE DE69506456T patent/DE69506456T2/en not_active Expired - Fee Related
- 1995-02-17 JP JP5198095A patent/JP3216688B2/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6018215A (en) * | 1996-11-22 | 2000-01-25 | Nec Corporation | Field emission cold cathode having a cone-shaped emitter |
| US6369496B1 (en) | 1997-12-03 | 2002-04-09 | Nec Corporation | Micro cold cathode with shield member |
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| JP2006127794A (en) * | 2004-10-26 | 2006-05-18 | Canon Inc | Image display device |
| WO2008007928A1 (en) * | 2006-07-13 | 2008-01-17 | Photegra Corporation | Photocathode lighting device, method for manufacturing the same and exposure apparatus using photocathode lighting device |
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Also Published As
| Publication number | Publication date |
|---|---|
| DE69506456D1 (en) | 1999-01-21 |
| JP3216688B2 (en) | 2001-10-09 |
| TW366589B (en) | 1999-08-11 |
| EP0668603B1 (en) | 1998-12-09 |
| US5442193A (en) | 1995-08-15 |
| EP0668603A1 (en) | 1995-08-23 |
| DE69506456T2 (en) | 1999-07-22 |
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