JPH07235649A - Manufacture of non-volatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To lessen a memory cell enough in area through a simple manufacturing process by a method wherein a second conductive film is connected between adjacent semiconductor square rods, a flattening insulting film is buried between the semiconductor square rods, and a wiring layer connected to a first conductivity type conductive layer above the semiconductor square rods is formed. CONSTITUTION:A polysilicon 117 formed on the side wall of a semiconductor square rod 107 is made to serve as a floating gate, and a polysilicon film 121 formed surrounding the floating gate is made to serve as a control gate 121. As a floating gate is formed on the side wall of a semiconductor square rod, it can be formed in a self-aligned manner. Furthermore, semiconductor square rods are reduced in space between them by the thickness of a floating gate, so that the polysilicon 121 is connected between adjacent semiconductor square rods when a polysilicon 121 is formed on the side wall of the floating gate through the intermediary of an insulating film 119. In result, a word line-shaped control gate connected between adjacent semiconductor square rods can be formed in a self-aligned manner.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device. In particular, it relates to a method for manufacturing a non-volatile memory cell in which memory cells are arranged at a high density.

[0002]

2. Description of the Related Art Conventionally, in a nonvolatile semiconductor memory device, a MOS transistor in which a floating gate and a control gate are stacked and formed with an insulating film on a channel region between a semiconductor substrate and a source and drain of opposite conductivity type is used as a memory. It is used as a cell. However, when a large-capacity semiconductor memory device is realized by using this memory cell, the contact area for connecting the bit line and the drain (usually one contact area for every two memory cells) is densified. It was an obstacle.

Here, in order to significantly reduce the ratio of the contact region per memory cell, a nonvolatile semiconductor memory device using a memory cell in which the sources and drains of a plurality of stacked gate type MOS transistors are connected in series has been proposed. It has been developed. NA for such memory cells
It is called an ND type memory cell, and the memory cells before it are NO.
It is called an R-type memory cell.

Assuming that the minimum processing line width is F, the NAND type memory cell ideally stores information per bit of 6F.
It can be realized in ² areas. However, for example, 16
In the case of a NAND type memory cell in which memory cells are connected in series, a contact is still required for every 32 bits, and it is also necessary to provide two kinds of select transistors on the source side and the drain side. As a result, the memory cell area cannot be reduced to an ideal level.

[0005]

As described above, a NAND type memory cell has been developed in order to reduce the memory cell area. However, since there is a bit line contact, a select transistor, etc., the cell area is sufficiently reduced. There is a problem that it cannot be reduced. Furthermore, NOR type, NAN
There is also a problem in that the number of steps including mask alignment increases because a step of separating the floating gate for each memory cell is required for both the D type. The present invention eliminates the above drawbacks,
An object of the present invention is to provide a method for manufacturing a non-volatile semiconductor memory device which realizes a high density memory cell by a simple manufacturing process.

[0006]

In order to achieve the above object, in the present invention, as a first means, a first semiconductor substrate is used.
A step of forming a plurality of semiconductor prisms adjacent to each other by laminating conductive layers in the order of a first conductivity type, a second conductivity type, and a first conductivity type on a conductivity type semiconductor region; Forming a separate first conductive film on the side wall of the conductive type conductive layer region via the first insulating film; and forming a second conductive film on the side wall via the second insulating film. , A step of connecting the second conductive film between a plurality of adjacent semiconductor prisms, a step of embedding a planarization insulating film between the semiconductor prisms, and a step of connecting the first conductive type conductive layer above the semiconductor prisms. A method for manufacturing a non-volatile semiconductor memory device, comprising the step of forming a wiring layer.

As a second means, a step of forming an insulating film for element isolation on a semiconductor region of the first conductivity type of a semiconductor substrate and forming openings adjacent to each other and reaching the semiconductor region, and (a) semiconductor A step of forming a plurality of semiconductor prisms adjacent to each other by laminating conductive layers in the order of a first conductivity type, a second conductivity type, and a first conductivity type that are directly or indirectly connected to a region, and (b) Forming independent first conductive films on the sidewalls of the second conductive type conductive layer region of the semiconductor prism through the first insulating film; and (c) forming a plurality of first conductive films on the sidewalls of the first conductive films. A step of forming a second conductive film via the second insulating film and connecting the second conductive film between a plurality of adjacent semiconductor prisms; and (d) embedding a planarizing insulating film between the semiconductor prisms. And (a), (b),
A step of forming a wiring layer connected to the first conductive type conductive layer of the uppermost semiconductor prism, after repeating the steps (c) and (d) a plurality of times in sequence. A method for manufacturing a semiconductor memory device is provided.

[0008]

When the first means provided by the present invention is used, the first conductive film formed on the side wall of the semiconductor prism is used as a floating gate, and the second conductive film formed around the floating gate is controlled. Acts as a gate. Since the floating gate is formed on the side wall of the semiconductor prism, the step of cutting off the floating gate for each cell by mask alignment is not necessary, and can be so-called self-aligned. Further, the gap between the semiconductor prisms is narrowed due to the film thickness of the floating gate. Therefore, when the second conductive film is formed on the sidewall of the floating gate via the second insulating film, the adjacent semiconductor prisms are exposed to each other. The two conductive films are connected. As a result, the word line-shaped control gates connected between the semiconductor prisms adjacent to each other can be naturally formed, so to speak, self-aligned. Therefore, it is possible to provide a method of manufacturing a nonvolatile semiconductor memory device in which both the floating gate and the control gate are formed by self-alignment by a simple manufacturing process.

The nonvolatile semiconductor memory cell formed by using the manufacturing method of the present invention is of a vertical type, and since the lower part of the prism acts as a source electrode and the upper part acts as a drain electrode, the region occupied as a bit line contact is formed. , It can overlap with the channel region of the memory cell in a plane. Therefore, one more than a NAND memory cell
A memory cell having a small occupied area per bit can be provided.

Further, when the second means provided by the present invention is used, in the memory cell layer formed by the steps (a) to (d), the lower portion of the semiconductor prism belonging to the memory cell layer is the source. The electrode and the upper part act as a drain electrode. Therefore, each layer can be formed continuously, and a vertical NAND memory cell can be realized. This makes it possible to realize a higher density memory cell.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. First, a first embodiment will be described with reference to FIGS. 1 to 5. FIG. 5 is a cross-sectional view of a memory cell used in the nonvolatile semiconductor memory device of the present invention and its equivalent circuit diagram. As shown in FIG. 5A, this memory cell includes an N-type diffusion layer region 103 formed on the surface of a P-type semiconductor substrate 101, an element isolation insulating film 105, and a semiconductor substrate 101 through this opening. Connected to the N-type layer 109 and the P-type layer 1
Semiconductor prism 107 in which 11 and N-type layer 113 are laminated
And a gate insulating film 115, a polysilicon film 117, an inter-gate insulating film 119, and a polysilicon film 121 which are sequentially stacked on the side wall of the semiconductor prism 107. The polysilicon film 117 is independent for each semiconductor prism 107, but the polysilicon film 121 is connected for each adjacent semiconductor prism (not connected between adjacent semiconductor prisms in the direction shown in FIG. 5). However, it is connected between the semiconductor prisms in the direction perpendicular to the paper surface (not shown)). Furthermore, this memory cell is composed of an interlayer insulating film 123 for planarization, which fills the space between semiconductor prisms, and a metal wiring 125.

FIG. 5B shows an equivalent circuit of the memory cell shown in FIG. A plurality of floating gate Ms connected in parallel between the bit line BL and the common source line SL
It consists of an OS transistor Q1. The bit line BL is the metal wiring 125, and the common source line SL is the N-type diffusion layer region 103.
The floating gate of the MOS transistor Q1 is the polysilicon film 117, and the control gate is the polysilicon film 12
Equivalent to 1. Further, the N-type layer 109 serves as a source electrode,
The P-type layer 111 corresponds to the channel region, and the N-type layer 113 corresponds to the drain electrode.

Next, the manufacturing process of the first embodiment of the present invention will be described with reference to FIGS. An N type diffusion layer region 103 having a depth of about 1 μm is formed on the surface of the semiconductor substrate 101 made of P type single crystal silicon by ion implantation. The surface of the semiconductor substrate 101 is thermally oxidized to about 0.5.
An element isolation insulating film 105 having a thickness of μm is formed by thermal oxidation. A predetermined region of the element isolation insulating film 105 is
It is selectively removed by a method such as reactive ion etching using a square mask having a minimum processing line width of one side. When the minimum processing line width is 0.5 μm, 0.5 μm ×
A plurality of 0.5 μm openings are formed. The openings are formed in a matrix, and are arranged at intervals of twice the minimum processing line width in the column direction and at intervals of the same width as the minimum processing line width in the row direction. A semiconductor layer is formed by using the semiconductor substrate 101 exposed by the opening as a seed crystal and using a single crystal growth technique (lateral epitaxy method). Impurities are mixed in during this single crystal growth, and the N-type layer 1 having a thickness of 0.5 μm is formed in order from the lower layer.
09, 0.8 μm thick P-type layer 111 and 0.8 μm
The semiconductor layers are sequentially formed so as to become the N-type layer 113 having the film thickness of. Here, if necessary, the crystallinity may be improved by using a laser annealing method, an electron annealing method or the like. As described above, since the P-type layer 111 is used as the channel region of the transistor, it is necessary to sufficiently control the impurity concentration. The optimum P-type impurity concentration is 5 × 10 ¹⁶ c
It is about m ^-3 . Subsequently, the single-crystal-grown silicon stack is processed into a square shape by reactive ion etching or the like so as to have a flat area of 0.7 μm × 0.7 μm,
A semiconductor prism 107 is formed. (See FIG. 1, where (a) is a plan view and (b) is a cross-sectional view of the AA ′ region.) Then, on the side surface of the semiconductor prism 107, a gate insulating film having a thickness of about 10 nm is formed. The first insulating film 115 is formed by thermal oxidation. N on the entire surface with a high concentration of 0.4 μm
A polysilicon film doped with type impurities is formed, and is etched back using a reactive ion etching method to form a polysilicon film 11 only on the side wall of the semiconductor prism 107.
7 is left. Here, the etching is controlled so that the side portion of the P-type layer 111 is completely covered with the polysilicon film 117. Then, a second insulating film 119 having a thickness of about 10 nm to be an inter-gate insulating film is formed on the side surface of the polysilicon film 117 by thermal oxidation. Here, the second insulating film 119 is not limited to the thermal oxide film and may be a composite film including an oxide film, a nitride film, and an oxide film. (See FIG. 2, where (a) is a plan view and (b) is a cross-sectional view taken along the line AA ′.)
Then, a polysilicon film having a high concentration of 0.4 μm and doped with N-type impurities is formed on the entire surface, and is etched back by using a reactive ion etching method to adjoin the side wall of the semiconductor prism 107 and the adjacent side. The polysilicon film 121 is left in the region between the semiconductor prisms. It is also possible to use a silicide film, a polycide film, a refractory metal film, or the like as the polysilicon film. Here, since the distance between the semiconductor prisms 107-1 and 107-2 adjacent to each other in the column direction is the minimum processing line width, the polysilicon films 121 are connected to each other, but the semiconductor prisms 107-1 adjacent to each other in the row direction. 1
Since the interval between 07-3 is twice the minimum processing line width, the polysilicon films 121 are not connected to each other. (See FIG. 3, where (a) is a plan view and (b) is a cross-sectional view of the area AA ′.) Then, after forming an oxide film to a thickness of 2.5 μm on the entire surface. Etch back is performed on the entire surface using an ammonium fluoride solution or the like to expose the upper layer portion of the semiconductor prisms 107 and the region between the semiconductor prisms is filled with an oxide film 123. (See FIG. 4) Subsequently, aluminum is deposited on the entire surface by a sputtering method or the like, and this is patterned into a bit line shape to form a metal wiring 125. The metal wiring may be formed of an alloy of aluminum / silicon / copper or a multilayer film using a barrier metal such as copper, titanium / titanium nitride. (See FIG. 5) As described above, according to the first embodiment, the polysilicon film 117 formed on the side wall of the semiconductor prism 107, that is, the first conductive film surrounds the floating gate as an outside. The formed polysilicon film 121, that is, the second conductive film functions as a control gate. Since the floating gate is formed on the side wall of the semiconductor prism, the step of cutting off the floating gate for each cell by mask alignment is not necessary, and can be so-called self-aligned. Furthermore, since the gap between the semiconductor prisms is narrowed due to the film thickness of the floating gate, when the polysilicon 121 is formed on the sidewall of the floating gate via the second insulating film 119, these semiconductors are connected between adjacent semiconductor prisms. To be done. As a result, the word line-shaped control gates connected between the semiconductor prisms adjacent to each other can be naturally formed, so to speak, self-aligned. Therefore, the floating gate,
Both control gates can be self-aligned.

The nonvolatile semiconductor memory cell of this embodiment is of a vertical type, and since the lower part of the prism acts as the source electrode and the upper part acts as the drain electrode, the region occupied by the bit line contact is planarly stored in the memory. It can overlap the channel region of the cell. As a result, 1 bit can be realized with an ideal area of 6F ² . Therefore,
A memory cell having a smaller occupied area per bit than a NAND type memory cell can be formed.

Further, the memory cell formed in the first embodiment has a NOR type connection, and reading is generally faster than that of the NAND type. Furthermore, since the transistor has a surround gate shape (a shape in which a semiconductor prism is covered by a control gate), it can be reliably turned off when not selected, and can be reliably turned on if it is an erased memory cell when selected. (The conductance is larger than that of a general planar type). Therefore, it is more advantageous for speeding up.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 6 is a cross-sectional view of a memory cell used in the nonvolatile semiconductor memory device of the present invention and its equivalent circuit diagram. As shown in FIG. 5A, this memory cell has 10
Since the memory cell layers 131 ... 140 each have the same shape as the memory cell structure described in the first embodiment, the corresponding elements are designated by the same reference numerals. There is. That is, a P-type semiconductor substrate 101,
A first memory cell layer 131 and an upper memory cell layer are formed on the N-type diffusion layer region 103 and the isolation insulating film 105, and each memory cell layer is an N-type layer 109 and a P-type layer 1.
Semiconductor prism 107 in which 11 and N-type layer 113 are laminated
And a gate insulating film 115, a polysilicon film 117, an inter-gate insulating film 119, and a polysilicon film 121 which are sequentially stacked on the side wall of the semiconductor prism 107. The polysilicon film 117 is independent for each semiconductor prism 107, but the polysilicon film 121 is connected for each adjacent semiconductor prism (not connected between adjacent semiconductor prisms in the direction shown in FIG. 5). However, it is connected between the semiconductor prisms in the direction perpendicular to the paper surface (not shown)). Further, in this memory cell layer, an interlayer insulating film 123 for flattening, which is embedded between semiconductor prisms, is formed, and a metal wiring 125 is formed in the uppermost layer.

FIG. 6B shows an equivalent circuit of the memory cell shown in FIG. M with floating gate connected in series between bit line BL and common source line SL
It consists of an OS transistor Q1 ... Q10. Bit line BL
Corresponds to the metal wiring 125, the common source line SL corresponds to the N type diffusion layer region 103, the floating gate of the MOS transistor Q1 corresponds to the polysilicon film 117, and the control gate corresponds to the polysilicon film 121. Further, the N-type layer 109 is a source electrode, the P-type layer 111 is a channel region, and the N-type layer 113 is
Correspond to drain electrodes, respectively. The eight transistors of the MOS transistors Q2 ... Q9 act as memory cell transistors, the MOS transistor Q1 acts as a source side selection transistor, and the MOS transistor Q10 acts as a drain side selection transistor. When n memory cell layers are stacked in this manner, an n-2 bit NAND type memory cell is realized.

As described above, by using the second means provided by the present invention, among the memory cell layers formed by each step, the lower part of the semiconductor prism belonging to the memory cell layer is the source electrode and the upper part is the drain electrode. Acts as. Therefore, each layer can be formed continuously, and a vertical NAND memory cell can be realized.
This makes it possible to realize a higher density memory cell.

Further, like the first embodiment, both the floating gate and the control gate can be formed by self-alignment by a simple manufacturing process. Further, the region occupied as the bit line contact can be planarly overlapped with the channel region of the memory cell.
Therefore, a memory cell having an extremely small occupied area per bit can be formed.

Further, since the transistor has a surround gate shape (a shape in which a semiconductor prism is covered by a control gate), it is surely turned off when not selected, and surely turned on if it is an erased memory cell when selected. It is possible (the conductance is larger than that of a general planar type). This is highly desirable for NAND memory cells where the series conductance between the bit line and the common source line tends to increase. Therefore, it is also very advantageous for speeding up.

[0021]

As described above, according to the present invention, a method for manufacturing a non-volatile semiconductor memory device which realizes a high density memory cell can be realized by a simple manufacturing process. As an additional effect, it is possible to provide a non-volatile semiconductor memory device capable of high speed erasing and high speed reading operations. This effect is NAN
It is particularly important when used in a D-type memory cell.

[Brief description of drawings]

FIG. 1 is a plan view and a cross-sectional view showing a manufacturing process of a nonvolatile semiconductor memory cell according to a first embodiment of the present invention.

2A and 2B are a plan view and a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory cell according to the first embodiment of the present invention.

FIG. 3 is a plan view and a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory cell according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory cell according to the first embodiment of the present invention.

FIG. 5 is a sectional view of a nonvolatile semiconductor memory cell according to a first embodiment of the present invention and its equivalent circuit.

FIG. 6 is a cross-sectional view of a nonvolatile semiconductor memory cell according to a second embodiment of the present invention and its equivalent circuit.

[Explanation of symbols]

 101 semiconductor substrate 103 N-type diffusion layer 105 element isolation insulating film 107 semiconductor prism 109 N-type layer 111 P-type layer 113 N-type layer 115 first insulating film 117 polysilicon film 119 second insulating film 121 polysilicon film 123 Flattening interlayer insulating film 125 Metal wiring BL Bit line SL Common source line Q MOS transistor

Claims (2)

[Claims] 1. A plurality of semiconductor prisms adjacent to each other are formed on a semiconductor region of a first conductivity type of a semiconductor substrate, comprising a conductive layer of a first conductivity type, a second conductivity type, and a first conductivity type stacked in this order. A step of forming independent first conductive films on the sidewalls of the conductive layer regions of the second conductivity type of the plurality of semiconductor prisms with a first insulating film interposed therebetween; Forming a second conductive film on a sidewall of the film through a second insulating film and connecting the second conductive film between a plurality of adjacent semiconductor prisms; and insulating for planarization between the semiconductor prisms. A method of manufacturing a nonvolatile semiconductor memory device, comprising: a step of burying a film; and a step of forming a wiring layer connected to the first conductive type conductive layer above the semiconductor prism. 2. A step of forming an element isolation insulating film on a semiconductor region of the first conductivity type of a semiconductor substrate and forming openings adjacent to each other and reaching the semiconductor region, and (a) directly connecting to the semiconductor region. Alternatively, a step of forming a plurality of semiconductor prisms adjacent to each other, which are composed of conductive layers laminated in the order of a first conductivity type, a second conductivity type, and a first conductivity type that are indirectly connected, and (b) a plurality of the semiconductor prisms. Forming independent first conductive films on the sidewalls of the second conductive type conductive layer region via a first insulating film, and (c) forming a plurality of first conductive films on the sidewalls of the plurality of first conductive films. Forming a second conductive film via the second insulating film and connecting the second conductive film between a plurality of adjacent semiconductor prisms; and (d) forming a planarizing insulating film between the semiconductor prisms. And a step of embedding, further comprising (a), (b), (c) and A step of forming a wiring layer connected to the conductive layer of the first conductivity type of the semiconductor prism, which is the uppermost layer, after repeating step (d) a plurality of times in sequence. Device manufacturing method.