JPH07235255A - Electron emission element and its manufacture, and electron source using that electron emission element, and image formation device - Google Patents

Electron emission element and its manufacture, and electron source using that electron emission element, and image formation device

Info

Publication number
JPH07235255A
JPH07235255A JP14167094A JP14167094A JPH07235255A JP H07235255 A JPH07235255 A JP H07235255A JP 14167094 A JP14167094 A JP 14167094A JP 14167094 A JP14167094 A JP 14167094A JP H07235255 A JPH07235255 A JP H07235255A
Authority
JP
Japan
Prior art keywords
electron
emitting device
emitting
voltage
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14167094A
Other languages
Japanese (ja)
Other versions
JP3416266B2 (en
Inventor
Masato Yamanobe
正人 山野辺
Ichiro Nomura
一郎 野村
Hidetoshi Suzuki
英俊 鱸
Yoshikazu Sakano
嘉和 坂野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP14167094A priority Critical patent/JP3416266B2/en
Publication of JPH07235255A publication Critical patent/JPH07235255A/en
Application granted granted Critical
Publication of JP3416266B2 publication Critical patent/JP3416266B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J31/00Cathode ray tubes; Electron beam tubes
    • H01J31/08Cathode ray tubes; Electron beam tubes having a screen on or from which an image or pattern is formed, picked up, converted, or stored
    • H01J31/10Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes
    • H01J31/12Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes with luminescent screen
    • H01J31/123Flat display tubes
    • H01J31/125Flat display tubes provided with control means permitting the electron beam to reach selected parts of the screen, e.g. digital selection
    • H01J31/127Flat display tubes provided with control means permitting the electron beam to reach selected parts of the screen, e.g. digital selection using large area or array sources, i.e. essentially a source for each pixel group
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2201/00Electrodes common to discharge tubes
    • H01J2201/30Cold cathodes
    • H01J2201/316Cold cathodes having an electric field parallel to the surface thereof, e.g. thin film cathodes
    • H01J2201/3165Surface conduction emission type cathodes

Landscapes

  • Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)
  • Cold Cathode And The Manufacture (AREA)
  • Electrodes For Cathode-Ray Tubes (AREA)

Abstract

PURPOSE:To make possible stable control, and lessen an element current as far as possible, and besides, enlarge an emission element as far as possible so as to improve efficiency by having a deposit, which has carbon for its main ingredient, at a high- resistance part. CONSTITUTION:The material constituting a film (conductive film) 4 including an electron emission part 3 is a metal such as Pd, Ru, etc., an oxide such as PdO, etc., a boride such a HfB2, etc., a carbide such as TiC, etc., a nitride such as TiN, etc., a semiconductor such as Si, etc., carbon, or the like, and it consists of fine particles. Moreover, the part 3 is made at one part of a film 4. For example, it is a high- resistance part such as a crack or the like, and has many pieces of conductive fine particles with specified diameters. Moreover, carbon or a carbon compound (graphite, amorphous carbon) is deposited on one part of the part 3, further on the film 4 in the vicinity of the section 3. Hereby, an electron emission element can be made, in which the control of the electron emission property, which was unclear in vacuum in the past, becomes possible and also the property becomes more staple than the initial stage of the drive of the electron emission element and besides the element current is small and the efficiency is high.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電子源およびその応用
である表示装置等の画像形成装置にかかわり、特に、新
規な構成の表面伝導型電子放出素子、それを用いた電子
源および、その応用である表示装置等の画像形成装置に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electron source and an image forming apparatus such as a display device, which is an application thereof, and particularly to a surface conduction electron-emitting device having a novel structure, an electron source using the same, and The present invention relates to an applied image forming apparatus such as a display device.

【0002】[0002]

【従来の技術】従来、電子放出素子として熱電子源と冷
陰極電子源の2種類が知られている。冷陰極電子には電
子放出型(以下FE型と略す)、金属/絶縁層/金属型
(以下MIM型と略す)や表面伝導型電子放出素子等が
ある。
2. Description of the Related Art Conventionally, two types of electron emitters, a thermoelectron source and a cold cathode electron source, are known. The cold cathode electrons include an electron emission type (hereinafter abbreviated as FE type), a metal / insulating layer / metal type (hereinafter abbreviated as MIM type), a surface conduction type electron emission element, and the like.

【0003】FE型の例としてはW.P.Dyke&
W.W.Dolan、“Fieldemissio
n”、Advance in Electron Ph
ysics、8、89(1956)あるいはC.A.S
pindt,“PHYSICALProperties
of thin−filmfield emissi
on cathodes with molybden
ium cones”,J.Appl.Phys.,4
7,5248(1976)等が知られている。
As an example of the FE type, W. P. Dyke &
W. W. Dolan, "Fielddemissio
n ”, Advance in Electron Ph
ysics, 8, 89 (1956) or C.I. A. S
pindt, “PHYSICAL Properties”
of thin-filmfield emissi
on cathodes with mollybden
ium cones ”, J. Appl. Phys., 4
7, 5248 (1976) and the like are known.

【0004】MIM型の例としてはC.A.Mead、
“The tunnel−emission ampl
ifier、J.Appl.Phys.,32,646
(1961)等が知られている。
An example of the MIM type is C.I. A. Mead,
"The tunnel-emission ampl
ifier, J.M. Appl. Phys. , 32,646
(1961) and the like are known.

【0005】表面伝導型電子放出素子の例としては、
M.I.Elinson、RadioEng.Elec
tron Pys.、10、(1965)等がある。
As an example of the surface conduction electron-emitting device,
M. I. Elinson, Radio Eng. Elec
tron Pys. 10, (1965) and so on.

【0006】表面伝導型電子放出素子は基板上に形成さ
れた小面積の薄膜に、膜面に並行に電流を流すことによ
り、電子放出が生ずる現象を利用するものである。この
表面伝導型電子放出素子としては、前記エリンソン等に
よるSnO2 薄膜を用いたもの、Au薄膜によるもの
[G.Dittmer:“Thin Solid Fi
lms”、9、317(1972)]、In23 /S
nO2 薄膜によるもの[M.Hartwe11 and
C.G.Fonstad:“IEEE Trans.
ED Conf.”、519(1975)]、カーボン
薄膜によるもの[荒木久他:真空、第26巻、第1号、
22頁(1983)]等が報告されている。
The surface conduction electron-emitting device utilizes a phenomenon in which electron emission occurs by causing a current to flow in parallel to a film surface of a thin film having a small area formed on a substrate. As the surface conduction electron-emitting device, one using the SnO 2 thin film by Erinson et al., One using the Au thin film [G. Dittmer: "Thin Solid Fi
lms ”, 9, 317 (1972)], In 2 O 3 / S.
nO 2 thin film [M. Hartwe11 and
C. G. Fonstad: “IEEE Trans.
ED Conf. , 519 (1975)], by a carbon thin film [Hisashi Araki et al .: Vacuum, Vol. 26, No. 1,
22 (1983)] and the like are reported.

【0007】これらの表面伝導型電子放出素子の典型的
な素子構成として前述のM.ハートウェルの素子構成を
図18に示す。同図において1は絶縁性基板である。2
は電子放出部形成用薄膜で、H型形状のパターンに、ス
パッタで形成された金属酸化物薄膜等からなり、後述の
フォーミングと呼ばれる通電処理により電子放出部3が
形成される。4は電子放出部を含む薄膜と呼ぶことにす
る。尚、図中のL1は、0.5〜1mm、Wは、0.1
mmで設定されている。
As a typical element structure of these surface conduction electron-emitting devices, the above-mentioned M. The Hartwell device configuration is shown in FIG. In the figure, 1 is an insulating substrate. Two
Is a thin film for forming an electron emitting portion, which is composed of a metal oxide thin film or the like formed by sputtering on an H-shaped pattern, and the electron emitting portion 3 is formed by an energization process called forming described later. 4 will be referred to as a thin film including an electron emitting portion. In the figure, L1 is 0.5 to 1 mm, and W is 0.1.
It is set in mm.

【0008】従来、これらの表面伝導型電子放出素子に
おいては、電子放出を行う前に電子放出部形成用薄膜2
を予めフォーミングと呼ばれる通電処理によって電子放
出部3を形成するのが一般的であった。即ち、フォーミ
ングとは前記電子放出部形成用薄膜2の両端に直流電圧
あるいは非常にゆっくりとした昇電圧例えば1V/分程
度を印加通過し、電子放出形成用薄膜を局所的に破壊、
変形もしくは変質せしめ、電気的に高抵抗な状態にした
電子放出部3を形成することである。尚、電子放出部3
は電子放出部形成用薄膜2の一部に亀裂が発生しその亀
裂付近から電子放出が行われる。以下フォーミングによ
り形成した電子放出部を含む電子放出部形成用薄膜2を
電子放出部を含む薄膜4と呼ぶ。前記フォーミング処理
をした表面伝導型電子放出素子は、上述電子放出部を含
む薄膜4に電圧を印加し、素子に電流を流すことによ
り、上述電子放出部3より電子を放出せしめるものであ
る。
Conventionally, in these surface conduction electron-emitting devices, the electron-emitting portion forming thin film 2 is formed before electron emission.
It was general that the electron emitting portion 3 was formed in advance by an energization process called forming. That is, the forming means that a direct current voltage or a very slow rising voltage, for example, about 1 V / min is applied and passed across the electron emission part forming thin film 2 to locally destroy the electron emission forming thin film.
This is to form the electron emitting portion 3 which is deformed or altered to have a high electrical resistance. The electron emission unit 3
A crack is generated in a part of the electron emission portion forming thin film 2, and electrons are emitted from the vicinity of the crack. Hereinafter, the electron emitting portion forming thin film 2 including the electron emitting portion formed by forming will be referred to as a thin film 4 including the electron emitting portion. The surface-conduction electron-emitting device that has undergone the forming process is one in which electrons are emitted from the electron-emitting unit 3 by applying a voltage to the thin film 4 including the electron-emitting unit and passing a current through the device.

【0009】しかしながら、これら従来の表面伝導型電
子放出素子においては、実用化にあたっては、様々の問
題があったが、本出願人等は、後述する様な様々な改善
を鋭意検討し、実用化上の様々な問題点を解決してき
た。
However, although these conventional surface conduction electron-emitting devices have various problems in practical use, the applicants of the present invention diligently studied various improvements as described later and put them into practical use. We have solved various problems above.

【0010】上述の表面伝導型電子放出素子は、構造が
単純で製造も容易であることから、大面積にわたり多数
素子を配列形成できる利点がある。そこで、この特徴を
生かせるようないろいろな応用が研究されている。例え
ば、荷電ビーム源、表示装置等があげられる。
Since the surface conduction electron-emitting device described above has a simple structure and is easy to manufacture, it has an advantage that many devices can be arrayed and formed over a large area. Therefore, various applications that can make full use of this feature are being studied. Examples thereof include a charged beam source and a display device.

【0011】多数の表面伝導型電子放出素子を配列形成
した例としては、並列に表面伝導型電子放出素子を配列
し、個々の素子の両端を配線にてそれぞれ結線した行を
多数行配列した電子源があげられる。(例えば、特開昭
64−31332号公報,特開平1−283749号公
報,特開平1−257552号公報)また、特に表示装
置等の画像形成装置においては、近年、液晶を用いた平
板型表示装置が、CRTに替わって、普及してきたが、
自発光型でないため、バックライト等を持たなければな
らない等の問題点があり、自発光型の表示装置の開発
が、望まれてきた。表面伝導型電子放出素子を多数配置
した電子源と電子源より放出された電子によって、可視
光を発光せしめる蛍光体とを組み合わせた表示装置であ
る画像形成装置は、大画面の装置でも比較的容易に製造
でき、かつ表示品位の優れた自発光型表示装置である
(例えば、USP5066883号)。
As an example in which a large number of surface-conduction type electron-emitting devices are formed in an array, the surface-conduction type electron-emitting devices are arranged in parallel, and a large number of rows in which both ends of each element are connected by wiring are arranged. The source is raised. (For example, JP-A-64-31332, JP-A-1-283749, and JP-A-1-257552) In recent years, particularly in image forming apparatuses such as display devices, flat panel display using liquid crystal has been recently used. The device has become popular instead of the CRT,
Since it is not a self-luminous type, there is a problem that it must have a backlight or the like, and development of a self-luminous display device has been desired. An image forming apparatus, which is a display device in which a large number of surface conduction electron-emitting devices are arranged and a phosphor that emits visible light by the electrons emitted from the electron source, is relatively easy to use in an image forming apparatus. It is a self-luminous display device that can be manufactured according to the present invention and has excellent display quality (for example, USP 5066883).

【0012】尚、従来、多数の表面伝導型電子放出素子
より構成された電子源より、電子放出をし、蛍光体の発
光をさせる素子の選択は、上述の多数の表面伝導型電子
放出素子を並列に配置し結線した配線(行方向配線と呼
ぶ)、行配線と直交する方向に(列方向と呼ぶ)、該電
子源と蛍光対間の空間に設置された制御電極(グリッド
と呼ぶ)と列方向配線への適当な駆動信号によるもので
ある(例えば、特開平1−283749号公報等)。
Conventionally, the selection of the element which emits electrons from the electron source composed of a large number of surface-conduction type electron-emitting devices and causes the phosphor to emit light is performed by the above-mentioned large number of surface-conduction type electron-emitting devices. Wirings arranged and connected in parallel (referred to as row-direction wirings), control electrodes (referred to as grids) installed in a space between the electron source and the fluorescent pair in a direction orthogonal to the row wirings (referred to as column direction). This is due to an appropriate drive signal to the column direction wiring (for example, Japanese Patent Laid-Open No. 1-283749).

【0013】[0013]

【発明が解決しようとしている課題】しかしながら、前
記電子源、画像形成装置等に用いられる表面伝導型電子
放出素子の真空中の挙動は、殆ど判っておらず、安定で
制御された電子放出特性、及びその効率の向上が、望ま
れてきた。
However, the behavior of the surface conduction electron-emitting device used in the electron source, the image forming apparatus and the like in a vacuum is hardly known, and stable and controlled electron emission characteristics, And the improvement of the efficiency has been desired.

【0014】ここで効率とは、表面伝導型電子放出素子
の一対の対向する素子電極に電圧を印加したとき、流れ
る電流(以下、素子電流Ifと呼ぶ)に対する真空中に
放出される電流(以下、放出電流Ieと呼ぶ)との電流
比をさす。
The term "efficiency" as used herein means the current (hereinafter referred to as "device current If") emitted in a vacuum when a voltage is applied to a pair of opposed device electrodes of a surface conduction electron-emitting device (hereinafter referred to as "device current If"). , Emission current Ie).

【0015】つまり、素子電流はできるだけ小さく、放
出電流はできるだけ大きいことが望ましい。
That is, it is desirable that the device current be as small as possible and the emission current be as large as possible.

【0016】安定で制御された電子放出特性と効率の向
上がなされれば、例えば蛍光体を画像形成部材とする画
像形成装置においては、低電流で明るい高品位な画像形
成装置、例えば、フラットテレビが実現される。また、
低電流化にともない、画像形成装置を構成する駆動回路
等も安価になることも期待できる。本発明は、上記問題
を鑑み、安定で制御され、素子電流はでき得るだけ小さ
く且つ放出電流はでき得るだけ大きい、効率の高い電子
放出素子の新規な構成とその製造方法及びそれを用いた
電子源及び画像形成装置を提供するものである。
If stable and controlled electron emission characteristics and efficiency are improved, in an image forming apparatus using, for example, a phosphor as an image forming member, a bright and high quality image forming apparatus with a low current, such as a flat television. Is realized. Also,
It can be expected that the drive circuit and the like that form the image forming apparatus will become cheaper as the current becomes lower. In view of the above problems, the present invention provides a novel structure of a highly efficient electron-emitting device that is stable and controlled, a device current is as small as possible and an emission current is as large as possible, a manufacturing method thereof, and an electron using the same. A source and an image forming apparatus are provided.

【0017】[0017]

【課題を解決するための手段】上記課題を解決する、本
発明の電子放出素子は、対向する電極間に、高抵抗部を
含む導電性膜を有する電子放出素子において、該高抵抗
部に、炭素を主成分とする堆積物を有することを特徴と
する電子放出素子であり、好ましくは前記炭素を主成分
とする堆積物は、前記高抵抗部の一部から前記導電性膜
上に存在する電子放出素子であり、更に好ましくは、前
記炭素を主成分とする堆積物は、前記高抵抗部の一部か
ら前記電極のうちの高電位電極側の導電性膜上に偏在す
る電子放出素子である。
In order to solve the above-mentioned problems, an electron-emitting device of the present invention is an electron-emitting device having a conductive film including a high resistance portion between opposing electrodes, wherein the high resistance portion is An electron-emitting device having a deposit containing carbon as a main component, preferably the deposit containing carbon as a main component is present on a part of the high resistance portion on the conductive film. An electron-emitting device, more preferably, the deposit containing carbon as a main component is an electron-emitting device unevenly distributed from a part of the high resistance portion on the conductive film on the high potential electrode side of the electrodes. is there.

【0018】また上記電子放出素子の製造方法は、対向
する電極間に、電子放出部を含む導電性膜を有する電子
放出素子の製造方法において、素子の活性化工程を有す
ることを特徴とする電子放出素子の製造方法であり、こ
こで言う前記活性化工程は、前記素子に炭素を主成分と
する堆積物を堆積させる工程を有するものであり、好ま
しくは、以上の活性化工程は、真空中にて、電極間に設
けられた導電性膜に電圧を印加する工程を有するもので
ある。
Further, the above-described method for manufacturing an electron-emitting device is the method for manufacturing an electron-emitting device having a conductive film including an electron-emitting portion between opposing electrodes, characterized in that it has an element activation step. A method for manufacturing an emitting device, wherein the activation step referred to here has a step of depositing a deposit containing carbon as a main component on the element, and preferably, the above activation step is performed in a vacuum. Then, there is a step of applying a voltage to the conductive film provided between the electrodes.

【0019】また、このましくは、該電圧の印加はパル
ス状電圧の印加であり、特に好ましくは、電子放出素子
の駆動電圧であることが良い。
Further, preferably, the voltage application is a pulsed voltage application, and particularly preferably a drive voltage for the electron-emitting device.

【0020】更に本発明は、以上の電子放出素子を有
し、入力信号に応じて電子を放出する電子源であり、好
ましくは、上記の電子放出素子を、基体上に、複数個配
置したことを特徴とした電子源であって、基体に、複数
の電子放出素子を複数個並列に配置し、個々の素子の両
端を配線に接続した電子放出素子の行を複数もち、更
に、変調手段を有している配置形態、あるいは、基体
に、互いに、電気的に、絶縁されたm本のX方向配線と
n本のY方向配線とに、該電子放出素子の一対の素子電
極とを接続した電子放出素子を複数個配列した配置形態
を有する電子源である。
Furthermore, the present invention is an electron source which has the above-mentioned electron-emitting device and emits electrons in response to an input signal. Preferably, a plurality of the above-mentioned electron-emitting devices are arranged on a substrate. And a plurality of rows of electron-emitting devices in which a plurality of electron-emitting devices are arranged in parallel on a substrate and both ends of each device are connected to a wiring, and a modulation means is further provided. A pair of device electrodes of the electron-emitting device are connected to m arrangements of X-direction wirings and n wirings of Y-directions electrically insulated from each other in the arrangement form or the substrate. This is an electron source having an arrangement form in which a plurality of electron-emitting devices are arranged.

【0021】更に本発明は、画像形成装置であって、入
力信号にもとづいて、画像を形成する画像形成装置にお
いて、少なくとも、画像形成部材と前記本発明の電子源
とを有するこを特徴とする画像形成装置である。
Further, the present invention is an image forming apparatus which forms an image based on an input signal, and is characterized by having at least an image forming member and the electron source of the present invention. The image forming apparatus.

【0022】以下に、本発明の好ましい実施態様につい
て述べる。
The preferred embodiments of the present invention will be described below.

【0023】まず、本発明に係わる表面伝導型電子放出
素子の基本的な構成について説明する。
First, the basic structure of the surface conduction electron-emitting device according to the present invention will be described.

【0024】図1の(a)、(b)は、それぞれ、本発
明にかかわる基本的な平面型の表面伝導型電子放出素子
の構成を示す平面図及び断面図である。図1を用いて、
本発明に係わる素子の基本的な構成を説明する。
1 (a) and 1 (b) are a plan view and a cross-sectional view, respectively, showing the structure of a basic planar type surface conduction electron-emitting device according to the present invention. Using Figure 1,
The basic configuration of the device according to the present invention will be described.

【0025】図1において1は基板、5と6は素子電
極、4は電子放出部を含む薄膜(導電性膜)、3は電子
放出部である。
In FIG. 1, 1 is a substrate, 5 and 6 are device electrodes, 4 is a thin film (conductive film) including an electron emitting portion, and 3 is an electron emitting portion.

【0026】基板1としては、石英ガラス、Na等の不
純物含有量を減少したガラス、青板ガラス、青板ガラス
にスパッタ法等により形成したSiO2 を積層したガラ
ス基板等及びアルミナ等のセラミックス等が挙げられ
る。
Examples of the substrate 1 include quartz glass, glass having a reduced content of impurities such as Na, soda lime glass, a soda lime glass substrate laminated with SiO 2 formed by a sputtering method, and ceramics such as alumina. To be

【0027】対向する素子電極5、6の材料としては導
電性を有するものであればどのようなものであっても構
わないが、例えばNi、Cr、Au、Mo、W、Pt、
Ti、Al、Cu、Pd等の金属或は合金及びPd、A
g、Au、RuO2 、Pd−Ag等の金属或は金属酸化
物とガラス等から構成される印刷導体、In23 −S
nO2 等の透明導電体及びポリシリコン等の半導体材料
等が挙げられる。
Any material may be used as the material of the opposing device electrodes 5 and 6 as long as it has conductivity. For example, Ni, Cr, Au, Mo, W, Pt,
Metals or alloys such as Ti, Al, Cu, Pd and Pd, A
g, Au, printed conductors composed of RuO 2, metal or metal oxide such as Pd-Ag and glass, etc., In 2 O 3 -S
Examples include transparent conductors such as nO 2 and semiconductor materials such as polysilicon.

【0028】素子電極間隔L1,素子電極長さW1,導
電性膜4の形状等は、この素子の応用形態等によって適
宜設計され、例えば、後述する表示装置で、テレビジョ
ン等では、画面サイズに対応した画素サイズが設計さ
れ、とりわけ、高品位TVでは、画素サイズが小さく、
高精細さが要求される。そのため、電子放出素子のサイ
ズが、限定されたなかで、十分な輝度を得るためには、
十分な放出電流が得られるように設計される。
The element electrode interval L1, the element electrode length W1, the shape of the conductive film 4 and the like are appropriately designed according to the application form of this element. For example, in a display device described later, in a television or the like, the screen size is changed. Corresponding pixel size is designed, especially in high definition TV, the pixel size is small,
High definition is required. Therefore, in order to obtain sufficient brightness, the size of the electron-emitting device is limited.
It is designed to obtain a sufficient emission current.

【0029】素子電極間隔L1は、数百オングストロー
ムより数百マイクロメートルあり、素子電極の製法の基
本となるフォトリソグラフィー技術、即ち、露光機の性
能とエッチング方法等、及び、素子電極間に印加する電
圧と電子放出し得る電界強度等により設定されるが、好
ましくは、数マイクロメートルより数十マイクロメート
ルである。
The element electrode interval L1 is several hundreds of angstroms to several hundreds of micrometers, and the photolithography technology that is the basis of the manufacturing method of the element electrodes, that is, the performance of the exposure device and the etching method, and the application between the element electrodes are applied. The voltage is set depending on the voltage and the electric field strength capable of emitting electrons, but is preferably several micrometers to several tens of micrometers.

【0030】素子電極の長さW1、及び、素子電極5、
6の膜厚dは、電極の抵抗値、前述したX、Y配線との
結線、多数配置された電子源の配置上の問題より適宜設
計され、通常は、素子電極の長さW1は、数マイクロメ
ートルより数百マイクロメートルであり、素子電極5、
6の膜厚dは、数百オングストロームより数マイクロメ
ートルである。
The length W1 of the device electrode and the device electrode 5,
The film thickness d of 6 is appropriately designed in consideration of the resistance value of the electrode, the connection with the X and Y wirings described above, and the arrangement problem of a large number of arranged electron sources. Usually, the length W1 of the device electrode is several It is several hundreds of micrometers rather than micrometers, and the device electrode 5,
The film thickness d of 6 is several micrometers to several hundred angstroms.

【0031】基板1上に設けられた対向する素子電極5
と素子電極6間及び素子電極5、6上設置された電子放
出部を含む薄膜4は、電子放出部3を含むが、図1の
(b)に示された場合だけでなく、素子電極5、6上に
は、設置されない場合もある。即ち、絶縁性基板1上
に、電子放出部形成用薄膜2、対向する素子電極5、6
の順に積層構成した場合である。また、対向する素子電
極5と素子電極6間全てが、製法によっては、電子放出
部として機能する場合もある。この電子放出部を含む薄
膜4の膜厚は、好ましくは、数オングストロームより数
千オングストロームで特に、好ましくは10オングスト
ロームより500オングストロームあり、素子電極5、
6へのステップカバレージ、電子放出部3と素子電極
5、6間の抵抗値及び電子放出部3の導電性微粒子の粒
径、後述する通電処理条件等によって、適宜設定され
る。その抵抗値は、10の3乗より10の7乗オーム/
□のシート抵抗値を示す。
Opposing element electrodes 5 provided on the substrate 1
The thin film 4 including the electron emitting portion provided between the device electrode 6 and the device electrodes 5, 6 includes the electron emitting portion 3, but not only in the case shown in FIG. , 6 may not be installed. That is, on the insulating substrate 1, the electron emission portion forming thin film 2 and the opposing device electrodes 5 and 6 are formed.
This is the case where the layers are laminated in this order. Further, depending on the manufacturing method, the entire space between the opposing device electrodes 5 and 6 may function as an electron emitting portion. The film thickness of the thin film 4 including the electron emitting portion is preferably several angstroms to several thousand angstroms, particularly preferably 10 angstroms to 500 angstroms.
It is appropriately set depending on the step coverage to 6, the resistance value between the electron emitting portion 3 and the device electrodes 5 and 6, the particle size of the conductive fine particles in the electron emitting portion 3, the energization processing condition described later, and the like. The resistance value is 10 7 to 10 7 ohm /
The sheet resistance value of □ is shown.

【0032】電子放出部を含む薄膜(導電性膜)4を構
成する材料の具体例を挙げるならばPd、Ru、Ag、
Au、Ti、In、Cu、Cr、Fe、Zn、Sn、T
a、W、Pb等の金属、PdO、SnO2 、In2
3 、PbO、Sb23 等の酸化物、HfB2 、ZrB
2 、LaB6 、CeB6 、YB4 、GdB4 等の硼化
物、TiC、ZrC、HfC、TaC、SiC、WC等
の炭化物、TiN、ZrN、HfN等の窒化物、Si、
Ge等の半導体、カーボン、AgMg、NiCu、P
b、Sn等であり、微粒子からなる。
Specific examples of the material forming the thin film (conductive film) 4 including the electron emitting portion are Pd, Ru, Ag,
Au, Ti, In, Cu, Cr, Fe, Zn, Sn, T
a, W, Pb and other metals, PdO, SnO 2 , In 2 O
3 , oxides such as PbO and Sb 2 O 3 , HfB 2 , ZrB
2, LaB 6, CeB 6, YB 4, GdB borides such as 4, TiC, ZrC, HfC, TaC, SiC, and WC, etc., TiN, ZrN, nitrides such as HfN, Si,
Semiconductors such as Ge, carbon, AgMg, NiCu, P
b, Sn, etc., and are composed of fine particles.

【0033】尚、ここで述べる微粒子膜とは、複数の微
粒子が集合した膜であり、その微細構造として、微粒子
が個々に分散配置した状態のみならず、微粒子が互いに
隣接、あるいは重なり合った状態(島状も含む)の膜を
さす。
The fine particle film described here is a film in which a plurality of fine particles are aggregated, and its fine structure is not only a state in which the fine particles are individually dispersed and arranged but also a state in which the fine particles are adjacent to each other or overlap each other ( (Including island-shaped) film.

【0034】微粒子の粒径は、数オングストロームより
数千オングストローム、このましくは、10オングスト
ロームより200オングストロームである。
The particle size of the fine particles is from several angstroms to several thousand angstroms, preferably from 10 angstroms to 200 angstroms.

【0035】電子放出部3は、導電性膜4の一部に形成
された、例えば、亀裂等の高抵抗部であり、更には、好
ましくは、数オングストロームより数百オングストロー
ム、特に好ましくは、10オングストロームより500
オングストロームの粒径の導電性微粒子多数個を有する
場合もあり、電子放出部を含む薄膜(導電性膜)4の膜
厚及び後述する通電処理条件等の製法に依存しており、
適宜設定される。
The electron emitting portion 3 is a high resistance portion such as a crack formed in a part of the conductive film 4, and more preferably several angstroms to several hundred angstroms, particularly preferably 10 angstroms. 500 from Angstrom
There may be a large number of conductive fine particles having a particle diameter of angstrom, and it depends on the film thickness of the thin film (conductive film) 4 including the electron emitting portion and the manufacturing method such as the energization processing condition described later.
It is set appropriately.

【0036】又、前記導電性微粒子は、電子放出部を含
む薄膜(導電性膜)4を構成する材料の元素の一部ある
いは全てと同様の物である。
The conductive fine particles are the same as some or all of the elements of the material forming the thin film (conductive film) 4 including the electron emitting portion.

【0037】又、電子放出部3の一部、更には、電子放
出部3の近傍の導電性膜4には、炭素あるいは炭素化合
物が堆積されている。
Carbon or a carbon compound is deposited on a part of the electron emitting portion 3 and further on the conductive film 4 near the electron emitting portion 3.

【0038】次に本発明に係る別な構成の表面伝導型電
子放出素子である垂直型表面導電型電子放出素子につい
て説明する。
Next, a vertical type surface conduction electron-emitting device which is a surface conduction electron emission device having another structure according to the present invention will be described.

【0039】図12は基本的な垂直型表面伝導型電子放
出素子の構成を示す模式的図面である。
FIG. 12 is a schematic view showing the structure of a basic vertical surface conduction electron-emitting device.

【0040】図12において、図1と同一の符号のもの
は、同一である。21は段さ形成部である。基板1、素
子電極5と6、電子放出部を含む薄膜4、電子放出部3
は、前述した平面型表面伝導型電子放出素子と同様の材
料で構成されたものであり、段さ形成部21は、真空蒸
着法、印刷法、スパッタ法等で形成されたSiO2等の
絶縁性材料で構成され、段さ形成部21の膜厚が、先に
述べた平面型表面伝導型電子放出素子の素子電極間隔L
に対応し、数十ナノメートルより数十マイクロメートル
であり、段さ形成部の製法、及び、素子電極間に印加す
る電圧と電子放出し得る電界強度により設定されるが、
好ましくは、数十ナノメートルより数マイクロメートル
である。電子放出部を含む薄膜4は、素子電極5、6と
段さ形成部21作成後に、形成するため、素子電極5、
6の上に積層される。なお、電子放出部3は、図12に
おいて、段差形成部21に直線状に示されているが、作
成条件、通電フォーミング条件等に依存し、形状、位置
ともこれに限るものでない。
In FIG. 12, the same symbols as those in FIG. 1 are the same. Reference numeral 21 is a step forming portion. Substrate 1, device electrodes 5 and 6, thin film 4 including electron emitting portion, electron emitting portion 3
Is made of a material similar to that of the above-mentioned planar surface conduction electron-emitting device, and the step forming portion 21 is made of an insulating material such as SiO 2 formed by a vacuum deposition method, a printing method, a sputtering method or the like. Made of a conductive material, and the film thickness of the step forming portion 21 is equal to the device electrode interval L of the planar surface conduction electron-emitting device described above.
Corresponding to tens of nanometers to tens of micrometers, and is set by the manufacturing method of the step forming portion and the voltage applied between the device electrodes and the electric field strength capable of emitting electrons.
It is preferably several tens of nanometers to several micrometers. Since the thin film 4 including the electron emitting portion is formed after the device electrodes 5 and 6 and the step forming portion 21 are formed,
6 is laminated on top. Although the electron emitting portion 3 is shown as a linear shape in the step forming portion 21 in FIG. 12, the shape and position are not limited to this, depending on the production conditions, energization forming conditions, and the like.

【0041】電子放出部3を有する電子放出素子の製造
方法としては様々な方法が考えられるが、その一例を図
2に示す。尚、図2中、2は電子放出部形成用薄膜(導
電性膜)で例えば微粒子膜が挙げられる。
Various methods are conceivable as a method of manufacturing an electron-emitting device having the electron-emitting portion 3, one example of which is shown in FIG. In FIG. 2, reference numeral 2 denotes a thin film (electroconductive film) for forming an electron emitting portion, which is, for example, a fine particle film.

【0042】以下、順をおって製造方法の説明を図1及
び図2に基づいて説明する。 1)基板1を洗剤、純水および有機溶剤により十分に洗
浄後、真空蒸着法、スパッタ法等により素子電極材料を
堆積後、フォトリソグラフィー技術により該絶縁性基板
1の面上に素子電極5、6を形成する(図2の
(a))。 2)絶縁性基板1上に設けられた素子電極5と素子電極
6との間に、素子電極5と6を形成した絶縁性基板上に
有機金属溶液を塗布して放置することにより、有機金属
薄膜を形成する。なお、有機金属溶液とは、前記Pd、
Ru、Ag、Au、Ti、In、Cu、Cr、Fe、Z
n、Sn、Ta、W、Pb等の金属を主元素とする有機
化合物の溶液である。この後、有機金属薄膜を加熱焼成
処理し、リフトオフ、エッチング等によりパターニング
し、電子放出部形成用薄膜2を形成する(図2の
(b))。尚、ここでは、有機金属溶液の塗布法により
説明したが、これに限る物でなく、真空蒸着法、スパッ
タ法、化学的気相堆積法、分散塗布法、ディッピング
法、スピンナー法等によって形成される場合もある。 3)つづいて、フォーミングと呼ばれる通電処理を素子
電極5、6間に電圧を不図示の電源によりパルス状ある
いは、昇電圧による通電処理がおこなわれると、電子放
出部形成用薄膜(導電性膜)2の部位に構造の変化した
電子放出部3が形成される(図2の(c))。この通電
処理により電子放出部形成用薄膜(導電性膜)2を局所
的に破壊、変形もしくは変質せしめ、構造の変化した部
位(高抵抗部位)を電子放出部3と呼ぶ。
Hereinafter, the manufacturing method will be described step by step with reference to FIGS. 1 and 2. 1) After thoroughly cleaning the substrate 1 with a detergent, pure water, and an organic solvent, depositing an element electrode material by a vacuum deposition method, a sputtering method, or the like, and then using a photolithography technique, an element electrode 5 on the surface of the insulating substrate 1, 6 is formed ((a) of FIG. 2). 2) The organic metal solution is applied between the element electrodes 5 and 6 provided on the insulating substrate 1 on the insulating substrate on which the element electrodes 5 and 6 are formed. Form a thin film. The organometallic solution means the Pd,
Ru, Ag, Au, Ti, In, Cu, Cr, Fe, Z
It is a solution of an organic compound containing a metal such as n, Sn, Ta, W, or Pb as a main element. After that, the organic metal thin film is heat-fired and patterned by lift-off, etching, etc. to form the electron emission portion forming thin film 2 ((b) of FIG. 2). In addition, although the description has been given here by using the coating method of the organic metal solution, the present invention is not limited to this, and it may be formed by a vacuum deposition method, a sputtering method, a chemical vapor deposition method, a dispersion coating method, a dipping method, a spinner method, or the like. There are also cases. 3) Subsequently, when an energization process called forming is performed by applying a voltage between the element electrodes 5 and 6 in a pulsed manner by a power source (not shown) or by a rising voltage, a thin film (electroconductive film) for forming an electron emission portion is formed. An electron emitting portion 3 having a changed structure is formed at the portion 2 (FIG. 2 (c)). This energization process locally destroys, deforms, or modifies the electron-emitting-portion-forming thin film (conductive film) 2, and the portion where the structure is changed (high-resistance portion) is called the electron-emitting portion 3.

【0043】フォーミング処理以降の電気的処理は、図
3に示す測定評価装置内で行う。以下に測定評価装置を
説明する。
The electrical processing after the forming processing is carried out in the measurement / evaluation apparatus shown in FIG. The measurement / evaluation apparatus will be described below.

【0044】図3は、図1で示した構成を有する素子の
電子放出特性を測定するための測定評価装置の概略構成
図である。図3において、1は基体、5及び6は素子電
極、4は電子放出部を含む薄膜、3は電子放出部を示
す。また、31は素子に素子電圧Vfを印加するための
電源、30は素子電極5、6間の電子放出部を含む薄膜
4を流れる素子電流Ifを測定するための電流計、34
は素子の電子放出部より放出される放出電流Ieを捕捉
するためのアノード電極、33はアノード電極34に電
圧を印加するための高圧電源、32は素子の電子放出部
3より放出される放出電流Ieを測定するための電流計
である。
FIG. 3 is a schematic configuration diagram of a measurement / evaluation apparatus for measuring the electron emission characteristics of the device having the configuration shown in FIG. In FIG. 3, 1 is a substrate, 5 and 6 are device electrodes, 4 is a thin film including an electron emitting portion, and 3 is an electron emitting portion. Further, 31 is a power supply for applying a device voltage Vf to the device, 30 is an ammeter for measuring a device current If flowing through the thin film 4 including the electron emitting portion between the device electrodes 5 and 6, and 34 is an ammeter.
Is an anode electrode for capturing the emission current Ie emitted from the electron emission portion of the device, 33 is a high-voltage power supply for applying a voltage to the anode electrode 34, and 32 is an emission current emitted from the electron emission portion 3 of the device It is an ammeter for measuring Ie.

【0045】電子放出素子の上記素子電流If、放出電
流Ieの測定にあたっては、素子電極5、6に電源31
と電流計30とを接続し、該電子放出素子の上方に電源
33と電流計32とを接続したアノード電極34を配置
している。また、電子放出素子及びアノード電極34は
真空装置内に設置され、その真空装置には不図示の排気
ポンプ及び真空計等の真空装置に必要な機器が具備され
ており、所望の真空下で素子の測定評価を行えるように
なっている。尚、排気ポンプは、ターボポンプ、ロータ
リーポンプからなる通常の高真空装置系あるいは、オイ
ルを使用しない、磁気浮上ターボポンプ、ドライポンプ
等の高真空装置系と更に、イオンポンプからなる超高真
空装置系からなる。 また、真空装置全体、及び電子源
基板は、不図示のヒーターにより200℃まで加熱でき
る。
When measuring the device current If and the emission current Ie of the electron-emitting device, the power supply 31 is applied to the device electrodes 5 and 6.
And an ammeter 30 are connected to each other, and an anode electrode 34 to which a power source 33 and an ammeter 32 are connected is arranged above the electron-emitting device. Further, the electron-emitting device and the anode electrode 34 are installed in a vacuum device, and the vacuum device is equipped with equipment necessary for the vacuum device such as an exhaust pump and a vacuum gauge (not shown), and the device is operated under a desired vacuum. The measurement and evaluation of can be performed. The exhaust pump is a normal high vacuum device system including a turbo pump or a rotary pump, or a high vacuum device system such as a magnetic levitation turbo pump or a dry pump that does not use oil, and an ultra high vacuum device including an ion pump. It consists of a system. Further, the entire vacuum device and the electron source substrate can be heated to 200 ° C. by a heater (not shown).

【0046】なお、アノード電極の電圧は1kV〜10
kV、アノード電極と電子放出素子との距離Hは2mm
〜8mmの範囲で測定した。
The voltage of the anode electrode is 1 kV to 10 kV.
kV, the distance H between the anode electrode and the electron-emitting device is 2 mm
It was measured in the range of ~ 8 mm.

【0047】フォーミング処理は、パルス波高値が定電
圧のパルスを印加する場合とパルス波高値を増加させな
がら、電圧パルスを印加する場合とがある。まず、パル
ス波高値が定電圧のパルスを印加の場合の電圧波形を図
4の(a)に示す。
In the forming process, there are a case of applying a pulse having a constant pulse peak value and a case of applying a voltage pulse while increasing the pulse peak value. First, FIG. 4A shows a voltage waveform when a pulse having a constant pulse peak value is applied.

【0048】図4の(a)中、T1及びT2は電圧波形
のパルス幅とパルス間隔であり、T1を1マイクロ秒〜
10ミリ秒、T2を10マイクロ秒〜100ミリ秒と
し、三角波の波高値(フォーミング時のピーク電圧)は
適宜選択し、真空雰囲気下で印加する。
In FIG. 4A, T1 and T2 are the pulse width and pulse interval of the voltage waveform, where T1 is 1 microsecond to
10 ms, T2 is 10 microseconds to 100 ms, the peak value of the triangular wave (peak voltage during forming) is appropriately selected, and application is performed in a vacuum atmosphere.

【0049】次に、パルス波高値を増加させながら、電
圧パルスを印加する場合の電圧波形を、図4の(b)に
示す。
Next, FIG. 4B shows a voltage waveform when a voltage pulse is applied while increasing the pulse crest value.

【0050】図4の(b)中、T1及びT2は電圧波形
のパルス幅とパルス間隔であり、T1を1マイクロ秒〜
10ミリ秒、T2を10マイクロ秒〜100ミリ秒と
し、三角波の波高値(フォーミング時のピーク電圧)
は、例えば0.1Vステップ程度づつ、増加させ、真空
雰囲気下で印加する。
In FIG. 4B, T1 and T2 are the pulse width and pulse interval of the voltage waveform, and T1 is 1 microsecond to
10 milliseconds, T2 is 10 microseconds to 100 milliseconds, and the peak value of the triangular wave (peak voltage during forming)
Is increased in steps of, for example, about 0.1 V and applied in a vacuum atmosphere.

【0051】尚、フォーミング処理の終了は、パルス間
隔T2中に、電子放出部形成用薄膜2を局所的に破壊、
変形しない程度の電圧例えば0.1V程度の電圧で、素
子電流を測定し、抵抗値を求め、例えば、1Mオーム以
上の抵抗を示した時、フォーミングを終了とした。この
時の電圧を、フォーミング電圧Vformと呼ぶことに
する。
The end of the forming process is to locally destroy the electron emission portion forming thin film 2 during the pulse interval T2.
The element current was measured at a voltage that did not deform, for example, a voltage of about 0.1 V, and the resistance value was obtained. When the resistance was 1 M ohm or more, the forming was terminated. The voltage at this time will be referred to as a forming voltage Vform.

【0052】以上説明した電子放出部を形成する際に、
素子の電極間に三角波パルスを印加してフォーミング処
理を行っているが、素子の電極間に印加する波形は三角
波に限定することはなく、矩形波など所望の波形を用い
ても良く、その波高値及びパルス幅、パルス間隔等につ
いても上述の値に限ることなく、電子放出部が良好に形
成される様に、電子放出素子の抵抗値等にあわせて、所
望の値を選択する。
When forming the electron emitting portion described above,
Although the triangular wave pulse is applied between the electrodes of the element to perform the forming process, the waveform applied between the electrodes of the element is not limited to the triangular wave, and a desired waveform such as a rectangular wave may be used. The high value, the pulse width, the pulse interval, and the like are not limited to the above values, and a desired value is selected according to the resistance value of the electron-emitting device so that the electron-emitting portion can be formed well.

【0053】また、このフォーミング電圧は、素子の材
料,構成等により一義的に決まるので、上記図4の
(b)に示すようなパルス波高値を増加させながら、電
圧パルスを印加する場合の方が、個々の素子に適正なフ
ォーミングのエネルギーが容易に得られ、良好な電子放
出特性が得られるので好ましい。 4)次に、フォーミングが終了した素子に活性化処理と
呼ぶ処理を施す。活性化処理とは、10のマイナス4乗
〜10のマイナス5乗torr程度の真空度で、フォー
ミング同様、パルス波高値が定電圧のパルスの印加を繰
りかえす処理のことを言い、真空中に存在する有機物質
から、炭素あるいは炭素化合物を堆積することで、素子
電流If、放出電流Ieが、著しく変化する処理であ
る。素子電流Ifと放出電流Ieを測定しながら、例え
ば、放出電流Ieが飽和した時点で、活性化処理を終了
する。素子電流If、放出電流Ieの活性化処理時間依
存例を図5に示す。
Since this forming voltage is uniquely determined by the material, structure, etc. of the element, it is better to apply a voltage pulse while increasing the pulse crest value as shown in FIG. 4 (b). However, it is preferable because proper forming energy can be easily obtained for each element and good electron emission characteristics can be obtained. 4) Next, a process called an activation process is performed on the element for which forming has been completed. The activation process is a process in which a vacuum degree of about 10 −4 to 10 −5 torr is applied, and like in forming, a pulse wave whose peak value is a constant voltage is repeatedly applied and exists in a vacuum. By depositing carbon or a carbon compound from an organic substance, the device current If and the emission current Ie are significantly changed. While measuring the device current If and the emission current Ie, for example, when the emission current Ie is saturated, the activation process ends. FIG. 5 shows an example of activation processing time dependence of the device current If and the emission current Ie.

【0054】活性化処理は、真空度、素子に印加するパ
ルス電圧等に依存して、この素子電流If、放出電流I
eの時間依存が変化し、またフォーミング処理によっ
て、変形、変質した薄膜への被膜(堆積物)の形成状態
が変化する。
The activation process depends on the degree of vacuum, the pulse voltage applied to the device, etc., and the device current If and emission current I
The time dependency of e changes, and the forming state of the film (deposit) on the deformed and altered thin film changes due to the forming process.

【0055】活性化処理電圧が、フォーミング電圧V
formに比べて、十分に高いパルスを印加し活性化処理す
る場合を高抵抗活性化処理と呼ぶこととする。一方、活
性化処理電圧が、フォーミング電圧Vformに比べて、十
分に低いパルスを印加し活性化処理する場合を低抵抗活
性化処理と呼ぶこととする。尚、後述する電圧制御型負
性抵抗を示す開始電圧VPをただしくは、ほぼ、境界と
して活性化処理が分類される。
The activation processing voltage is the forming voltage V.
The case of applying a sufficiently higher pulse than the form and performing the activation process will be referred to as a high resistance activation process. On the other hand, a case where the activation processing voltage is applied by applying a pulse sufficiently lower than the forming voltage V form is referred to as low resistance activation processing. In addition, the activation process is classified almost as a boundary except for a start voltage VP indicating a voltage control type negative resistance described later.

【0056】高抵抗活性化処理、低抵抗活性化処理の場
合の素子の形態変化を観察したものの模式図が図6の
(a)、(b)である。尚、上記観察は、FESEM、
TEM等によって行った。
FIGS. 6 (a) and 6 (b) are schematic views of morphological changes of the element observed in the high resistance activation process and the low resistance activation process. In addition, the above-mentioned observation was conducted by FESEM,
It was performed by TEM or the like.

【0057】図6の(a)、(b)は、それぞれ高抵抗
活性化処理、低抵抗活性化処理した場合の素子の断面で
ある。尚、5を高電位側電極、6を低電位側電極とし
て、電圧の印加が行われた。高抵抗活性化処理の場合を
示す図6の(a)では、フォーミングによって、導電性
膜4に、亀裂などの変形、変質をせしめた部分(高抵抗
部分)3の一部より主として高電位電極5側の導電性膜
4上に炭素あるいは炭素化合物61が堆積している。更
に高倍率で観察すると微粒子の周囲及び周辺にも堆積し
ている。また、対向する素子電極間距離にもよるが、素
子電極にも炭素あるいは炭素化合物61が堆積する場合
もある。その膜厚は、好ましくは、500オングストロ
ーム以下、より好ましくは、300オングストローム以
下である。
FIG. 6A and FIG. 6B are cross sections of the element when subjected to the high resistance activation treatment and the low resistance activation treatment, respectively. The voltage was applied with 5 as the high potential side electrode and 6 as the low potential side electrode. In (a) of FIG. 6 showing the case of the high resistance activation treatment, the high potential electrode is mainly formed than a part of the portion (high resistance portion) 3 in which the conductive film 4 is deformed or altered by forming, such as a crack. Carbon or carbon compound 61 is deposited on the conductive film 4 on the fifth side. When observed at a higher magnification, particles are deposited around and around the particles. Depending on the distance between the opposing device electrodes, carbon or carbon compound 61 may also be deposited on the device electrodes. The film thickness is preferably 500 angstroms or less, and more preferably 300 angstroms or less.

【0058】尚ここで、炭素あるいは炭素化合物とは、
TEM、ラマン等の結果、グラファイト(単、多結晶双
方を指す)、非晶質カーボン(非晶質カーボン及び多結
晶グラファイトとの混合物を指す)である。
Here, the term carbon or carbon compound means
As a result of TEM, Raman, and the like, graphite (refers to both single and polycrystalline) and amorphous carbon (refers to a mixture of amorphous carbon and polycrystalline graphite).

【0059】一方、低抵抗活性化処理の場合を示す図6
の(b)では、フォーミングによって変形、変質せしめ
た部分3の一部に炭素あるいは炭素化合物61が堆積し
ている。更に高倍率で観察すると微粒子の周囲及び周辺
にも堆積している。
On the other hand, FIG. 6 showing the case of low resistance activation processing.
In (b), carbon or a carbon compound 61 is deposited on a part of the portion 3 which is deformed and altered by forming. When observed at a higher magnification, particles are deposited around and around the particles.

【0060】尚、ここで、炭素あるいは炭素化合物と
は、先と同様、TEM、ラマン等の結果、グラファイト
(単、多結晶双方を指す)、非晶質カーボン(非晶質カ
ーボン及び多結晶グラファイトとの混合物を指す)であ
る。 5)こうして作成した電子放出素子を、好ましくは、フ
ォーミング処理及び活性化処理した真空度より高い真空
度の真空雰囲気にて駆動する。また、フォーミング処理
及び活性化処理した真空度より高い真空度の真空雰囲気
とは、好ましくは、約10のマイナス6乗torr以上
の真空度を有する真空度であり、より好ましくは、超高
真空系で、炭素、及び炭素化合物の新たに、ほぼ、堆積
しない真空度である。
Here, the carbon or carbon compound is the same as the above, as a result of TEM, Raman, etc., graphite (indicating both single and polycrystalline), amorphous carbon (amorphous carbon and polycrystalline graphite). And refers to the mixture). 5) The electron-emitting device thus produced is preferably driven in a vacuum atmosphere having a vacuum degree higher than the vacuum degree subjected to the forming treatment and the activation treatment. The vacuum atmosphere having a higher vacuum degree than the vacuum degree subjected to the forming treatment and the activation treatment is preferably a vacuum degree having a vacuum degree of about 10 −6 torr or more, more preferably an ultra-high vacuum system. Thus, the degree of vacuum at which carbon and carbon compounds are newly deposited is almost non-deposited.

【0061】従って、これによって、これ以上の炭素及
び炭素化合物の堆積を抑制する事が可能となり、素子電
流If、放出電流Ieが、一定に安定する。
Therefore, it becomes possible to suppress further deposition of carbon and carbon compounds, and the device current If and emission current Ie are stabilized constantly.

【0062】尚、高抵抗活性化処理、低抵抗活性化処理
の場合の素子では、駆動初期における安定性が異なり、
より好ましくは、高抵抗活性化処理が活性化処理として
選択される。
The elements in the high resistance activation treatment and the low resistance activation treatment have different stability in the initial driving stage.
More preferably, the high resistance activation treatment is selected as the activation treatment.

【0063】上述のような素子構成と製造方法によって
作成された本発明にかかわる電子放出素子の基本特性に
ついて図3、図7を用いて説明する。
The basic characteristics of the electron-emitting device according to the present invention produced by the above-described device structure and manufacturing method will be described with reference to FIGS.

【0064】図3に示した測定評価装置により測定され
た放出電流Ie及び素子電流Ifと素子電圧Vfの関係
の典型的な例を図7に示す。尚、図7は放出電流Ieは
素子電流Ifに比べて著しく小さいので、任意単位で示
されている。図7からも明らかなように、本電子放出素
子は放出電流Ieに対する3つの特性を有する。
FIG. 7 shows a typical example of the relationship between the emission voltage Ie and the device current If and the device voltage Vf measured by the measurement / evaluation apparatus shown in FIG. It should be noted that FIG. 7 shows the emission current Ie in an arbitrary unit because it is significantly smaller than the device current If. As is clear from FIG. 7, this electron-emitting device has three characteristics with respect to the emission current Ie.

【0065】まず第1に、本素子はある電圧(しきい値
電圧と呼ぶ、図7中のVth)以上の素子電圧を印加す
ると急激に放出電流Ieが増加し、一方しきい値電圧V
th以下では放出電流Ieがほとんど検出されない。す
なわち、放出電流Ieに対する明確なしきい値電圧Vt
hを持った非線形素子である。
First, in the present device, when a device voltage higher than a certain voltage (called threshold voltage, Vth in FIG. 7) is applied, the emission current Ie rapidly increases, while the threshold voltage V
Below th, the emission current Ie is hardly detected. That is, a clear threshold voltage Vt with respect to the emission current Ie
It is a non-linear element having h.

【0066】第2に、放出電流Ieが素子電圧Vfに依
存するため、放出電流Ieは素子電圧Vfで制御でき
る。
Secondly, since the emission current Ie depends on the element voltage Vf, the emission current Ie can be controlled by the element voltage Vf.

【0067】第3にアノード電極34に捕捉される放出
電荷は、素子電圧Vfを印加する時間に依存する。すな
わち、アノード電極34に捕捉される電荷量は、素子電
圧Vfを印加する時間により制御できる。
Thirdly, the emitted charges captured by the anode electrode 34 depend on the time for which the device voltage Vf is applied. That is, the amount of charge captured by the anode electrode 34 can be controlled by the time for which the device voltage Vf is applied.

【0068】一方、素子電流Ifは素子電圧Vfに対し
て単調増加する(MI特性と呼ぶ)特性(図7の実線)
及び電圧制御型負性抵抗(VCNR特性と呼ぶ)特性
(図7の破線)を示す場合があるが、これら素子電流の
特性は、その製法に依存する。又、VCNR特性を示す
境界電圧をVpという。
On the other hand, the element current If increases monotonically with the element voltage Vf (called MI characteristic) (solid line in FIG. 7).
And a voltage-controlled negative resistance (referred to as VCNR characteristic) characteristic (broken line in FIG. 7) may be shown, but the characteristic of these device currents depends on the manufacturing method. The boundary voltage showing the VCNR characteristic is called Vp.

【0069】即ち、素子電流IfのVCNR特性は、通
常の真空装置系で、フォーミングを行ったとき発生し、
その特性は、フォーミング時の電気的条件、真空装置系
の真空雰囲気条件等、あるいは、フォーミングを既に行
った電子放出素子の測定時の真空装置系の真空雰囲気条
件、測定時の電気的測定条件(例えば、電子放出素子の
電流−電圧特性を得るために、素子に印加する電圧を低
電圧から高電圧まで掃引した時の掃引速度等)測定時ま
での電子放出素子の真空装置内の放置時間等に依存し
て、大きく変わることが判明した。またこの時、放出電
流Ieは、MI特性を示す。
That is, the VCNR characteristic of the device current If occurs when forming is performed in an ordinary vacuum system,
The characteristics are the electrical conditions at the time of forming, the vacuum atmosphere conditions of the vacuum system, etc., the vacuum atmosphere conditions of the vacuum system at the time of measuring the electron-emitting device that has already been formed, the electrical measurement conditions at the time of measurement ( For example, in order to obtain the current-voltage characteristics of the electron-emitting device, the sweeping speed when the voltage applied to the device is swept from a low voltage to a high voltage, etc.) The time for which the electron-emitting device is left in the vacuum device until the measurement, etc. It turned out to vary greatly depending on. At this time, the emission current Ie shows MI characteristics.

【0070】以上のような表面伝導型電子放出素子の特
性、即ち、素子電流If、放出電流Ieの素子印加電圧
に対する単調増加特性を有するため、本発明にかかわる
電子放出素子は、多方面への応用が期待できる。
Since the surface conduction electron-emitting device has the characteristics as described above, that is, the characteristics of the device current If and the emission current Ie monotonically increasing with respect to the applied voltage of the device, the electron-emitting device according to the present invention can be applied to various fields. Application can be expected.

【0071】尚、あらかじめ導電性微粒子を分散して構
成した表面伝導型電子放出素子においては、前記本発明
の基本的な素子構成の基本的な製造方法のうちの一部を
変更してもよい。
In the case of the surface conduction electron-emitting device in which the conductive fine particles are dispersed in advance, a part of the basic manufacturing method of the basic device structure of the present invention may be modified. .

【0072】以上表面伝導型電子放出素子の基本的な構
成、製法について述べたが、本発明の思想によれば、表
面伝導形電子放出素子の特性で上述の3つの特徴を有す
れば、上述の構成等に限定されず、後述の電子源、表示
装置等の画像形成装置に於いても適用できる。
Although the basic structure and manufacturing method of the surface conduction electron-emitting device have been described above, according to the concept of the present invention, if the characteristics of the surface conduction electron-emitting device have the above-mentioned three characteristics, The present invention is not limited to the above-mentioned configuration, but can be applied to an image forming apparatus such as an electron source and a display device described later.

【0073】次に、本発明の電子源及び画像形成装置に
ついて述べる。
Next, the electron source and the image forming apparatus of the present invention will be described.

【0074】本発明の電子放出素子を複数個、基板上に
配列して、電子源あるいは、画像形成装置が構成でき
る。
By arranging a plurality of electron-emitting devices of the present invention on a substrate, an electron source or an image forming apparatus can be constructed.

【0075】基板上の配列の方式には、例えば、従来例
で述べた、多数の表面伝導型電子放出素子を並列に配置
し、個々の素子の両端を配線にて結線した、電子放出素
子の行を多数配列し(行方向と呼ぶ)、この配線と直交
する方向に(列方向と呼ぶ)、該電子源の上方の空間に
設置された制御電極(グリッドと呼ぶ)により電子を制
御駆動する配列形態(以後、はしご型という)、及び次
に述べるm本のX方向配線の上にn本のY方向配線を、
層間絶縁層を介して設置し、表面伝導形電子放出素子の
一対の素子電極にそれぞれ、X方向配線、Y方向配線を
接続した配列形態が挙げられる。これを単純マトリクス
配置と以降呼ぶ。
As the arrangement method on the substrate, for example, as described in the conventional example, a large number of surface conduction electron-emitting devices are arranged in parallel, and both ends of each device are connected by wirings. A large number of rows are arranged (called a row direction), electrons are controlled and driven by a control electrode (called a grid) installed in a space above the electron source in a direction orthogonal to this wiring (called a column direction). Arrangement form (hereinafter referred to as a ladder type), and n Y-direction wirings on m X-direction wirings described below,
There is an arrangement mode in which an X-direction wiring and a Y-direction wiring are connected to a pair of device electrodes of a surface conduction electron-emitting device, which are arranged via an interlayer insulating layer. This will be referred to as a simple matrix arrangement hereinafter.

【0076】次に、この単純マトリクスについて詳述す
る。
Next, this simple matrix will be described in detail.

【0077】本発明にかかわる表面伝導型電子放出素子
の前述した3つの基本的特性の特徴によれば、表面伝導
型電子放出素子からの放出電子は、しきい値電圧以上で
は、対向する素子電極間に印加するパルス状電圧の波高
値と巾で制御される。一方、しきい値電圧以下では、殆
ど放出されない。この特性によれば、多数の電子放出素
子を配置した場合においても、個々の素子に、上記パル
ス状電圧を適宜印加すれば、入力信号に応じて、表面伝
導型電子放出素子を選択し、その電子放出量が制御でき
る事となる。
According to the characteristics of the above-mentioned three basic characteristics of the surface conduction electron-emitting device according to the present invention, the emitted electrons from the surface conduction electron-emitting device are opposed to each other at the device electrodes above the threshold voltage. It is controlled by the peak value and the width of the pulse voltage applied in between. On the other hand, below the threshold voltage, it is hardly emitted. According to this characteristic, even when a large number of electron-emitting devices are arranged, if the pulsed voltage is appropriately applied to each device, the surface conduction electron-emitting device is selected according to the input signal, and The electron emission amount can be controlled.

【0078】以下、この原理に基づき構成した電子源基
板の構成について、図8を用いて説明する。
The configuration of the electron source substrate constructed based on this principle will be described below with reference to FIG.

【0079】m本のX方向配線82は、DX1、DX
2、‥DXmからなり、絶縁性基板1上に、真空蒸着
法、印刷法、スパッタ法等で形成し、所望のパーターン
とした導電性金属等からなり、多数の表面伝導型電子放
出素子にほぼ均等な電圧が供給される様に、材料、膜
厚、配線巾が設定される。Y方向配線83は、DY1、
DY2、‥DYnのn本の配線よりなり、X方向配線8
2と同様に、真空蒸着法、印刷法、スパッタ法等で形成
し、所望のパーターンとした導電性金属等からなり、多
数の表面伝導型電子放出素子にほぼ均等な電圧が供給さ
れる様に、材料、膜厚、配線巾等が設定される。これら
m本のX方向配線82とn本のY方向配線83間には、
不図示の層間絶縁層が設置され、電気的に分離されて、
マトリックス配線を構成する(このm、nは、共に正の
整数)。
The m X-direction wirings 82 are DX1 and DX.
2, ... DXm, which is formed on the insulating substrate 1 by a vacuum deposition method, a printing method, a sputtering method, or the like, and is made of a conductive metal or the like with a desired pattern, and is formed into a large number of surface conduction electron-emitting devices. The material, film thickness, and wiring width are set so that a uniform voltage is supplied. The Y-direction wiring 83 is DY1,
DY2, ... DYn consisting of n wires, X-direction wire 8
As in the case of 2, it is formed by a vacuum deposition method, a printing method, a sputtering method, or the like, and is made of a conductive metal or the like with a desired pattern, so that a substantially uniform voltage is supplied to many surface conduction electron-emitting devices. , Material, film thickness, wiring width, etc. are set. Between the m X-direction wirings 82 and the n Y-direction wirings 83,
An interlayer insulating layer (not shown) is installed and electrically separated,
A matrix wiring is formed (both m and n are positive integers).

【0080】不図示の層間絶縁層は、真空蒸着法、印刷
法、スパッタ法等で形成されたSiO2 等であり、X方
向配線82を形成した絶縁性基板1の全面あるいは一部
に所望の形状で形成され、特に、X方向配線82とY方
向配線83の交差部の電位差に耐え得る様に、膜厚、材
料、製法が適宜設定される。X方向配線82とY方向配
線83は、それぞれ外部端子として引き出されている。
The interlayer insulating layer (not shown) is SiO 2 or the like formed by a vacuum deposition method, a printing method, a sputtering method or the like, and is formed on the entire surface or a part of the insulating substrate 1 on which the X-direction wiring 82 is formed. The film thickness, the material, and the manufacturing method are appropriately set so as to withstand the potential difference at the intersection of the X-direction wiring 82 and the Y-direction wiring 83, in particular. The X-direction wiring 82 and the Y-direction wiring 83 are drawn out as external terminals.

【0081】更に、前述と同様にして、表面伝導型電子
放出素子84の対向する電極(不図示)が、m本のX方
向配線82(DX1、DX2、‥DXm)とn本のY方
向配線83(DY1、DY2、‥DYn)と、真空蒸着
法、印刷法、スパッタ法等で形成された導電性金属等か
らなる結線85によって電気的に接続されているもので
ある。
Further, in the same manner as described above, the opposing electrodes (not shown) of the surface conduction electron-emitting device 84 have m X-direction wirings 82 (DX1, DX2, ... DXm) and n Y-direction wirings. 83 (DY1, DY2, ... DYn) are electrically connected to each other by a connecting wire 85 made of a conductive metal or the like formed by a vacuum deposition method, a printing method, a sputtering method or the like.

【0082】ここで、m本のX方向配線82とn本のY
方向配線83と結線85と対向する素子電極の導電性金
属は、その構成元素の一部あるいは全部が同一であって
も、またそれぞれ異なってもよく、Ni、Cr、Au、
Mo、W、Pt、Ti、Al、Cu、Pd等の金属ある
いは合金及びPd、Ag、Au、RuO2、Pd−Ag
等の金属あるいは金属酸化物とガラス等から構成される
印刷導体、In2O3−SnO2等の透明導体及びポリ
シリコン等の半導体材料等より適宜選択される。また表
面伝導型電子放出素子は、絶縁性基板1、あるいは、不
図示の層間絶縁層上どちらに形成してもよい。
Here, m X-direction wirings 82 and n Y-direction wirings are provided.
The conductive metal of the element electrode facing the direction wiring 83 and the connection 85 may be the same or different in some or all of the constituent elements, and may be Ni, Cr, Au,
Metals or alloys such as Mo, W, Pt, Ti, Al, Cu, Pd and Pd, Ag, Au, RuO2, Pd-Ag
And the like, or a printed conductor composed of metal or metal oxide and glass, a transparent conductor such as In2O3-SnO2, a semiconductor material such as polysilicon, and the like. The surface conduction electron-emitting device may be formed either on the insulating substrate 1 or on an interlayer insulating layer (not shown).

【0083】又、詳しくは、後述するが、前記X方向配
線82には、X方向に配列する表面伝導型電子放出素子
84の行を、入力信号に応じて、走査するための走査信
号を印加するための不図示の走査信号印加手段と電気的
に接続され、一方、Y方向配線83には、Y方向に配列
する表面伝導型電子放出素子84の列の各列を入力信号
に応じて、変調するための変調信号を印加するための不
図示の変調信号発生手段と電気的に接続される。
Further, as will be described in detail later, a scanning signal for scanning the row of the surface conduction electron-emitting devices 84 arranged in the X direction according to the input signal is applied to the X-direction wiring 82. Is electrically connected to a scanning signal applying means (not shown), and the Y-direction wiring 83 is provided with each of the columns of the surface conduction electron-emitting devices 84 arranged in the Y-direction in accordance with an input signal. It is electrically connected to a modulation signal generating means (not shown) for applying a modulation signal for modulation.

【0084】更に、表面伝導型電子放出素子の各素子に
印加される駆動電圧は、当該素子に印加される走査信号
と変調信号の差電圧として供給されるものである。
Further, the drive voltage applied to each element of the surface conduction electron-emitting device is supplied as a difference voltage between the scanning signal applied to the element and the modulation signal.

【0085】次に、以上のようにして作成した電子源基
板を用いた電子源、及び、表示等に用いる画像形成装置
について図9と図10を用いて説明する。図9は画像形
成装置の基本構成図であり、図10は蛍光膜である。
Next, an electron source using the electron source substrate produced as described above and an image forming apparatus used for display will be described with reference to FIGS. 9 and 10. FIG. 9 is a basic configuration diagram of the image forming apparatus, and FIG. 10 is a fluorescent film.

【0086】図9において、1は基板、91は基板1を
固定したリアプレート、96は、ガラス基板93の内面
に蛍光膜94とメタルバック95等が形成されたフェー
スプレート、92は、支持枠であり、リアプレート9
1、支持枠92及びフェースプレート96をフリットガ
ラス等を塗布し、大気中あるいは、窒素中で、400〜
500℃で10分以上焼成することで、封着して、外囲
器98を構成する。
In FIG. 9, 1 is a substrate, 91 is a rear plate to which the substrate 1 is fixed, 96 is a face plate in which a fluorescent film 94 and a metal back 95 are formed on the inner surface of a glass substrate 93, and 92 is a support frame. And the rear plate 9
1, the support frame 92 and the face plate 96 are coated with frit glass or the like, and 400 to 400 in the air or nitrogen.
By firing at 500 ° C. for 10 minutes or more, they are sealed to form the envelope 98.

【0087】図9において、84は、図1あるいは図1
2に示された表面伝導型電子放出素子に相当する。8
2、83は、表面伝導形電子放出素子の一対の素子電極
と接続されたX方向配線及びY方向配線である。また、
これら素子電極への配線は、素子電極と配線材料が同一
である場合は、素子電極と呼ぶ場合もある。
In FIG. 9, reference numeral 84 designates FIG. 1 or FIG.
This corresponds to the surface conduction electron-emitting device shown in 2. 8
Reference numerals 2 and 83 are an X-direction wiring and a Y-direction wiring connected to a pair of device electrodes of the surface conduction electron-emitting device. Also,
Wiring to these element electrodes may be called element electrodes when the same wiring material is used for the element electrodes.

【0088】外囲器98は、上述の如く、フェースプレ
ート96、支持枠92、リアプレート91で外囲器98
を構成したが、リアプレート91は主に基板1の強度を
補強する目的で設けられてるため、基板1自体で十分な
強度を持つ場合は別体のリアプレート91は不要であ
り、基板1に直接支持枠92を封着し、フェースプレー
ト96、支持枠92、基板1にて外囲器98を構成して
も良い。
The envelope 98 includes the face plate 96, the support frame 92, and the rear plate 91 as described above.
However, since the rear plate 91 is provided mainly for the purpose of reinforcing the strength of the substrate 1, if the substrate 1 itself has sufficient strength, the separate rear plate 91 is unnecessary, and Alternatively, the support frame 92 may be directly sealed, and the face plate 96, the support frame 92, and the substrate 1 may constitute the envelope 98.

【0089】図10は、蛍光膜である。蛍光膜94は、
モノクロームの場合は蛍光体のみから成るが、カラーの
蛍光膜の場合は、蛍光体の配列によりブラックストライ
プあるいはブラックマトリクスなどと呼ばれる黒色導伝
材101と蛍光体102とで構成される。ブラックスト
ライプ、ブラックマトリクスが設けられる目的は、カラ
ー表示の場合必要となる3原色蛍光体の、各蛍光体10
2間の塗り分け部を黒くすることで混色等を目立たなく
することと、蛍光膜94における外光反射によるコント
ラストの低下を抑制することである。ブラックストライ
プの材料としては、通常良く用いられている黒鉛を主成
分とする材料だけでなく、導電性があり、光の透過及び
反射が少ない材料であればこれに限るものではない。
FIG. 10 shows a fluorescent film. The fluorescent film 94 is
In the case of monochrome, it is composed of only the phosphor, but in the case of a color phosphor film, it is composed of a black conductive material 101 and a phosphor 102 called a black stripe or a black matrix depending on the arrangement of the phosphors. The purpose of providing the black stripes and the black matrix is to provide each of the phosphors 10 of the three primary color phosphors required for color display.
It is to make the color-separated portion between the two black so as to make the color mixture inconspicuous and to suppress the deterioration of the contrast due to the reflection of external light on the fluorescent film 94. The material of the black stripe is not limited to the commonly used material containing graphite as a main component, but is not limited to this as long as it is a material having conductivity and little light transmission and reflection.

【0090】ガラス基板93に蛍光体を塗布する方法は
モノクローム、カラーによらず、沈殿法や印刷法が用い
られる。
As a method of applying the phosphor to the glass substrate 93, a precipitation method or a printing method is used regardless of monochrome or color.

【0091】また、蛍光膜94の内面側には通常メタル
バック95が設けられる。メタルバックの目的は、蛍光
体の発生のうち内面側への光をフェースプレート96側
へ鏡面反射することにより輝度を向上すること、電子ビ
ーム加速電圧を印加するための電極として作用するこ
と、外囲器内で発生した負イオンの衝突によるダメージ
からの蛍光体の保護等である。メタルバックは、蛍光膜
作製後、蛍光膜の内面側表面の平滑化処理(通常フィル
ミングと呼ばれる)を行い、その後A1を真空蒸着等で
堆積することで作製できる。
A metal back 95 is usually provided on the inner surface side of the fluorescent film 94. The purpose of the metal back is to improve the brightness by specularly reflecting the light toward the inner surface side of the generation of the phosphor to the face plate 96 side, to act as an electrode for applying an electron beam acceleration voltage, and to This is to protect the phosphor from damage due to collision of negative ions generated in the enclosure. The metal back can be produced by performing a smoothing process (usually called filming) on the inner surface of the fluorescent film after producing the fluorescent film, and then depositing A1 by vacuum evaporation or the like.

【0092】フェースプレート96には、更に蛍光膜9
4の導伝性を高めるため、蛍光膜94の外面側に透明電
極(不図示)が設けてもよい。
The face plate 96 further includes a fluorescent film 9
In order to improve the conductivity of No. 4, a transparent electrode (not shown) may be provided on the outer surface side of the fluorescent film 94.

【0093】前述の封着を行う際、カラーの場合は各色
蛍光体と電子放出素子とを対応させなくてはいけないた
め、十分な位置合わせを行なう必要がある。
At the time of performing the above-mentioned sealing, in the case of color, it is necessary to sufficiently align the phosphors of the respective colors with the electron-emitting devices.

【0094】外囲器98は、不図示の排気管を通じ、1
0のマイナス6乗トール程度の真空度にされ、外囲器9
8の封止がおこなわれる。
The envelope 98 is provided with an exhaust pipe (not shown)
A vacuum degree of 0 minus 6 torr is applied, and the envelope 9
8 is sealed.

【0095】尚、電子源基板は、前述した通りに電子放
出部を形成した図1あるいは図12の素子が、基板上に
上記の如く配置、配線されたものでも良いが、好ましく
は電子放出部形成前の素子、例えば図2の(b)にしさ
れた状態の素子を、基板上に上記の如く配置、配線し、
これを図9に示す外囲器98内に配置した後、不図示の
排気管を通じ、例えば、ロータリーポンプ、ターボポン
プをポンプ系とする様な通常の真空装置系で該外囲器内
を、10のマイナス6乗トール程度の真空度とし、容器
外端子Dox1ないしDoxmとDoy1ないしDoy
nを通じ素子電極5、6(図2の(b))間に電圧を印
加し、上述のフォーミングを行い、次に、前記活性化処
理を、該外囲器内を10のマイナス6乗トール程度の真
空度として行うことにより電子放出部3を形成して、電
子源基板を作製する。
The electron source substrate may be one in which the element of FIG. 1 or FIG. 12 in which the electron emitting portion is formed as described above is arranged and wired on the substrate as described above, but the electron emitting portion is preferable. The element before formation, for example, the element in the state shown in FIG. 2B is arranged and wired on the substrate as described above,
After arranging this in the envelope 98 shown in FIG. 9, the inside of the envelope is passed through an exhaust pipe (not shown) by an ordinary vacuum system such as a rotary pump or a turbo pump. The degree of vacuum is about 10 −6 torr, and terminals outside the container Dox1 to Doxm and Doy1 to Doy
A voltage is applied between the device electrodes 5 and 6 ((b) of FIG. 2) through n to perform the above-described forming, and then the activation process is performed inside the envelope by about 10 <-6> torr. Then, the electron emission portion 3 is formed by performing the vacuum treatment as described above, and the electron source substrate is manufactured.

【0096】以上の様に作製の後、特には、その後、8
0度〜150度でベーキングを3〜15時間行いなが
ら、例えば、イオンポンプ等のポンプ系とする超高真空
装置系にきりかえる。超高真空系の切り替え、及びベー
キングは、前述の表面伝導型電子放出素子の素子電流I
f、放出電流Ieの単調増加特性(MI特性)を満足す
るためであり、その方法、条件はこれに限るものでな
い。また、外囲器98の封止後の真空度を維持するため
に、ゲッター処理を行う場合もある。これは、外囲器9
8の封止を行う直前あるいは封止後に、抵抗加熱あるい
は高周波加熱等の加熱法により、外囲器98内の所定の
位置(不図示)に配置されたゲッターを加熱し、蒸着膜
を形成する処理である。ゲッターは通常Ba等が主成分
であり、該蒸着膜の吸着作用により、たとえば1×10
マイナス5乗ないしは1×10マイナス7乗[Tor
r]の真空度を維持するものである。
After manufacturing as described above, particularly, after that, 8
While baking is performed at 0 to 150 degrees for 3 to 15 hours, the system is switched to an ultra-high vacuum apparatus system that is a pump system such as an ion pump. Switching of the ultra-high vacuum system and baking are performed by the device current I of the surface conduction electron-emitting device described above.
This is because f and the monotonically increasing characteristic (MI characteristic) of the emission current Ie are satisfied, and the method and conditions are not limited to this. Further, a getter process may be performed in order to maintain the degree of vacuum after the envelope 98 is sealed. This is the envelope 9
Immediately before or after the sealing of No. 8, a getter arranged at a predetermined position (not shown) in the envelope 98 is heated by a heating method such as resistance heating or high frequency heating to form a vapor deposition film. Processing. The getter usually has Ba or the like as a main component, and is, for example, 1 × 10 5 due to the adsorption action of the deposited film.
Minus 5th power or 1 × 10 Minus 7th power [Tor
The vacuum degree of r] is maintained.

【0097】以上により完成した本発明の画像表示装置
において、各電子放出素子には、容器外端子Dox1な
いしDoxm、Doy1ないしDoynを通じ、電圧を
印加することにより、電子放出させ、高圧端子Hvを通
じ、メタルバック95あるいは透明電極(不図示)に数
kV以上の高圧を印加し、電子ビームを加速し、蛍光膜
94に衝突させ、励起・発光させることで画像を表示す
るものである。
In the image display device of the present invention completed as described above, each electron-emitting device is caused to emit electrons by applying a voltage through terminals outside the container Dox1 to Doxm, Doy1 to Doyn, and through the high voltage terminal Hv. An image is displayed by applying a high voltage of several kV or more to the metal back 95 or a transparent electrode (not shown), accelerating the electron beam, causing the electron beam to collide with the fluorescent film 94, and exciting and emitting light.

【0098】以上述べた構成は、表示等に用いられる好
適な画像形成装置を作製する上で必要な概略構成であ
り、例えば各部材の材料等、詳細な部分は上述内容に限
られるものではなく、画像装置の用途に適するよう適宜
選択する。
The above-described structure is a schematic structure necessary for producing a suitable image forming apparatus used for display and the like, and the detailed parts such as the material of each member are not limited to those described above. , As appropriate for the application of the image device.

【0099】[0099]

【実施例】以下に、実施例をあげて、本発明をさらに詳
述する。
EXAMPLES The present invention will be described in more detail below with reference to examples.

【0100】(実施例1)本発明にかかわる基本的な表
面伝導型電子放出素子の構成は、図1の(a)、(b)
の平面図及び断面図と同様である。
(Embodiment 1) The structure of a basic surface conduction electron-emitting device according to the present invention is as shown in FIGS.
It is similar to the plan view and cross-sectional view of FIG.

【0101】尚、基板1上には、同一形状の素子が図1
1に示すように4個形成されている。尚、図11におい
て、図1と同一の番号のものは、同一のものを示す。
On the substrate 1, elements of the same shape are shown in FIG.
Four are formed as shown in FIG. In FIG. 11, the same numbers as in FIG. 1 indicate the same items.

【0102】本発明に係わる表面伝導形電子放出素子の
製造法は、基本的には図2と同様である。以下、図1、
図2を用いて、本発明に係わる素子の基本的な構成及び
製造法を説明する。
The method of manufacturing the surface conduction electron-emitting device according to the present invention is basically the same as that shown in FIG. Below, FIG.
The basic structure and manufacturing method of the device according to the present invention will be described with reference to FIG.

【0103】図1において、1は基板、5と6は素子電
極、4は電子放出部を含む薄膜、3は電子放出部であ
る。
In FIG. 1, 1 is a substrate, 5 and 6 are device electrodes, 4 is a thin film including an electron emitting portion, and 3 is an electron emitting portion.

【0104】以下、順をおって製造方法の説明を図1及
び図2に基づいて説明する。
The manufacturing method will be sequentially described below with reference to FIGS. 1 and 2.

【0105】工程−a:清浄化した青板ガラス上に厚さ
0.5ミクロンのシリコン酸化膜をスパッタ法で形成し
た基板1上に、素子電極5と素子電極間ギャップGとな
るべきパターンをホトレジスト(RD−2000N−4
1日立化成社製)で形成し、真空蒸着法により、厚さ5
0ÅのTi、厚さ1000ÅNiを順次堆積した。ホト
レジストパターンを有機溶剤で溶解し、Ni/Ti堆積
膜をリフトオフし、素子電極間隔Gは3ミクロンとし、
素子電極の幅W1を300ミクロンを有する素子電極
5、6を形成した(図2の(a))。
Step-a: On the substrate 1 in which a 0.5 μm thick silicon oxide film is formed on the cleaned soda-lime glass by the sputtering method, a pattern for forming the device electrode 5 and the device electrode gap G is formed by photoresist. (RD-2000N-4
1 made by Hitachi Chemical Co., Ltd.), and the thickness is 5 by the vacuum deposition method.
0 Å Ti and 1000 Å Ni having a thickness were sequentially deposited. The photoresist pattern is dissolved in an organic solvent, the Ni / Ti deposition film is lifted off, and the device electrode gap G is set to 3 μm.
Device electrodes 5 and 6 having a device electrode width W1 of 300 μm were formed ((a) of FIG. 2).

【0106】工程−b:素子間電極ギャップGおよびこ
の近傍に開口を有するマスクにより膜厚1000ÅのC
r膜121を真空蒸着により堆積・パターニングし、そ
のうえに有機Pd(ccp4230奥野製薬(株)社
製)をスピンナーにより回転塗布、300℃で10分間
の加熱焼成処理をした。また、こうして形成された主元
素としてPbよりなる微粒子からなる電子放出部形成用
薄膜2の膜厚は100オングストローム、シート抵抗値
は2×10の4乗Ω/□であった。なおここで述べる微
粒子膜とは、上述したように、複数の微粒子が集合した
膜であり、その微細構造として、微粒子が個々に分散配
置した状態のみならず、微粒子が互いに隣接、あるい
は、重なり合った状態(島状も含む)の膜をさし、その
粒径とは、前記状態で粒子形状が認識可能な微粒子につ
いての径をいう。
Step-b: C having a film thickness of 1000 Å by a mask having an inter-element electrode gap G and an opening in the vicinity thereof.
The r film 121 was deposited and patterned by vacuum evaporation, and then organic Pd (ccp4230 manufactured by Okuno Chemical Industries Co., Ltd.) was spin-coated by a spinner and heated and baked at 300 ° C. for 10 minutes. The thickness of the electron emission part forming thin film 2 formed of fine particles of Pb as the main element thus formed was 100 angstrom, and the sheet resistance value was 2 × 10 4 Ω / □. Note that the fine particle film described here is a film in which a plurality of fine particles are aggregated as described above, and as a fine structure, not only the fine particles are individually dispersed and arranged, but also the fine particles are adjacent to each other or overlap each other. A film in a state (including an island shape) is referred to, and the particle diameter thereof means a diameter of fine particles whose particle shape can be recognized in the above state.

【0107】工程−c:Cr膜および焼成後の電子放出
部形成用薄膜2を酸エッチャントによりエッチングして
所望のパターンを形成した。以上の工程により基板1上
に、素子電極5、6、電子放出部形成用薄膜2等を形成
した(図2の(b))。
Step-c: The Cr film and the electron emission part forming thin film 2 after firing were etched by an acid etchant to form a desired pattern. Through the above steps, the device electrodes 5 and 6, the electron emission portion forming thin film 2 and the like were formed on the substrate 1 ((b) of FIG. 2).

【0108】工程−d:次に、図3の測定評価装置に設
置し、真空ポンプにて排気し、2×10のマイナス5乗
torrの真空度に達した後、素子に素子電圧Vfを印
加するための電源31より、4素子各々の素子電極5、
6間にそれぞれ、電圧を印加し、通電処理(フォーミン
グ処理)した。フォーミング処理の電圧波形を図4の
(b)に示す。
Step-d: Next, the device is installed in the measurement / evaluation apparatus of FIG. 3, evacuated by a vacuum pump, and after reaching a vacuum degree of 2 × 10 −5 torr, the device voltage Vf is applied to the device. From the power supply 31 for
A voltage was applied to each of 6 and an energization process (forming process) was performed. The voltage waveform of the forming process is shown in FIG.

【0109】図4の(b)中、T1及びT2は電圧波形
のパルス幅とパルス間隔であり、本実施例ではT1を1
ミリ秒、T2を10ミリ秒とし、矩形波の波高値(フォ
ーミング時のピーク電圧)は0.1Vステップで昇圧
し、フォーミング処理を行なった。また、フォーミング
処理中は、同時に、0.1Vの電圧で、T2間に抵抗測
定パルスを挿入し、抵抗を測定した。尚フォーミング処
理の終了は、抵抗測定パルスでの測定値が、約1Mオー
ム以上になった時とし、同時に、素子への電圧の印加を
終了した。それぞれの素子のフォーミング電圧V
formは、5.1V、5.0V、5.0V、5.15Vで
あった。
In FIG. 4B, T1 and T2 are the pulse width and pulse interval of the voltage waveform, and in this embodiment T1 is 1
With the millisecond and T2 set to 10 milliseconds, the peak value of the rectangular wave (peak voltage during forming) was increased in 0.1 V steps to perform the forming process. Further, during the forming process, a resistance measuring pulse was inserted between T2 at a voltage of 0.1 V at the same time to measure the resistance. The forming process was terminated when the measured value by the resistance measurement pulse became about 1 M ohm or more, and at the same time, the application of the voltage to the element was terminated. Forming voltage V of each element
The form was 5.1V, 5.0V, 5.0V, 5.15V.

【0110】工程−e:続いて、フォーミング処理した
4素子に対しそれぞれ、図4の(b)の波形で矩形波の
波高値をそれぞれ4Vと14Vで、各2個づつ活性化処
理をした。低抵抗活性化処理つまり、4Vで活性化処理
した素子サンプルを素子A、高抵抗活性化処理、つまり
14Vで活性化処理をした素子サンプルを素子Bと呼ぶ
ことにする。
Step-e: Subsequently, each of the four elements subjected to the forming treatment was subjected to an activation treatment with two crest values of the rectangular wave having the waveform of FIG. 4B at 4 V and 14 V, respectively. An element sample that has undergone low resistance activation processing, that is, activation processing at 4V is referred to as element A, and an element sample that has performed high resistance activation processing, that is, activation processing at 14V, is referred to as element B.

【0111】活性化処理とは前述した様に、図3の測定
評価装置内で、素子電極間にパルス電圧を、素子電流I
f及び放出電流Ieを測定しながら、印加した。尚、こ
の時、図3の測定評価装置内の真空度は、1.5×10
のマイナス5乗torrであった。約30分で活性化処
理を終了した。
As described above, the activation process is performed by applying the pulse voltage between the device electrodes and the device current I in the measurement and evaluation device of FIG.
It was applied while measuring f and emission current Ie. At this time, the degree of vacuum in the measurement and evaluation device of FIG.
It was minus 5 torr. The activation treatment was completed in about 30 minutes.

【0112】こうして、電子放出部3を形成し電子放出
素子を作製した。
Thus, the electron emitting portion 3 was formed and the electron emitting device was manufactured.

【0113】上述の工程で作製した表面伝導形電子放出
素子の特性及び形態を把握するために、上記素子A、B
を各1個づつ、その電子放出特性の測定を上述の図3の
測定評価装置を用いて行った。また残りの1個づつを電
子顕微鏡で観察した。
In order to understand the characteristics and morphology of the surface conduction electron-emitting device manufactured in the above process, the above devices A and B were used.
One by one, and the electron emission characteristics thereof were measured by using the above-described measurement and evaluation apparatus of FIG. The remaining ones were observed with an electron microscope.

【0114】なお、アノード電極と電子放出素子間の距
離を4mm、アノード電極の電位を1kV、電子放出特
性測定時の真空装置内の真空度を1×10のマイナス6
乗torrとした。素子A、Bとも、電極5及び6の間
に素子電圧を14V印加し、その時に流れる素子電流I
f及び放出電流Ieを測定した。素子Aでは、測定開始
直後に10mA程度の素子電流Ifが流れ、次第に減少
し、それにともない、放出電流Ieが観察された。一
方、素子Bでは、測定初期より、安定した素子電流I
f、放出電流Ieが観察され、素子電圧14Vでは素子
電流Ifが2.0mA、放出電流Ieが1.0μAとな
り、電子放出効率η=Ie/If×100(%)は0.
05%であった。以上より、素子Aは、素子電流If
が、測定初期において、著しく大きく、不安定である
が、一方、素子Bでは測定初期より、安定でかつ効率η
のよい電子放出素子であることがわかる。
The distance between the anode electrode and the electron-emitting device was 4 mm, the potential of the anode electrode was 1 kV, and the degree of vacuum in the vacuum apparatus at the time of measuring the electron emission characteristics was 1 × 10 minus 6.
The power was torr. In both the devices A and B, a device voltage of 14 V is applied between the electrodes 5 and 6, and a device current I flowing at that time is applied.
f and the emission current Ie were measured. In the device A, a device current If of about 10 mA flows immediately after the start of the measurement, and the device current If gradually decreases, and accordingly, the emission current Ie was observed. On the other hand, in the element B, a stable element current I is obtained from the initial measurement.
f, the emission current Ie was observed, the device current If was 2.0 mA and the emission current Ie was 1.0 μA at the device voltage of 14 V, and the electron emission efficiency η = Ie / If × 100 (%) was 0.
It was 05%. From the above, the element A has the element current If
However, in the initial measurement, it is significantly large and unstable.
It can be seen that the electron-emitting device has a good electron emission.

【0115】また、素子Bについて、活性化処理の真空
度1.5×10のマイナス5乗に戻し、素子に0.00
5Hz程度の三角波で電圧を掃印しながら、素子電流I
f、放出電流Ieを測定すると、図7に示される破線の
特性を示した。図7に示される様に、約5V前後まで、
素子電流Ifは、単調増加したのち、5V以上で電圧制
御型負性抵抗を示す。この時、素子電流Ifが最大を示
す電圧(VPと呼ぶ)は、5Vである。また10V以上
では、素子電流Ifは、最大の素子電流の数分の1の1
mA程度であった。電子顕微鏡で観察した素子A、Bの
形態は、図6の(a)、(b)に示したものと同様であ
る。図6の(B)より素子Aでは、素子電極間の薄膜
(導電性膜)4の変質部分3の一部に多くの被膜(堆積
物)61が形成されているのがわかる。一方、素子Bで
は、図6の(a)より、活性化処理時の素子への電圧の
印加方向に依存して、特に、変質部分3の一部より高電
位電極5側の導電性膜4上を主として、被膜(堆積物)
61が形成されていた。更に、高倍率のFESEM(2
次電子顕微鏡の略)で観察すると、この被膜は、金属微
粒子の周囲及び微粒子間にも形成されているようであっ
た。
Regarding the element B, the degree of vacuum in the activation treatment was returned to 1.5 × 10 to the power of −5, and the element was adjusted to 0.005.
While sweeping the voltage with a triangular wave of about 5 Hz, the device current I
When f and the emission current Ie were measured, the characteristic of the broken line shown in FIG. 7 was shown. As shown in FIG. 7, up to about 5V,
The element current If monotonically increases and then exhibits a voltage control type negative resistance at 5 V or higher. At this time, the voltage at which the device current If is maximum (called VP) is 5V. At 10 V or higher, the device current If is 1/1 of the maximum device current.
It was about mA. The forms of the elements A and B observed with an electron microscope are the same as those shown in FIGS. 6A and 6B. From FIG. 6B, it can be seen that in the device A, many coatings (deposits) 61 are formed on a part of the altered portion 3 of the thin film (conductive film) 4 between the device electrodes. On the other hand, in the element B, as shown in FIG. 6A, the conductive film 4 closer to the high potential electrode 5 than a part of the altered portion 3 depends on the direction of voltage application to the element during the activation process. Mainly on top, film (deposit)
61 was formed. Furthermore, high magnification FESEM (2
When observed with a secondary electron microscope), this coating appeared to be formed around the metal fine particles and between the fine particles.

【0116】尚、TEM(透過電子顕微鏡)ラマン等で
観察すると、グラファイト、アモルファスカーボンから
なる炭素被膜が観察された。
When observed by TEM (Transmission Electron Microscope) Raman or the like, a carbon film made of graphite or amorphous carbon was observed.

【0117】又、これらの観察により、素子Aでは、先
に述べた電圧制御型負性抵抗を示す電圧Vp以下で活性
化されたため、フォーミング処理によって発生した薄膜
の変質部の一部に、素子Bより多くの炭素が形成され、
著しく大きな素子電流が流れ、測定電圧で、薄膜変質部
の高電位側と低電位側間に形成された炭素被膜が電流パ
スとなり、素子Bの数倍の素子電流が流れ、駆動初期か
ら素子電流が変動したと考えられる。
Further, from these observations, since the element A was activated at the voltage Vp or lower indicating the voltage controlled negative resistance described above, the element A was partially formed on the altered portion of the thin film generated by the forming process. More carbon is formed than B,
A remarkably large element current flows, and at the measurement voltage, the carbon film formed between the high potential side and the low potential side of the thin film alteration portion becomes a current path, and the element current several times that of the element B flows. Is thought to have fluctuated.

【0118】一方、高抵抗活性化処理をおこなった素子
Bでは、先に述べた電圧制御型負性抵抗を示す電圧Vp
以上で活性化されたため、素子A同様に、変質部の一部
に炭素被膜が形成されながらも、素子Aよりは炭素被膜
の部分的に電気的に切断された部位が多いと考えられ
る。このため、駆動初期より安定した電流になったと考
えられる。
On the other hand, in the element B which has been subjected to the high resistance activation processing, the voltage Vp showing the voltage control type negative resistance described above.
Since it is activated as described above, it is considered that, like the element A, although the carbon coating is formed on a part of the altered portion, the carbon coating is more electrically partially cut than the element A. Therefore, it is considered that the current became stable from the initial stage of driving.

【0119】以上より高抵抗活性化処理により、素子電
流If、放出電流Ieが安定し、かつ、効率のよい電子
放出が作成された。
As described above, by the high resistance activation treatment, the device current If and the emission current Ie were stabilized, and efficient electron emission was produced.

【0120】(実施例2)本実施例は、多数の表面伝導
形電子放出素子を単純マトリクス配置した画像形成装置
の例である。
(Embodiment 2) This embodiment is an example of an image forming apparatus in which a large number of surface conduction electron-emitting devices are arranged in a simple matrix.

【0121】電子源の一部の平面図を図13に示す。ま
た、図中のA−A′断面図を図14に示す。但し、図1
3、図14、図15、図16で、同じ記号を示したもの
は、同じものを示す。ここで1は基板、82は図8のD
xmに対応するX方向配線(下配線とも呼ぶ)、83は
図8のDynに対応するY方向配線(上配線とも呼
ぶ)、4は電子放出部を含む薄膜、5、6は素子電極、
141は層間絶縁層、142は素子電極5と下配線82
と電気的接続のためのコンタクトホールである。
A plan view of a part of the electron source is shown in FIG. 14 is a sectional view taken along the line AA 'in FIG. However, in FIG.
3, FIG. 14, FIG. 15, and FIG. 16, the same symbols indicate the same items. Here, 1 is a substrate, and 82 is D in FIG.
X-direction wiring (also called lower wiring) corresponding to xm, 83 Y-direction wiring corresponding to Dyn in FIG. 8 (also called upper wiring), 4 is a thin film including an electron emitting portion, 5 and 6 are device electrodes,
141 is an interlayer insulating layer, 142 is the element electrode 5 and the lower wiring 82.
And a contact hole for electrical connection.

【0122】次に、製造方法を図15、図16により工
程順に従って具体的に説明する。
Next, the manufacturing method will be specifically described in the order of steps with reference to FIGS.

【0123】工程−a:清浄化した青板ガラス上に厚さ
0.5ミクロンのシリコン酸化膜をスパッタ法で形成し
た基板1上に、真空蒸着により厚さ50オングストロ−
ムのCr、厚さ6000オングストロ−ムのAuを順次
積層した後、ホトレジスト(AZ1370ヘキスト社
製)をスピンナーにより回転塗布、ベークした後、ホト
マスク像を露光、現像して、下配線82のレジストパタ
ーンを形成し、Au/Cr堆積膜をウエットエッチング
して、所望の形状の下配線82を形成する(図15の
(a))。
Step-a: 50 angstroms thick by vacuum deposition on a substrate 1 formed by sputtering a 0.5 μm thick silicon oxide film on a cleaned soda lime glass.
After sequentially laminating Cr of Cr and Au of 6000 Å in thickness, spin coating a photoresist (manufactured by AZ1370 Hoechst) with a spinner and baking, exposing and developing a photomask image, and a resist pattern of the lower wiring 82. Is formed, and the Au / Cr deposited film is wet-etched to form the lower wiring 82 having a desired shape ((a) of FIG. 15).

【0124】工程−b:次に、厚さ1.0ミクロンのシ
リコン酸化膜からなる層間絶縁層141をRFスパッタ
法により堆積する(図15の(b))。
Step-b: Next, an interlayer insulating layer 141 made of a silicon oxide film having a thickness of 1.0 micron is deposited by the RF sputtering method ((b) of FIG. 15).

【0125】工程−c:前記工程bで堆積したシリコン
酸化膜にコンタクトホール142を形成するためのホト
レジストパターンを作り、これをマスクとして層間絶縁
層141をエッチングしてコンタクトホール142を形
成する。エッチングはCF4とH2ガスを用いたRIE
(Reactive Ion Etching)法によ
った(図15の(c))。
Step-c: A photoresist pattern for forming the contact hole 142 is formed in the silicon oxide film deposited in the step b, and the interlayer insulating layer 141 is etched using this as a mask to form the contact hole 142. RIE using CF4 and H2 gas for etching
(Reactive Ion Etching) method ((c) of FIG. 15).

【0126】工程−d:その後、素子電極5と素子電極
間ギャップGとなるべきパターンをホトレジスト(RD
−2000N−41日立化成社製)で形成し、真空蒸着
法により、厚さ50オングストロ−ムのTi、厚さ10
00オングストロ−ムのNiを順次堆積した。ホトレジ
ストパターンを有機溶剤で溶解し、Ni/Ti堆積膜を
リフトオフし、素子電極間隔Gは3ミクロン、素子電極
の幅W1は300ミクロンとし、素子電極5、6を形成
した(図15の(d))。
Step-d: After that, a pattern which is to be the device electrode 5 and the device electrode gap G is formed with a photoresist (RD).
-2000N-41 manufactured by Hitachi Chemical Co., Ltd.), Ti of 50 angstrom in thickness and 10 in thickness by vacuum evaporation method.
00 Angstrom of Ni was sequentially deposited. The photoresist pattern was dissolved in an organic solvent, the Ni / Ti deposited film was lifted off, the device electrode spacing G was 3 μm, and the device electrode width W1 was 300 μm to form the device electrodes 5 and 6 ((d in FIG. 15). )).

【0127】工程−e:素子電極5、6の上に上配線8
3のホトレジストパターンを形成した後、厚さ50オン
グストロ−ムのTi、厚さ5000オングストロ−ムの
Auを順次、真空蒸着により堆積し、リフトオフにより
不要の部分を除去して、所望の形状の上配線84を形成
した(図16の(e))。
Process-e: Upper wiring 8 on the device electrodes 5 and 6
After forming the photoresist pattern of No. 3, Ti with a thickness of 50 Å and Au with a thickness of 5000 Å are sequentially deposited by vacuum evaporation, and unnecessary portions are removed by lift-off to obtain a desired shape. The wiring 84 was formed ((e) of FIG. 16).

【0128】工程−f:膜厚1000オングストロ−ム
のCr膜151を真空蒸着により堆積・パターニング
し、その上に有機Pd(ccp4230奥野製薬(株)
社製)をスピンナーにより回転塗布、300℃で10分
間の加熱焼成処理をした。また、こうして形成された主
元素としてPdよりなる微粒子からなる電子放出部形成
用薄膜2の膜厚は85オングストローム、シート抵抗値
は3.9×10の4乗Ω/□であった。なおここで述べ
る微粒子膜とは、上述したように、複数の微粒子が集合
した膜であり、その微細構造として、微粒子が個々に分
散配置した状態のみならず、微粒子が互いに隣接、ある
いは、重なり合った状態(島状も含む)の膜をさし、そ
の粒径とは、前記状態で粒子形状が認識可能な微粒子に
ついての径をいう(図16の(f))。
Step-f: A Cr film 151 having a film thickness of 1000 Å is deposited and patterned by vacuum evaporation, and organic Pd (ccp4230 Okuno Seiyaku Co., Ltd.) is formed thereon.
Was manufactured by spin coating with a spinner and heated and baked at 300 ° C. for 10 minutes. Further, the film thickness of the electron emission portion forming thin film 2 formed of fine particles of Pd as the main element thus formed was 85 angstrom, and the sheet resistance value was 3.9 × 10 4 Ω / □. Note that the fine particle film described here is a film in which a plurality of fine particles are aggregated as described above, and as a fine structure, not only the fine particles are individually dispersed and arranged, but also the fine particles are adjacent to each other or overlap each other. A film in a state (including an island shape) is referred to, and the particle diameter thereof means a diameter of fine particles whose particle shape can be recognized in the above state ((f) in FIG. 16).

【0129】工程−g:Cr膜151及び焼成後の電子
放出部形成用薄膜2を酸エッチャントによりエッチング
して所望のパターンを形成した(図16の(g))。
Step-g: The Cr film 151 and the electron emission portion forming thin film 2 after firing were etched by an acid etchant to form a desired pattern ((g) of FIG. 16).

【0130】工程−h:コンタクトホール142部分以
外にレジストを塗布するようなパターンを形成し、真空
蒸着により厚さ50オングストロ−ムのTi、厚さ50
00オングストロ−ムのAuを順次堆積した。リフトオ
フにより不要の部分を除去することにより、コンタクト
ホール142を埋め込んだ(図16の(h))。
Step-h: A pattern is formed such that a resist is applied to a portion other than the contact hole 142 portion, and Ti having a thickness of 50 Å and a thickness of 50 are formed by vacuum evaporation.
00 angstrom of Au was sequentially deposited. The contact hole 142 was buried by removing unnecessary portions by lift-off ((h) of FIG. 16).

【0131】以上の工程により絶縁性基板1上に下配線
82、層間絶縁層141、上配線83、素子配線5、
6、電子放出部形成用薄膜2等を形成した。
Through the above steps, the lower wiring 82, the interlayer insulating layer 141, the upper wiring 83, the element wiring 5, and the like are formed on the insulating substrate 1.
6. A thin film 2 for forming an electron emitting portion and the like were formed.

【0132】次に、以上のようにして作成した電子源基
板を用いて、電子源及び表示装置を構成した例を、図9
と図10を用いて説明する。
Next, an example in which an electron source and a display device are constructed by using the electron source substrate created as described above is shown in FIG.
Will be described with reference to FIG.

【0133】以上のようにして素子を作製した基板1
を、リアプレート91上に固定した後、基板1の5mm
上方に、フェースプレート96(ガラス基板93の内面
に蛍光膜94とメタルバック95が形成されて構成され
る)を支持枠92を介し配置し、フェースプレート9
6、支持枠92、リアプレート91の接合部にフリット
ガラスを塗布し、大気中あるいは窒素雰囲気中で400
℃ないし500℃で10分以上焼成することで封着し
た。またリアプレート91への基板1の固定もフリット
ガラスで行った。
Substrate 1 on which the device is manufactured as described above
Is fixed on the rear plate 91, and then 5 mm of the substrate 1
A face plate 96 (which is formed by forming a fluorescent film 94 and a metal back 95 on the inner surface of a glass substrate 93) is arranged above the support frame 92, and the face plate 9 is provided.
6, frit glass is applied to the joint portion of the support frame 92 and the rear plate 91, and 400
It was sealed by baking at 10 to 500 ° C. for 10 minutes or more. The frit glass was also used to fix the substrate 1 to the rear plate 91.

【0134】本実施例において図9の84は、電子放出
部形成前の電子放出素子(例えば、図2の(b)に相当
する)であり、82、83はそれぞれX方向及びY方向
の素子配線である。
In the present embodiment, 84 in FIG. 9 is an electron-emitting device before the formation of an electron-emitting portion (eg, corresponds to (b) in FIG. 2), and 82 and 83 are devices in the X and Y directions, respectively. Wiring.

【0135】蛍光膜94は、モノクロームの場合は蛍光
体のみから成るが、本実施例では蛍光体はストライプ形
状を採用し(図10の(a))、先にブラックストライ
プを形成し、その間隙部に各色蛍光体を塗布し、蛍光膜
94を作製した。ブラックストライプの材料として通常
良く用いられている黒鉛を主成分とする材料を用いた。
ガラス基板93に蛍光体を塗布する方法はスラリー法を
用いた。
In the case of monochrome, the fluorescent film 94 is composed of only the fluorescent material, but in this embodiment, the fluorescent material adopts a stripe shape ((a) of FIG. 10), and a black stripe is formed first, and the gap is formed. Each part was coated with a phosphor of each color to form a phosphor film 94. As a material for the black stripe, a material containing graphite as a main component, which is often used, was used.
A slurry method was used to apply the phosphor to the glass substrate 93.

【0136】また、蛍光膜94の内面側には通常メタル
バック95が設けられる。メタルバックは、蛍光膜作製
後、蛍光膜の内面側表面の平滑化処理(通常フィルミン
グと呼ばれる)を行い、その後、A1を真空蒸着するこ
とで作製した。
A metal back 95 is usually provided on the inner surface side of the fluorescent film 94. The metal back was produced by performing a smoothing treatment (usually called filming) on the inner surface of the fluorescent film after producing the fluorescent film, and then vacuum-depositing A1.

【0137】フェースプレート96には、更に蛍光膜9
4の導伝性を高めるため、蛍光膜94の外面側に透明電
極(不図示)が設けらる場合もあるが、本実施例では、
メタルバックのみで十分な導伝性が得られたので省略し
た。
The face plate 96 further includes a fluorescent film 9
In order to improve the conductivity of No. 4, a transparent electrode (not shown) may be provided on the outer surface side of the fluorescent film 94, but in this embodiment,
It was omitted because sufficient conductivity was obtained only with the metal back.

【0138】前述の封着を行う際、カラーの場合は各色
蛍光体と電子放出素子とを対応させなくてはいけないた
め、十分な位置合わせを行った。
When performing the above-mentioned sealing, in the case of a color, the phosphors of the respective colors and the electron-emitting devices must correspond to each other, so that sufficient alignment was performed.

【0139】以上のようにして完成したガラス容器内の
雰囲気を排気管(図示せず)を通じ真空ポンプにて排気
し、十分な真空度に達した後、容器外端子Dxo1ない
しDoxmとDoy1ないしDoynを通じ電子放出素
子74の電極5、6間に電圧を印加し、電子放出部形成
用薄膜2をフォーミング処理した。フォーミング処理の
電圧波形は、図4の(b)と同様である。
The atmosphere in the glass container completed as described above is exhausted by a vacuum pump through an exhaust pipe (not shown), and after reaching a sufficient degree of vacuum, the external terminals Dxo1 to Doxm and Doy1 to Doyn. A voltage was applied between the electrodes 5 and 6 of the electron-emitting device 74 through the film to form the electron-emitting portion forming thin film 2. The voltage waveform of the forming process is similar to that of FIG.

【0140】本実施例ではT1を1ミリ秒、T2を10
ミリ秒とし、約1×10のマイナス5乗torrの真空
雰囲気下で行った。
In this embodiment, T1 is 1 millisecond and T2 is 10
It was performed in a vacuum atmosphere of about 1 × 10 minus 5 torr.

【0141】このように作成された電子放出部3は、パ
ラジウム元素を主成分とする微粒子が分散配置された状
態となり、その微粒子の平均粒径は30オングストロー
ムであった。
In the electron-emitting portion 3 thus formed, fine particles containing palladium as a main component were dispersed and arranged, and the average particle diameter of the fine particles was 30 Å.

【0142】次にフォーミングと同一の矩形波で、波高
14Vで、真空度2×10のマイナス5乗torrの真
空度で、素子電流If、放出電流Ieを測定しながら、
高抵抗活性化処理を行った。
Next, while measuring the element current If and the emission current Ie with the same rectangular wave as the forming, a wave height of 14 V, and a vacuum degree of 2 × 10 minus 5 torr.
High resistance activation treatment was performed.

【0143】フォーミング、活性化処理を行い、電子放
出部3を形成し電子放出素子84を作製した。
Forming and activation treatments were performed to form the electron emitting portion 3 and the electron emitting device 84 was manufactured.

【0144】次に10のマイナス6乗トール程度の真空
度まで排気し、不図示の排気管をガスバーナーで熱する
ことで溶着し外囲器の封止を行った。
Next, the vacuum was evacuated to about 10 −6 torr, and the exhaust pipe (not shown) was heated by a gas burner to be welded to seal the envelope.

【0145】最後に封止後の真空度を維持するために、
高周波加熱法でゲッター処理を行った。
Finally, in order to maintain the degree of vacuum after sealing,
Getter processing was performed by the high frequency heating method.

【0146】以上のように完成した本発明の画像表示装
置において、各電子放出素子には、容器外端子Dx1な
いしDxm、Dy1ないしDynを通じ、走査信号及び
変調信号を不図示の信号発生手段より、それぞれ印加す
ることにより、電子放出させ、高圧端子Hvを通じ、メ
タルバック95に5kV以上の高圧を印加し、電子ビー
ムを加速し、蛍光膜99に衝突させ、励起・発光させる
ことで画像を表示した。又、素子電流If、放出電流I
eは双方とも図7の実線を示し、駆動初期から安定であ
った。又、この時、テレビジョンに要求される輝度10
0fL〜150fLにも対応できる放出電流であった。
In the image display device of the present invention completed as described above, the scanning signal and the modulation signal are supplied to each electron-emitting device through the external terminals Dx1 to Dxm and Dy1 to Dyn from the signal generating means (not shown). By applying each, electrons are emitted, and a high voltage of 5 kV or more is applied to the metal back 95 through the high voltage terminal Hv, the electron beam is accelerated, collided with the fluorescent film 99, excited and emitted to display an image. . Also, the device current If and the emission current I
Both e indicate the solid line in FIG. 7 and were stable from the initial stage of driving. Also, at this time, the brightness 10 required for the television
The emission current was compatible with 0 fL to 150 fL.

【0147】(実施例3)図17は、前記説明の表面伝
導形電子放出素子を電子源として用いたディスプレイパ
ネルに、たとえばテレビジョン放送をはじめとする種々
の画像情報源より提供される画像情報を表示できるよう
に構成した表示装置の一例を示すための図である。図1
7中、17100はディスプレイパネル、17101は
ディスプレイパネルの駆動回路、17102はディスプ
レイコントローラ、17103はマチプレクサ、171
04はデコーダ、17105は入出力インターフェース
回路、17106はCPU、17107は画像生成回
路、17108及び17109及び17110は画像メ
モリーインターフェース回路、17111は画像入力イ
ンターフェース回路、17112及び17113はTV
信号受信回路、17114は入力部である(なお、本表
示装置は、例えばテレビジョン信号のように映像情報と
音声情報の両方を含む信号を受信する場合には、当然映
像の表示と同時に音声を再生するものであるが、本発明
の特徴と直接関係しない音声情報の受信、分離、再生、
記憶などに関する回路やスピーカーなどについては説明
を省略する。)。
(Third Embodiment) FIG. 17 shows a display panel using the surface conduction electron-emitting device described above as an electron source, and image information provided from various image information sources such as television broadcasting. It is a figure for showing an example of a display constituted so that it can display. Figure 1
In FIG. 7, 17100 is a display panel, 17101 is a display panel drive circuit, 17102 is a display controller, 17103 is a macyplexer, 171.
Reference numeral 04 is a decoder, 17105 is an input / output interface circuit, 17106 is a CPU, 17107 is an image generation circuit, 17108 and 17109 and 17110 are image memory interface circuits, 17111 is an image input interface circuit, and 17112 and 17113 are TVs.
The signal receiving circuit 17114 is an input unit (note that when the display device receives a signal including both video information and audio information, such as a television signal, of course, the audio is simultaneously displayed with the video. Receiving, separation, reproduction of audio information that is to be reproduced but is not directly related to the features of the present invention.
Descriptions of circuits and speakers related to memory are omitted. ).

【0148】以下、画像信号の流れに沿って各部の機能
を説明してゆく。
The function of each section will be described below along the flow of the image signal.

【0149】まず、TV信号受信回路17113は、例
えば電波や空間光通信などのような無線伝送系を用いて
伝送されるTV画像信号を受信する為の回路である。受
信するTV信号の方式は特に限られものではなく、例え
ば、NTSC方式、PAL方式、SECAM方式などの
諸方式でもよい。また、これらより更に多数の走査線よ
りなるTV信号(例えばMUSE方式をはじめとするい
わゆる高品位TV)は、大面積化や大画素数化に適した
前記ディスプレイパネルの利点を生かすのに好適な信号
源である。TV信号受信回路17113で受信されたT
V信号は、デコーダ17104に出力される。
First, the TV signal receiving circuit 17113 is a circuit for receiving a TV image signal transmitted using a wireless transmission system such as radio waves or spatial optical communication. The system of the TV signal to be received is not particularly limited, and various systems such as NTSC system, PAL system and SECAM system may be used. Further, a TV signal (for example, a so-called high-definition TV such as the MUSE system) including a larger number of scanning lines than these is suitable for taking advantage of the display panel suitable for a large area and a large number of pixels. It is a signal source. T received by the TV signal receiving circuit 17113
The V signal is output to the decoder 17104.

【0150】また、TV信号受信回路17112は、例
えば同軸ケーブルや光ファイバー等のような有線伝送系
を用いて伝送されるTV画像信号を受信する為の回路で
ある。前記TV信号受信回路17113と同様に、受信
するTV信号の方式は特に限られるものではなく、また
本回路で受信されたTV信号もデコーダ17104に出
力される。
The TV signal receiving circuit 17112 is a circuit for receiving a TV image signal transmitted using a wire transmission system such as a coaxial cable or an optical fiber. Similar to the TV signal receiving circuit 17113, the TV signal system to be received is not particularly limited, and the TV signal received by this circuit is also output to the decoder 17104.

【0151】また、画像入力インターフェース回路17
111は、例えばTVカメラや画像読み取りスキャナー
等の画像入力装置から供給される画像信号を取り込むた
めの回路で、取り込まれた画像信号はデコーダ1710
4に出力される。
Further, the image input interface circuit 17
Reference numeral 111 denotes a circuit for capturing an image signal supplied from an image input device such as a TV camera or an image reading scanner. The captured image signal is a decoder 1710.
4 is output.

【0152】また、画像メモリーインターフェース回路
17110は、ビデオテープレコーダー(以下VTRと
略す)に記憶されている画像信号を取り込むための回路
で、取り込まれた画像信号はデコーダ17104に出力
される。
The image memory interface circuit 17110 is a circuit for capturing the image signal stored in the video tape recorder (hereinafter abbreviated as VTR), and the captured image signal is output to the decoder 17104.

【0153】また、画像メモリーインターフェース回路
17109は、ビデオディスクに記憶されている画像信
号を取り込むための回路で、取り込まれた画像信号はデ
コーダ17104に出力される。
The image memory interface circuit 17109 is a circuit for fetching the image signal stored in the video disc, and the fetched image signal is output to the decoder 17104.

【0154】また、画像メモリーインターフェース回路
17108は、いわゆる静止画ディスクのように、静止
画像データを記憶している装置から画像信号を取り込む
ための回路で、取り込まれた静止画像データはデコーダ
17104に入力される。また、入出力インターフェー
ス回路17105は、本表示装置と、外部のコンピュー
タもしくはコンピュータネットワークもしくはプリンタ
ーなどの出力装置とを接続するための回路である。画像
データや文字・図形情報の入出力を行うのはもちろんの
こと、場合によっては本表示装置の備えるCPU171
06と外部との間で制御信号や数値データの入出力など
を行うことも可能である。
The image memory interface circuit 17108 is a circuit for capturing an image signal from a device that stores still image data, such as a so-called still image disc. The captured still image data is input to the decoder 17104. To be done. The input / output interface circuit 17105 is a circuit for connecting the display device to an external computer, a computer network, or an output device such as a printer. In addition to inputting / outputting image data and character / graphic information, in some cases, the CPU 171 provided in the display device.
It is also possible to input and output control signals and numerical data between 06 and the outside.

【0155】また、画像生成回路17107は、前記入
出力インターフェース回路17105を介して外部から
入力される画像データや文字・図形情報や、あるいはC
PU17106より出力される画像データや文字・図形
情報に基づき表示用画像データを生成するための回路で
ある。本回路の内部には、例えば画像データや文字・図
形情報を蓄積するための書き換え可能メモリーや、文字
コードに対応する画像パターンが記憶されている読み出
し専用メモリーや、画像処理を行うためのプロセッサー
等をはじめとして画像の生成に必要な回路が組み込まれ
ている。
Further, the image generation circuit 17107 is provided with image data, character / graphic information, or C data inputted from the outside through the input / output interface circuit 17105.
This is a circuit for generating display image data based on image data and character / graphic information output from the PU 17106. Inside this circuit, for example, a rewritable memory for storing image data and character / graphic information, a read-only memory that stores image patterns corresponding to character codes, a processor for image processing, etc. And the circuits necessary for image generation are incorporated.

【0156】本回路により生成された表示用画像データ
は、デコーダ17104に出力されるが、場合によって
は前記入出力インターフェース回路17105を介して
外部のコンピュータネットワークやプリンターに出力す
ることも可能である。
The display image data generated by this circuit is output to the decoder 17104, but in some cases, it may be output to an external computer network or printer via the input / output interface circuit 17105.

【0157】また、CPU17106は、主として本表
示装置の動作制御や、表示画像の生成や選択や編集に関
わる作業を行う。
Further, the CPU 17106 mainly performs operations related to operation control of the display device and generation, selection and editing of a display image.

【0158】例えば、マルチプレクサ17103に制御
信号を出力し、ディスプレイパネルに表示する画像信号
を適宜選択したり組み合わせたりする。また、その際に
は表示する画像信号に応じてディスプレイパネルコント
ローラ17102に対して制御信号を発生し、画面表示
周波数や走査方法(例えばインターレースかノンインタ
ーレースか)や一画面の走査線の数など表示装置の動作
を適宜制御する。
For example, a control signal is output to the multiplexer 17103 to appropriately select or combine image signals to be displayed on the display panel. At that time, a control signal is generated to the display panel controller 17102 according to the image signal to be displayed, and the screen display frequency, the scanning method (for example, interlaced or non-interlaced), the number of scanning lines in one screen, etc. are displayed. The operation of the device is controlled appropriately.

【0159】また、前記画像生成回路17107に対し
て画像データや文字・図形情報を直接出力したり、ある
いは前記入出力インターフェース回路17105を介し
て外部のコンピュータやメモリーをアクセスして画像デ
ータや文字・図形情報を入力する。なお、CPU171
06は、むろんこれ以外の目的の作業にも関わるもので
あって良い。例えば、パーソナルコンピュータやワード
プロセッサなどのように、情報を生成したり処理する機
能に直接関わっても良い。あるいは、前述したように入
出力インターフェース回路17105を介して外部のコ
ンピュータネットワークと接続し、例えば数値計算など
の作業を外部機器と協同して行っても良い。
Image data and character / graphic information may be directly output to the image generation circuit 17107, or an external computer or memory may be accessed via the input / output interface circuit 17105 to access the image data and character / figure information. Enter graphic information. The CPU 171
Of course, 06 may be related to work for other purposes. For example, it may be directly related to a function of generating and processing information, such as a personal computer or a word processor. Alternatively, as described above, the computer may be connected to an external computer network via the input / output interface circuit 17105, and work such as numerical calculation may be performed in cooperation with an external device.

【0160】また、入力部17114は、前記CPU1
7106に使用者が命令やプログラム、あるいはデータ
等を入力するためのものであり、例えばキーボードやマ
ウスのほか、ジョイスティック、バーコードリーダー、
音声認識装置など多様な入力機器を用いる事が可能であ
る。
The input unit 17114 is the CPU 1
7106 is for a user to input commands, programs, data, etc., such as a keyboard, a mouse, a joystick, a bar code reader,
It is possible to use various input devices such as a voice recognition device.

【0161】また、デコーダ17104は、前記171
07ないし17113より入力される種々の画像信号を
3原色信号、または輝度信号とI信号、Q信号に逆変換
するための回路である。なお、同図中に点線で示すよう
に、デコーダ17104は内部に画像メモリーを備える
のが望ましい。これは、例えばMUSE方式をはじめと
して、逆変換するに際して画像メモリーを必要とするよ
うなテレビ信号を扱うためである。
Further, the decoder 17104 has the above-mentioned 171
This is a circuit for inversely converting various image signals input from 07 to 17113 into three primary color signals, or a luminance signal and an I signal and a Q signal. It is desirable that the decoder 17104 has an image memory therein, as indicated by a dotted line in the figure. This is to handle a television signal that requires an image memory for reverse conversion, such as the MUSE method.

【0162】また、画像メモリーを備える事により、静
止画の表示が容易になる、あるいは前記画像生成回路1
7107及びCPU17106と協同して画像の間引
き、補間、拡大、縮小、合成をはじめとする画像処理や
編集が容易に行えるようになるという利点が生まれるか
らである。
Further, the provision of the image memory facilitates the display of a still image, or the image generation circuit 1 described above.
This is because, in cooperation with the 7107 and the CPU 17106, there is an advantage that image processing and editing such as image thinning, interpolation, enlargement, reduction, and composition can be easily performed.

【0163】また、マルチプレクサ17103は、前記
CPU17106より入力される制御信号に基づき表示
画像を適宜選択するものである。すなわち、マルチプレ
クサ17103はデコーダ17104から入力される逆
変換された画像信号のうちから所望の画像信号を選択し
て駆動回路17101に出力する。その場合には、一画
面表示時間内で画像信号を切り替えて選択することによ
り、いわゆる多画面テレビのように、一画面を複数の領
域に分けて領域によって異なる画像を表示することも可
能である。
Further, the multiplexer 17103 is for appropriately selecting the display image based on the control signal inputted from the CPU 17106. That is, the multiplexer 17103 selects a desired image signal from the inversely converted image signals input from the decoder 17104 and outputs it to the drive circuit 17101. In that case, by switching and selecting image signals within one screen display time, it is possible to divide one screen into a plurality of areas and display different images depending on the areas, as in a so-called multi-screen television. .

【0164】また、ディスプレイパネルコントローラ1
7102は、前記CPU17106より入力される制御
信号に基づき駆動回路17101の動作を制御するため
の回路である。
Also, the display panel controller 1
Reference numeral 7102 is a circuit for controlling the operation of the drive circuit 17101 based on a control signal input from the CPU 17106.

【0165】まず、ディスプレイパネルの基本的な動作
に関わるものとしては、たとえばディスプレイパネルの
駆動用電源(図示せず)の動作シーケンスを制御するた
めの信号を駆動回路17101に対して出力する。ま
た、ディスプレイパネルの駆動方法に関わるものとし
て、たとえば画面表示周波数や走査方法(たとえばイン
ターレースかノンインターレースか)を制御するための
信号を駆動回路17101に対して出力する。
First, regarding the basic operation of the display panel, for example, a signal for controlling the operation sequence of the power source (not shown) for driving the display panel is output to the drive circuit 17101. Further, as a signal relating to the display panel driving method, for example, a signal for controlling the screen display frequency and the scanning method (for example, interlace or non-interlace) is output to the drive circuit 17101.

【0166】また、場合によっては表示画像の輝度やコ
ントラストや色調やシャープネスといった画質の調整に
関わる制御信号を駆動回路17101に対して出力する
場合もある。
In some cases, control signals relating to image quality adjustment such as brightness, contrast, color tone and sharpness of a display image may be output to the drive circuit 17101.

【0167】また、駆動回路17101はディスプレイ
パネル17100に印加する駆動信号を発生するための
回路であり、前記マルチプレクサ17103から入力さ
れる画像信号と、前記ディスプレイパネルコントローラ
17102より入力される制御信号にもとづいて動作す
るものである。
The drive circuit 17101 is a circuit for generating a drive signal to be applied to the display panel 17100, and is based on the image signal input from the multiplexer 17103 and the control signal input from the display panel controller 17102. It works.

【0168】以上、各部の機能を説明したが、図17に
例示した構成により、本表示装置においては多様な画像
情報源より入力される画像情報をディスプレイパネル1
7100に表示する事が可能である。すなわち、テレビ
ジョン放送をはじめとする各種の画像信号はデコーダ1
7104において逆変換された後、マルチプレクサ17
103において適宜選択され、駆動回路17101に入
力される。一方、ディスプレイコントローラ17102
は、表示する画像信号に応じて駆動回路17101の動
作を制御するための制御信号を発生する。駆動回路17
101は、上記画像信号と制御信号にもとづいてディス
プレイパネル17100に駆動信号を印加する。これに
より、ディスプレイパネル17100において画像が表
示される。これらの一連の動作は、CPU17106に
より統括的に制御される。
The functions of the respective parts have been described above. With the configuration illustrated in FIG. 17, the display panel 1 displays image information input from various image information sources in this display device.
7100 can be displayed. That is, various image signals such as television broadcasting are transmitted to the decoder 1
After inverse conversion at 7104, multiplexer 17
It is appropriately selected in 103 and input to the drive circuit 17101. On the other hand, the display controller 17102
Generates a control signal for controlling the operation of the drive circuit 17101 according to the image signal to be displayed. Drive circuit 17
Reference numeral 101 applies a drive signal to the display panel 17100 based on the image signal and the control signal. As a result, the image is displayed on the display panel 17100. A series of these operations is controlled by the CPU 17106 as a whole.

【0169】また、本表示装置においては、前記デコー
ダ17104に内蔵する画像メモリや、画像生成回路1
7107および情報の中から選択したものを表示するだ
けでなく、表示する画像情報に対して、たとえば拡大、
縮小、回転、移動、エッジ強調、間引き、補間、色変
換、画像の縦横比変換などをはじめとする画像処理や、
合成、消去、接続、入れ換え、はめ込みなどをはじめと
する画像編集を行う事も可能である。また、本実施例の
説明では特に触れなかったが、上記画像処理や画像編集
と同様に、音声情報に関しても処理や編集を行なうため
の専用回路を設けても良い。
Further, in this display device, the image memory built in the decoder 17104 and the image generation circuit 1 are provided.
7107 and not only the one selected from the information is displayed, but the image information to be displayed is enlarged, for example,
Image processing such as reduction, rotation, movement, edge enhancement, thinning, interpolation, color conversion, image aspect ratio conversion, etc.
It is also possible to perform image editing such as composition, deletion, connection, replacement, and fitting. Further, although not particularly mentioned in the description of the present embodiment, a dedicated circuit for processing and editing voice information may be provided as in the above-mentioned image processing and image editing.

【0170】したがって、本表示装置はテレビジョン放
送の表示機器、テレビ会議の端末機器、静止画像および
動画像を扱う画像編集機器、コンピュータの端末機器、
ワードプロセッサをはじめとする事務用端末機器、ゲー
ム機などの機能を一台で兼ね備えることが可能で、産業
用あるいは民生用として極めて応用範囲が広い。
Therefore, the present display device is a display device for television broadcasting, a terminal device for a video conference, an image editing device for handling still images and moving images, a terminal device for a computer,
It is possible to combine the functions of office terminals such as word processors, game consoles, etc., with a very wide range of applications for industrial or consumer use.

【0171】なお、上記図17は表示伝導形放出素子を
電子ビーム源とするディスプレイパネルを用いた表示装
置の構成の一例を示したにすぎず、これのみに限定され
るものでない事は言うまでもない。たとえば、図17の
構成要素のうち使用目的上必要のない機能に関わる回路
は省いても差し支えない。またこれとは逆に、使用目的
によってはさらに構成要素を追加しても良い。たとえ
ば、本表示装置をテレビ電話機として応用する場合に
は、テレビカメラ、音声マイク、照明機、モデムを含む
送受信回路などを構成要素に追加するのが好適である。
It is needless to say that FIG. 17 shows only an example of the structure of a display device using a display panel having a display conduction type emission element as an electron beam source, and is not limited to this. . For example, of the constituent elements of FIG. 17, circuits relating to functions that are unnecessary for the purpose of use may be omitted. On the contrary, the constituent elements may be added depending on the purpose of use. For example, when the display device is applied as a video telephone, it is preferable to add a television camera, a voice microphone, an illuminator, a transmission / reception circuit including a modem, and the like to the components.

【0172】本表示装置においては、とりわけ表面伝導
形電子放出素子を電子ビーム源とするディスプレイパネ
ルの薄形化が容易なため、表示装置の奥行きを小さくす
ることができる。それに加えて、表面伝導形電子放出素
子を電子ビーム源とするディスプレイパネルは大画面化
が容易で輝度が高く視野角特性にも優れるため、本表示
装置は臨場感にあふれ迫力に富んだ画像を視認性良く表
示する事が可能である。
In this display device, the depth of the display device can be reduced because the display panel using the surface conduction electron-emitting device as an electron beam source can be easily thinned. In addition, a display panel using a surface conduction electron-emitting device as an electron beam source can easily enlarge the screen, has high brightness, and has excellent viewing angle characteristics, so that this display device can display a realistic image and a powerful image. It is possible to display with good visibility.

【0173】(実施例4)本実施例は多数の表面伝導型
電子放出素子と、制御電極(グリッド)を有する画像形
成装置の例である。
(Embodiment 4) This embodiment is an example of an image forming apparatus having a large number of surface conduction electron-emitting devices and control electrodes (grids).

【0174】本実施例の画像形成装置の製造方法は実施
例2とほぼ同等な方法で作製したので説明を詳細する。
The method of manufacturing the image forming apparatus according to this embodiment is almost the same as that of the second embodiment, and thus the description will be described in detail.

【0175】まず、表面伝導形電子放出素子を基板上に
多数個設けた電子源と、これを応用した表示装置の実施
例を説明する。図19および図20は、基板上に表面伝
導形電子放出素子の多数個を配列形成した電子源の2つ
の例を説明するための模式図である。
First, an embodiment of an electron source in which a large number of surface conduction electron-emitting devices are provided on a substrate and a display device to which the electron source is applied will be described. 19 and 20 are schematic diagrams for explaining two examples of electron sources in which a large number of surface conduction electron-emitting devices are formed on a substrate.

【0176】まず、図19においてSはたとえばガラス
を材料とする絶縁性基板、点線で囲んだESは前記基板
Sの上に設けられた表面伝導形電子放出素子、E1〜E
10は前記表面伝導形電子放出素子を配線するための配
線電極をあらわしている。表面伝導形電子放出素子は基
板上にX方向に沿って列をなして形成されている(以
下、これを素子列と呼ぶ)。各素子列を構成する表面伝
導形電子放出素子は、これを挟む両側の配線電極によっ
て電気的に並列に共通配線されている(たとえば、第1
列は両側の配線電極E1とE2によって配線されてい
る)。
First, in FIG. 19, S is an insulating substrate made of, for example, glass, ES surrounded by a dotted line is a surface conduction electron-emitting device provided on the substrate S, E1 to E.
Reference numeral 10 represents a wiring electrode for wiring the surface conduction electron-emitting device. The surface conduction electron-emitting devices are formed on the substrate in rows along the X direction (hereinafter referred to as element rows). The surface conduction electron-emitting devices that form each device row are electrically wired in parallel by the wiring electrodes on both sides sandwiching the device (for example, the first
The columns are wired by the wiring electrodes E1 and E2 on both sides).

【0177】本実施例の電子源は、配線電極間に適宜の
駆動電圧を印加することにより、各素子列を独立に駆動
することが可能である。すなわち、電子ビームを放出さ
せたい素子列には電子放出閾値を上回る適当な電圧を、
また電子ビームを放出しない素子列には電子放出閾値を
越えない適当な電圧(たとえば0[V])を印加すれば
よい(なお、以下の説明では、電子放出閾値を上回る適
当な駆動電圧をVE[V]と記す。)。
The electron source of this embodiment can drive each element array independently by applying an appropriate drive voltage between the wiring electrodes. That is, an appropriate voltage higher than the electron emission threshold is applied to the element array from which the electron beam is to be emitted,
Further, an appropriate voltage (for example, 0 [V]) that does not exceed the electron emission threshold may be applied to the element array that does not emit the electron beam (in the following description, an appropriate drive voltage that exceeds the electron emission threshold is VE). [V].).

【0178】次に、図20に示すのは電子源の他の一例
であり、Sはたとえばガラスを材料とする絶縁性基板、
点線で囲んだESは前記基板Sの上に設けられた表面伝
導形電子放出素子、E′1〜E′6は前記表面伝導形電
子放出素子を共通配線するための配線電極をあらわして
いる。前記図19の例と同様、本実施例においても表面
伝導形電子放出素子はX方向に沿って列をなして形成さ
れ、各素子列の表面伝導形電子放出素子は配線電極によ
って電気的に並列に共通配線されている。さらに、たと
えば素子列の第1列と第2列の片側の共通配線を配線電
極E′2が兼ねているように、本実施例においては隣接
する素子列の隣接する側の共通配線を1本の配線電極で
行っている。本実施例の電子源は、前記図19の列と比
較して同一形状の表面伝導形電子放出素子と配線電極を
用いた場合に、Y方向に配列する配列間隔を小さくでき
るという利点がある。
Next, FIG. 20 shows another example of the electron source, where S is an insulating substrate made of glass, for example.
ES surrounded by a dotted line represents a surface conduction electron-emitting device provided on the substrate S, and E'1 to E'6 represent wiring electrodes for common wiring of the surface conduction electron-emitting device. Similar to the example of FIG. 19, also in this embodiment, the surface conduction electron-emitting devices are formed in rows along the X direction, and the surface conduction electron-emitting devices of each device row are electrically connected in parallel by the wiring electrodes. Are commonly wired to. Further, in this embodiment, for example, one common wiring on the adjacent side of the adjacent element row is used so that the wiring electrode E'2 also serves as the common wiring on one side of the first row and the second row of the element row. This is done with the wiring electrodes. The electron source of this embodiment has an advantage that the arrangement interval in the Y direction can be reduced when the surface conduction electron-emitting devices and the wiring electrodes having the same shape are used as compared with the column of FIG.

【0179】本実施例の電子源は、配線電極間に適宜の
駆動電圧を印加することにより、各素子列を独立に駆動
することが可能である。すなわち、電子放出させたい電
子放出素子列はVE[V]を、電子放出させない素子列
にはたとえば0[V]の電圧を印加すればよい。たとえ
ば、第3列だけを駆動したい場合には、E′1〜E′3
の各配線電極には0[V]の電位を、またE′4〜E′
6の各配線電極にはVE[V]の電位を印加する。その
結果、第3列の素子列には、VE−0=VE[V]の電
圧が印加されるが、他の素子列に対しては、0−0=0
[V]かまたはVE−VE=0[V]というように0
[V]の電圧が印加されることになるわけである。ま
た、たとえば第2列と第5列を同時に駆動させる場合に
は、配線電極E′1とE′2とE′6には0[V]の電
位を、配線電極E′3とE′4とE′5にはVE[V]
の電位を印加すればよい。このように、本実施例におい
ても任意の素子列を選択的に駆動することが可能であ
る。
The electron source of this embodiment can independently drive each element array by applying an appropriate drive voltage between the wiring electrodes. That is, VE [V] may be applied to the electron-emitting device column from which electrons are desired to be emitted, and 0 [V] may be applied to the device column from which electrons are not to be emitted. For example, if it is desired to drive only the third column, E'1 to E'3
A potential of 0 [V] is applied to each wiring electrode of, and E'4 to E '
A potential of VE [V] is applied to each wiring electrode of No. 6. As a result, a voltage of VE-0 = VE [V] is applied to the third element row, but 0-0 = 0 to other element rows.
0 such as [V] or VE-VE = 0 [V]
A voltage of [V] will be applied. When the second and fifth columns are simultaneously driven, for example, a potential of 0 [V] is applied to the wiring electrodes E′1, E′2, and E′6, and the wiring electrodes E′3 and E′4. And VE [V] for E'5
It is sufficient to apply the potential of As described above, also in this embodiment, it is possible to selectively drive an arbitrary element array.

【0180】なお、上記図19と図20の電子源におい
ては、図示の便宜上から、表面伝導形電子放出素子をX
方向には1列あたり12素子をならべたが、素子数はこ
れに限るものではなく、より多数を配列してもよい。ま
た、Y方向には5列の素子列を並べたが、素子列の数は
これに限るものではなく、より多数を配列してもよい。
In the electron sources shown in FIGS. 19 and 20, the surface conduction electron-emitting device is an X-type electron emission device for convenience of illustration.
Although 12 elements are arranged in one row in the direction, the number of elements is not limited to this, and a larger number may be arranged. Further, although five element rows are arranged in the Y direction, the number of element rows is not limited to this, and a larger number may be arranged.

【0181】次に、上記の電子源を用いた平板型CRT
について例を挙げて説明する。
Next, a flat plate type CRT using the above electron source
This will be described with an example.

【0182】図21は前記図17の電子源を備えた平板
型CRTのパネル構造を示すための図であり、図中VC
はガラス製の真空容器で、その一部であるFPは表示面
側のフェースプレートを示している。フェースプレート
FPの内面には、たとえばITOを材料とする透明電極
が形成され、さらに該透明電極上には赤、緑、青の蛍光
体がモザイクもしくはストライプ状に塗り分けられてい
る。図面の複雑化を避けるため、図中では透明電極と蛍
光体を合わせてPHとして示している。なお、各色の蛍
光体の間にはCRTの分野では公知のブラックマトリク
スもしくはブラックストライプを設けてもよく、また蛍
光体の上に同じく公知のメタルバック層を形成すること
も可能である。前記透明電極は、電子ビームの加速電圧
を印加できるように端子EVを通じて真空容器外と電気
的に接続されている。
FIG. 21 is a view showing a panel structure of a flat plate type CRT equipped with the electron source shown in FIG.
Is a vacuum container made of glass, and FP which is a part of it is a face plate on the display surface side. A transparent electrode made of, for example, ITO is formed on the inner surface of the face plate FP, and red, green, and blue phosphors are applied in a mosaic or stripe pattern on the transparent electrode. In order to avoid complication of the drawing, the transparent electrode and the phosphor are shown together as PH in the drawing. A black matrix or a black stripe known in the field of CRT may be provided between the phosphors of the respective colors, and it is also possible to form a known metal back layer on the phosphors. The transparent electrode is electrically connected to the outside of the vacuum container through a terminal EV so that an acceleration voltage of an electron beam can be applied.

【0183】また、Sは真空容器VCの底面に固定され
た電子源の基板で、前記図19で説明したように表面伝
導形電子放出素子が配列形成されている。なお、本実施
例においては1列あたり200素子が並列に配線された
素子列が200列設けられている。各素子列の2本の配
線電極は、両側のパネル側面に設けられた電極端子Dp
1〜Dp200およびDm1〜Dm200と交互に接続
しており、真空容器外から駆動電気信号が印加できるよ
うになっている。
Further, S is a substrate of an electron source fixed to the bottom surface of the vacuum container VC, on which surface conduction electron-emitting devices are arrayed as described with reference to FIG. In this embodiment, 200 element rows are provided in which 200 elements are wired in parallel per row. The two wiring electrodes of each element row are electrode terminals Dp provided on the side surfaces of the panel on both sides.
1 to Dp200 and Dm1 to Dm200 are alternately connected, and a drive electric signal can be applied from outside the vacuum container.

【0184】また、基板SとフェースプレートFPの中
間には、ストライプ状のグリッド電極GRが設けられて
いる。グリッド電極GRは、前記素子列と直交して(す
なわちY方向に沿って)200本が独立して設けられて
おり、各グリッド電極には電子ビームを通過させるため
の開口Ghが設けられている。開口Ghは各表面伝導形
電子放出素子に対応して1個ずつ円形のものが設けられ
ているが、場合によってはメッシュ状に多数の通過口を
もうけることもある。各グリッド電極は、電子端子G1
〜G200により真空容器外と電気的に接続されてい
る。なお、グリッド電極は表面伝導形電子放出素子から
放出された電子ビームを変調することができるものであ
ればその形状や設置位置は必ずしも図21のようなもの
でなくともよく、たとえば表面伝導形電子放出素子の周
囲や近傍に設けてもよい。
A stripe-shaped grid electrode GR is provided between the substrate S and the face plate FP. 200 grid electrodes GR are provided independently orthogonal to the element row (that is, along the Y direction), and each grid electrode is provided with an opening Gh for passing an electron beam. . Although one circular opening Gh is provided corresponding to each surface conduction electron-emitting device, a large number of passage openings may be formed in a mesh in some cases. Each grid electrode has an electronic terminal G1
~ G200 electrically connects to the outside of the vacuum container. The grid electrode need not necessarily have the shape and installation position shown in FIG. 21 as long as it can modulate the electron beam emitted from the surface conduction electron-emitting device. It may be provided around or in the vicinity of the emitting element.

【0185】本表示パネルでは、表面伝導形電子放出素
子の素子列とグリッド電極で200×200のXYマト
リクスを構成している。したがって、素子列を1列ずつ
順次駆動(走査)していくのと同期してグリッド電極列
に画像1ライン分の変調信号を同時に印加することによ
り、各電子ビームの蛍光体への照射を制御し、画像を1
ラインずつ表示していくものである。
In the present display panel, a 200 × 200 XY matrix is formed by the element columns of the surface conduction electron-emitting devices and the grid electrodes. Therefore, the irradiation of each electron beam to the phosphor is controlled by simultaneously applying the modulation signal for one line of the image to the grid electrode row in synchronization with the sequential driving (scanning) of the element rows one by one. And then the image 1
It is displayed line by line.

【0186】つぎに、図22は前記図21の表示パネル
を駆動するための電気回路をブロック図として示したも
ので、図22中1000は前記図21の表示パネル、1
001は外部から入力する複合画像信号をデコードする
ためのデコード回路、1002はシリ/パラ変換回路、
1003はラインメモリ、1004は変調信号発生回
路、1005はタイミング制御回路、1006は走査信
号発生回路である。表示パネル1000の電極端子は各
々電気回路と接続されており、端子EVは10[kV]
の加速電圧を発生する電圧源HVと、端子G1〜G20
0は変調信号発生回路1004と、端子Dp1〜Dp2
00は走査信号発生回路1006と、端子Dm1〜Dm
200はグランドと接続されている。
Next, FIG. 22 is a block diagram showing an electric circuit for driving the display panel of FIG. 21. In FIG. 22, 1000 is the display panel of FIG.
001 is a decoding circuit for decoding a composite image signal input from the outside, 1002 is a serial / para conversion circuit,
Reference numeral 1003 is a line memory, 1004 is a modulation signal generation circuit, 1005 is a timing control circuit, and 1006 is a scanning signal generation circuit. The electrode terminals of the display panel 1000 are each connected to an electric circuit, and the terminal EV is 10 [kV].
Voltage source HV that generates the acceleration voltage of the terminals and terminals G1 to G20
0 is the modulation signal generation circuit 1004 and terminals Dp1 to Dp2
00 is a scanning signal generation circuit 1006 and terminals Dm1 to Dm
200 is connected to the ground.

【0187】以下、各部の機能を説明する。まず、デコ
ード回路1001は外部から入力するたとえばNTSC
テレビ信号などの複合画像信号をデコードするための回
路で、複合画像信号から輝度信号成分と同期信号成分を
分離して、前者をData信号としてシリ/パラ変換回
路1002に、後者をTsync信号としてタイミング
制御回路1005に出力する。すなわち、デコード回路
1001は、RGBの各色成分ごとの輝度を表示パネル
1000のカラー画素配列に合わせて配列しシリ/パラ
変換回路1002に順次出力する。また、垂直同期信号
と水平同期信号を抽出してタイミング制御回路1005
に出力する。タイミング制御回路1005は前記同期信
号Tsyncを基準にして、各部の動作タイミングを整
合させるための各種タイミング制御信号を発生する。つ
まり、シリ/パラ変換回路1002に対してはTsp
を、ラインメモリ1003に対してはTmryを変調信
号発生回路1004に対してはTmodを走査信号発生
回路1006に対してはTscanを出力する。
The function of each section will be described below. First, the decoding circuit 1001 is input from the outside, for example, NTSC.
A circuit for decoding a composite image signal such as a television signal separates a luminance signal component and a synchronization signal component from the composite image signal, and uses the former as a Data signal for the serial / para conversion circuit 1002 and the latter as a Tsync signal for timing. Output to the control circuit 1005. That is, the decoding circuit 1001 arranges the brightness of each of the RGB color components according to the color pixel arrangement of the display panel 1000, and sequentially outputs the brightness to the serial / para conversion circuit 1002. Further, the timing control circuit 1005 extracts the vertical synchronizing signal and the horizontal synchronizing signal.
Output to. The timing control circuit 1005 generates various timing control signals for matching the operation timings of the respective parts with the synchronization signal Tsync as a reference. That is, for the serial / parallel conversion circuit 1002, Tsp
, Tmody to the line memory 1003, Tmod to the modulation signal generation circuit 1004, and Tscan to the scanning signal generation circuit 1006.

【0188】シリ/パラ変換回路1002は、デコード
回路1001から入力する輝度信号Dataをタイミン
グ制御回路1005より入力されるタイミング信号Ts
pにもとづいて順次サンプリングし、200個の並列信
号I1 〜I200 としてラインメモリ1003に出
力する。タイミング制御回路1005は画像の1ライン
分のデータがシリ/パラ変換された時点でラインメモリ
1003に対して書き込みタイミング制御信号Tmry
を出力する。ラインメモリ1003はTmryを受ける
とI1 〜I200の内容を記憶して、それをI′1
〜I′200として変調信号発生回路1004に出力す
るが、これはラインメモリに次の書き込みタイミング制
御信号Tmryが入力されるまで保持される。
The serial / parallel conversion circuit 1002 receives the luminance signal Data input from the decoding circuit 1001 and the timing signal Ts input from the timing control circuit 1005.
Sequential sampling is performed based on p, and 200 parallel signals I1 to I200 are output to the line memory 1003. The timing control circuit 1005 writes a write timing control signal Tmry to the line memory 1003 at the time when one line of image data is serial / para-converted.
Is output. Upon receiving Tmry, the line memory 1003 stores the contents of I1 to I200 and stores it in I'1.
.About.I'200 is output to the modulation signal generation circuit 1004, which is held until the next write timing control signal Tmry is input to the line memory.

【0189】変調信号発生回路1004はラインメモリ
1003より入力される画像1ライン分の輝度データに
もとづいて、表示パネル1000のグリッド電極に印加
する変調信号を発生させるための回路であり、タイミン
グ制御回路1005の発生するタイミング制御信号Tm
odに合わせて変調信号端子G1 〜G200に同時に
印加する。変調信号は画像の輝度データに応じて電圧の
大きさを変える電圧変調方式を用いるが、輝度データに
応じて電圧パルスの長さを変えるパルス幅変調方式を用
いることも可能である。
The modulation signal generation circuit 1004 is a circuit for generating a modulation signal to be applied to the grid electrodes of the display panel 1000 based on the brightness data for one line of the image input from the line memory 1003, and is a timing control circuit. Timing control signal Tm generated by 1005
The modulation signal terminals G1 to G200 are simultaneously applied in accordance with odd. The modulation signal uses a voltage modulation method that changes the magnitude of the voltage according to the brightness data of the image, but it is also possible to use a pulse width modulation method that changes the length of the voltage pulse according to the brightness data.

【0190】また、走査信号発生回路1006は表示パ
ネル1000の表面伝導形電子放出素子の素子列を適宜
駆動するための電圧パルスを発生するための回路であ
る。タイミング制御回路1005の発生するタイミング
制御信号Tscanに合わせて適宜内部のスイッチング
回路を切り替え、定電圧源DVの発生する表面伝導形電
子放出素子の閾値を上回る適当な駆動電圧VE[V]
か、またはグランドレベル(すなわち0[V])かを選
択して端子Dp1〜Dp200に印加するものである。
Further, the scanning signal generating circuit 1006 is a circuit for generating a voltage pulse for appropriately driving the element array of the surface conduction electron-emitting devices of the display panel 1000. An appropriate drive voltage VE [V] exceeding the threshold of the surface conduction electron-emitting device generated by the constant voltage source DV is switched by appropriately switching the internal switching circuit according to the timing control signal Tscan generated by the timing control circuit 1005.
Or the ground level (that is, 0 [V]) is selected and applied to the terminals Dp1 to Dp200.

【0191】以上の回路により、表示パネル1000に
は図23のタイムチャートに示すタイミングで駆動信号
が印加される。図23中の(a)〜(d)は、走査信号
発生回路1006から表示パネルの端子Dp1〜Dp2
00に印加される信号の一部を示すが、図から分かるよ
う振幅VE[V]の電圧パルスが画像の1ライン表示時
間ごとに順次Dp1、Dp2、Dp3…の順に印加され
てゆく。一方、端子Dm1〜Dm200は常にグランド
レベル(0[V])と接続されているため、上記電圧パ
ルスにより素子列は第1列目から順次駆動され電子ビー
ムが出力されていく。
With the above circuit, the drive signal is applied to the display panel 1000 at the timing shown in the time chart of FIG. 23A to 23D show the terminals Dp1 to Dp2 of the display panel from the scanning signal generating circuit 1006.
A part of the signal applied to the signal 00 is shown. As can be seen from the figure, the voltage pulse of the amplitude VE [V] is applied sequentially in the order of Dp1, Dp2, Dp3, ... For each line display time of the image. On the other hand, since the terminals Dm1 to Dm200 are always connected to the ground level (0 [V]), the element train is sequentially driven from the first train by the voltage pulse and the electron beam is output.

【0192】また、これと同期して変調信号発生回路1
004から同図(f)に点線で示すタイミングで画像の
1ライン分の変調信号が同時に端子G1〜G200に印
加される。走査信号が切り替えられるのと同期して順次
変調信号も切り替えられ、、1画面分の画像が表示され
てゆく。これを連続して繰り返し行うことにより、テレ
ビジョン動画の表示が可能なわけである。
Further, in synchronization with this, the modulation signal generation circuit 1
From 004, the modulation signal for one line of the image is simultaneously applied to the terminals G1 to G200 at the timing shown by the dotted line in FIG. The modulation signal is sequentially switched in synchronization with the switching of the scanning signal, and an image for one screen is displayed. By continuously repeating this, it is possible to display a television moving image.

【0193】以上、図19の電子源を備えた平板型CR
Tについて説明したが、次に前記図20の電子源を備え
た平板型CRTについて図22を用いて説明する。
As described above, the flat plate type CR provided with the electron source shown in FIG.
Having described T, the flat plate type CRT having the electron source shown in FIG. 20 will be described next with reference to FIG.

【0194】図24の平板型CRTは、基本的には前記
図21の平板型CRTの電子源部を、図20のタイプで
置き換えたものであり、電子放出素子列とグリッド電極
で200×200のXYマトリクスを構成している。た
だし、200列の表面伝導形電子放出素子の配線がE1
〜E201の201本の配線電極でなされているため、
真空容器にはEx1〜Ex201の201本の電極端子
が設けられている。
The flat panel CRT of FIG. 24 is basically the flat panel CRT of FIG. 21 in which the electron source portion is replaced by the type of FIG. 20, and the electron emitting element array and the grid electrode are 200 × 200. Of the XY matrix. However, the wiring of the 200-row surface conduction electron-emitting device is E1
Since it is made with 201 wiring electrodes of ~ E201,
The vacuum container is provided with 201 electrode terminals Ex1 to Ex201.

【0195】図25に本表示パネル1008を駆動する
駆動回路を示すが、走査信号発生回路1007を除け
ば、前記G4図の回路と基本的に同様である。走査信号
発生回路1007は、定電圧源DVの発生する表面伝導
形電子放出素子の電子放出閾値を上回る適当な駆動電圧
VE[V]か、またはグランドレベル(0[V])を適
宜選択して表示パネルの端子に出力するが、そのタイミ
ングを図24のタイムチャートに示す。表示パネルは
(a)に示すタイミングで表示動作を行うが、そのため
に電極端子Ex1〜Ex4には走査信号発生回路100
7より(b)〜(e)に示すような駆動信号が印加され
る。そのため、表面伝導形電子放出素子列には(f)〜
(h)のような電圧が印加され、1列ずつ順次駆動され
る。これと同期して、変調信号発生回路1004からは
(i)のようなタイミングで変調信号が出力され、順次
画像が表示されるものである。
FIG. 25 shows a drive circuit for driving the present display panel 1008, which is basically the same as the circuit shown in FIG. G4 except for the scanning signal generating circuit 1007. The scanning signal generation circuit 1007 appropriately selects an appropriate drive voltage VE [V] that exceeds the electron emission threshold of the surface conduction electron-emitting device generated by the constant voltage source DV, or a ground level (0 [V]). Output to the terminals of the display panel, the timing is shown in the time chart of FIG. The display panel performs the display operation at the timing shown in (a), and therefore the scanning signal generating circuit 100 is connected to the electrode terminals Ex1 to Ex4.
7, drive signals as shown in (b) to (e) are applied. Therefore, (f)-
A voltage as shown in (h) is applied and the cells are sequentially driven one by one. In synchronization with this, the modulation signal generation circuit 1004 outputs the modulation signal at the timing as shown in (i), and the images are sequentially displayed.

【0196】本実施例の画像形成装置も、実施例2と同
様な効果を奏するものであった。
The image forming apparatus of this embodiment also has the same effect as that of the second embodiment.

【0197】[0197]

【発明の効果】以上説明した様に、本発明によれば、電
子放出素子の活性化処理工程により、電子放出部の一部
にグラファイト、あるいはアモルファスカーボン、ある
いはそれらの混合物からなる炭素を主成分とする被膜を
制御して被覆したため、従来、真空中で不明であった電
子放出特性の制御が、可能となった。
As described above, according to the present invention, carbon, which is graphite or amorphous carbon or a mixture thereof, is used as a main component in a part of the electron emission portion by the activation process of the electron emission device. Since the above coating was controlled and coated, it was possible to control the electron emission characteristics, which was conventionally unknown in vacuum.

【0198】より好ましくは、該活性化工程は該薄膜に
炭素を主成分とする被膜を被覆する工程、真空中で該電
子放出素子の一対の電極に電圧制御型負性抵抗特性領域
以上の電圧を印加する工程とすることで、該電子放出部
の一部より高電位側に炭素を主成分とする被膜で被覆す
ることで電子放出素子の駆動初期より特性が安定で、か
つ素子電流が小さく、効率の高い電子放出素子の作成が
可能となった。
More preferably, the activation step is a step of coating the thin film with a film containing carbon as a main component, and the pair of electrodes of the electron-emitting device is applied with a voltage higher than a voltage control type negative resistance characteristic region in vacuum. By applying the step of applying, by coating with a film containing carbon as a main component on the higher potential side than a part of the electron-emitting portion, the characteristics are stable from the initial driving of the electron-emitting device and the device current is small. It is now possible to create highly efficient electron-emitting devices.

【0199】さらには、入力信号に応じて電子を放出す
る電子源においては、安定で、かつ、歩どまりよく作成
できるようになった。また、効率の向上により、消費電
力が少なく周辺回路等の負担も軽減され安価な装置が提
供できた。
Furthermore, an electron source that emits electrons in response to an input signal is stable and can be manufactured with high yield. Further, due to the improved efficiency, it is possible to provide an inexpensive device that consumes less power and reduces the burden on peripheral circuits and the like.

【0200】また、画像形成装置においては、安定で制
御された電子放出特性と効率の向上がなされ、例えば蛍
光体を画像形成部材とする画像形成装置においては、低
電流で明るい高品位な画像形成装置、例えばカラーフラ
ットテレビが実現された。
Further, in the image forming apparatus, stable and controlled electron emission characteristics and efficiency are improved. For example, in an image forming apparatus using a phosphor as an image forming member, bright and high quality image formation with low current is formed. Devices, eg color flat televisions, have been realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る基本的な表面伝導型電子放出素子
の構成を示す図。
FIG. 1 is a diagram showing a configuration of a basic surface conduction electron-emitting device according to the present invention.

【図2】本発明に係る表面伝導型電子放出素子の基本的
な製造方法を説明するための図。
FIG. 2 is a diagram for explaining a basic manufacturing method of the surface conduction electron-emitting device according to the present invention.

【図3】本発明に係る表面伝導型電子放出素子の特性評
価に用いる測定評価装置の図。
FIG. 3 is a diagram of a measurement / evaluation apparatus used for characteristic evaluation of the surface conduction electron-emitting device according to the present invention.

【図4】本発明に係るフォ−ミング処理における電圧波
形の一例を示す図。
FIG. 4 is a diagram showing an example of a voltage waveform in a forming process according to the present invention.

【図5】本発明に係る表面伝導型電子放出素子の素子電
流及び放出電流の活性化処理時間に対する依存性を示す
図。
FIG. 5 is a diagram showing the dependence of the device current and the emission current of the surface conduction electron-emitting device according to the present invention on the activation processing time.

【図6】本発明に係る表面伝導型電子放出素子の活性化
処理による形態変化を示す図。
FIG. 6 is a diagram showing a morphological change due to activation treatment of the surface conduction electron-emitting device according to the present invention.

【図7】本発明に係る表面伝導型電子放出素子の放出電
流、素子電流、及び素子電圧の関係の典型例を示す図。
FIG. 7 is a diagram showing a typical example of the relationship between the emission current, the device current, and the device voltage of the surface conduction electron-emitting device according to the present invention.

【図8】本発明に係る電子源基板の構成を示す図。FIG. 8 is a diagram showing a configuration of an electron source substrate according to the present invention.

【図9】本発明に係る画像形成装置の基本構成を示す
図。
FIG. 9 is a diagram showing a basic configuration of an image forming apparatus according to the present invention.

【図10】図10の画像形成装置に用いられる蛍光膜を
示す図。
10 is a diagram showing a fluorescent film used in the image forming apparatus of FIG.

【図11】本発明の実施例1の表面伝導型電子放出素子
を示す図。
FIG. 11 is a diagram showing a surface conduction electron-emitting device according to Example 1 of the present invention.

【図12】本発明に係る基本的な表面伝導型電子放出素
子の別の態様の構成を示す図。
FIG. 12 is a diagram showing the configuration of another aspect of the basic surface conduction electron-emitting device according to the present invention.

【図13】本発明の実施例2の電子源の構成の一部を示
す図。
FIG. 13 is a diagram showing a part of a configuration of an electron source according to a second embodiment of the present invention.

【図14】図13のA−A’断面図。14 is a cross-sectional view taken along the line A-A ′ in FIG.

【図15】本発明の実施例2の電子源の製造工程を説明
するための断面図。
FIG. 15 is a sectional view for explaining a manufacturing process of the electron source according to the second embodiment of the present invention.

【図16】本発明の実施例2の電子源の製造工程を説明
するための断面図。
FIG. 16 is a sectional view for explaining a manufacturing process of the electron source according to the second embodiment of the present invention.

【図17】本発明の実施例3の表示装置を説明するため
の図。
FIG. 17 is a diagram illustrating a display device according to a third embodiment of the present invention.

【図18】従来の表面伝導型電子放出素子の構成を示す
図。
FIG. 18 is a diagram showing a configuration of a conventional surface conduction electron-emitting device.

【図19】本発明の実施例4の画像形成装置の電子源基
板の概略構成図。
FIG. 19 is a schematic configuration diagram of an electron source substrate of an image forming apparatus according to a fourth embodiment of the present invention.

【図20】本発明の実施例4の画像形成装置の電子源基
板の概略構成図。
FIG. 20 is a schematic configuration diagram of an electron source substrate of an image forming apparatus according to a fourth embodiment of the invention.

【図21】本発明の実施例4の画像形成装置におけるパ
ネル構成図。
FIG. 21 is a panel configuration diagram of an image forming apparatus according to a fourth embodiment of the present invention.

【図22】本発明の実施例4の画像形成装置を駆動する
ための電気回路を説明するためのブロック図。
FIG. 22 is a block diagram illustrating an electric circuit for driving the image forming apparatus according to the fourth embodiment of the invention.

【図23】本発明の実施例4の画像形成装置の駆動を説
明するためのタイムチャ−ト図。
FIG. 23 is a time chart for explaining driving of the image forming apparatus according to the fourth embodiment of the invention.

【図24】本発明の実施例4の画像形成装置におけるパ
ネル構成図。
FIG. 24 is a panel configuration diagram of an image forming apparatus according to a fourth embodiment of the present invention.

【図25】本発明の実施例4の画像形成装置を駆動する
ための電気回路を説明するためのブロック図。
FIG. 25 is a block diagram illustrating an electric circuit for driving an image forming apparatus according to a fourth embodiment of the invention.

【図26】本発明の実施例4の画像形成装置の駆動を説
明するためのタイムチャ−ト図。
FIG. 26 is a time chart for explaining driving of the image forming apparatus according to the fourth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 基板 2 電子放出部形成用薄膜 3 電子放出部 4 電子放出部を含む薄膜 5,6 素子電極 84,74 電子放出素子 82,83 配線 85 結線 91 リヤプレ−ト 92 支持枠 93 透明基板 94 蛍光膜 95 メタルバック 96 フェースプレート 98 外囲器 141 層間絶縁層 142 コンタクトホール DESCRIPTION OF SYMBOLS 1 Substrate 2 Electron emission part forming thin film 3 Electron emission part 4 Thin film including electron emission part 5,6 Element electrode 84,74 Electron emission element 82,83 Wiring 85 Connection 91 Rear plate 92 Support frame 93 Transparent substrate 94 Fluorescent film 95 metal back 96 face plate 98 envelope 141 interlayer insulating layer 142 contact hole

───────────────────────────────────────────────────── フロントページの続き (72)発明者 坂野 嘉和 東京都大田区下丸子3丁目30番2号キヤノ ン株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshikazu Sakano 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (30)

【特許請求の範囲】[Claims] 【請求項1】 対向する電極間に、高抵抗部を含む導電
性膜を有する電子放出素子において、該高抵抗部に、炭
素を主成分とする堆積物を有することを特徴とする電子
放出素子。
1. An electron-emitting device having a conductive film including a high-resistance portion between opposed electrodes, wherein the high-resistance portion has a deposit containing carbon as a main component. .
【請求項2】 前記炭素を主成分とする堆積物は、更
に、該高抵抗部の近傍に存在する請求項1に記載の電子
放出素子。
2. The electron emitting device according to claim 1, wherein the deposit containing carbon as a main component is further present in the vicinity of the high resistance portion.
【請求項3】 前記炭素を主成分とする堆積物は、前記
高抵抗部の一部から前記導電性膜上に存在する請求項2
に記載の電子放出素子。
3. The deposit containing carbon as a main component is present on the conductive film from a part of the high resistance portion.
The electron-emitting device according to item 1.
【請求項4】 前記炭素を主成分とする堆積物は、前記
高抵抗部の一部から前記電極のうちの一方の電極側の導
電性膜上に偏在する請求項3に記載の電子放出素子。
4. The electron-emitting device according to claim 3, wherein the deposit containing carbon as a main component is unevenly distributed from a part of the high resistance portion on a conductive film on one electrode side of the electrodes. .
【請求項5】 前記炭素を主成分とする堆積物は、前記
高抵抗部の一部から前記電極のうちの高電位電極側の導
電性膜上に偏在する請求項4に記載の電子放出素子。
5. The electron emitting device according to claim 4, wherein the deposit containing carbon as a main component is unevenly distributed from a part of the high resistance portion on a conductive film on a high potential electrode side of the electrode. .
【請求項6】 前記導電性膜は、導電性微粒子よりなる
請求項1に記載の電子放出素子。
6. The electron-emitting device according to claim 1, wherein the conductive film is made of conductive fine particles.
【請求項7】 前記導電性微粒子は、金属あるいは金属
酸化物である請求項6に記載の電子放出素子。
7. The electron-emitting device according to claim 6, wherein the conductive fine particles are metal or metal oxide.
【請求項8】 前記導電性微粒子は、少なくともその一
部が前記堆積物により被覆されている請求項6に記載の
電子放出素子。
8. The electron-emitting device according to claim 6, wherein at least a part of the conductive fine particles is covered with the deposit.
【請求項9】 前記高抵抗部は、導電性微粒子を有する
請求項1に記載の電子放出素子。
9. The electron emitting device according to claim 1, wherein the high resistance portion includes conductive fine particles.
【請求項10】 前記導電性微粒子は、少なくともその
一部が前記堆積物により被覆されている請求項9に記載
の電子放出素子。
10. The electron-emitting device according to claim 9, wherein at least a part of the conductive fine particles is covered with the deposit.
【請求項11】 前記炭素を主成分とする堆積物は、前
記電極の少なくとも一部を被覆する請求項1に記載の電
子放出素子。
11. The electron-emitting device according to claim 1, wherein the deposit containing carbon as a main component covers at least a part of the electrode.
【請求項12】 前記炭素を主成分とする堆積物は、グ
ラファイト、アモルファスカーボンあるいはそれらの混
合物である請求項1に記載の電子放出素子。
12. The electron-emitting device according to claim 1, wherein the deposit containing carbon as a main component is graphite, amorphous carbon, or a mixture thereof.
【請求項13】 前記電極間に印加される電圧に対して
電子放出電流は、単調増加特性を有する請求項1に記載
の電子放出素子。
13. The electron emission device according to claim 1, wherein the electron emission current has a monotonically increasing characteristic with respect to a voltage applied between the electrodes.
【請求項14】 電子放出素子を有し、入力信号に応じ
て電子を放出する電子源において、前記電子放出素子が
請求項1〜13のいずれかに記載の電子放出素子である
ことを特徴とする電子源。
14. An electron source having an electron-emitting device for emitting electrons according to an input signal, wherein the electron-emitting device is the electron-emitting device according to any one of claims 1 to 13. An electron source to do.
【請求項15】 前記電子放出素子を複数有し、該複数
の電子放出素子の各々の両端を配線にて接続した電子放
出素子の行を複数行と、該電子放出素子より放出される
電子線の変調を行う変調手段とを有する請求項14に記
載の電子源。
15. A plurality of rows of electron-emitting devices having a plurality of the electron-emitting devices, wherein both ends of each of the plurality of electron-emitting devices are connected by wiring, and an electron beam emitted from the electron-emitting devices. 15. The electron source according to claim 14, further comprising a modulation unit that modulates the.
【請求項16】 前記電子放出素子を複数有し、該複数
の電子放出素子が互いに電気的に絶縁されたm本のX方
向配線とn方向配線とに接続し並設されている請求項1
4に記載の電子源。
16. A plurality of the electron-emitting devices are provided, and the plurality of the electron-emitting devices are arranged in parallel so as to be connected to the m X-direction wirings and the n-direction wirings electrically insulated from each other.
4. The electron source according to item 4.
【請求項17】 電子源と画像形成部材とを有し、入力
信号に応じて画像形成する画像形成装置において、前記
電子源が電子放出素子を有し、該電子放出素子が請求項
1〜13のいずれかに記載の電子放出素子であることを
特徴とする画像形成装置。
17. An image forming apparatus having an electron source and an image forming member for forming an image in response to an input signal, wherein the electron source has an electron emitting element, and the electron emitting element is an electron emitting element. An image forming apparatus comprising the electron-emitting device according to any one of 1.
【請求項18】 前記電子源が、前記電子放出素子を複
数有し、該複数の電子放出素子の各々の両端を配線にて
接続した電子放出素子の行を複数行と、該電子放出素子
より放出される電子線の変調を行う変調手段とを有する
電子源である請求項17に記載の画像形成装置。
18. The electron source has a plurality of the electron-emitting devices, and a plurality of rows of the electron-emitting devices in which both ends of each of the plurality of the electron-emitting devices are connected by wiring are provided. The image forming apparatus according to claim 17, wherein the image forming apparatus is an electron source having a modulating unit that modulates an emitted electron beam.
【請求項19】 前記電子源が、前記電子放出素子を複
数有し、該複数の電子放出素子が互いに電気的に絶縁さ
れたm本のX方向配線とn方向配線とに接続し並設され
ている電子源である請求項17に記載の画像形成装置。
19. The electron source has a plurality of the electron-emitting devices, and the plurality of electron-emitting devices are connected in parallel and connected to m X-direction wirings and n-direction wirings electrically insulated from each other. The image forming apparatus according to claim 17, wherein the image forming apparatus is an electron source.
【請求項20】 前記電子源の放出電流及び素子電流
が、素子印加電圧に対して、単調増加特性を有する請求
項17に記載の画像形成装置。
20. The image forming apparatus according to claim 17, wherein the emission current and the device current of the electron source have a monotonically increasing characteristic with respect to the device applied voltage.
【請求項21】 画像形成装置内が、前記炭素を主成分
とする堆積物の新たな堆積を防止する真空度に維持され
ている請求項17に記載の画像形成装置。
21. The image forming apparatus according to claim 17, wherein the inside of the image forming apparatus is maintained at a vacuum degree that prevents new deposition of the deposit containing carbon as a main component.
【請求項22】 対向する電極間に、電子放出部を含む
導電性膜を有する電子放出素子の製造方法において、素
子の活性化工程を有することを特徴とする電子放出素子
の製造方法。
22. A method of manufacturing an electron-emitting device having a conductive film including an electron-emitting portion between opposing electrodes, comprising a step of activating the device.
【請求項23】 前記活性化工程は、前記素子に炭素を
主成分とする堆積物を堆積させる工程である請求項22
に記載の電子放出素子の製造方法。
23. The activation step is a step of depositing a deposit containing carbon as a main component on the device.
A method for manufacturing an electron-emitting device according to item 1.
【請求項24】 前記活性化工程は、真空中にて、電極
間に設けられた導電性膜に電圧を印加する工程を有する
請求項23に記載の電子放出素子の製造方法。
24. The method of manufacturing an electron-emitting device according to claim 23, wherein the activation step includes a step of applying a voltage to a conductive film provided between electrodes in a vacuum.
【請求項25】 前記電圧は、パルス状で印加される請
求項24に記載の電子放出素子の製造方法。
25. The method of manufacturing an electron-emitting device according to claim 24, wherein the voltage is applied in pulses.
【請求項26】 前記電圧は、電圧制御型負性抵抗特性
領域以上の電圧である請求項25に記載の電子放出素子
の製造方法。
26. The method of manufacturing an electron-emitting device according to claim 25, wherein the voltage is equal to or higher than a voltage control type negative resistance characteristic region.
【請求項27】 前記電圧は、電子放出素子の駆動電圧
である請求項26に記載の電子放出素子の製造方法。
27. The method of manufacturing an electron-emitting device according to claim 26, wherein the voltage is a driving voltage of the electron-emitting device.
【請求項28】 更に、フォーミング工程を有する請求
項22に記載の電子放出素子の製造方法。
28. The method of manufacturing an electron-emitting device according to claim 22, further comprising a forming step.
【請求項29】 前記フォーミング工程は、電極間に設
けられた導電性膜に、高抵抗部を形成する工程である請
求項28に記載の電子放出素子の製造方法。
29. The method of manufacturing an electron-emitting device according to claim 28, wherein the forming step is a step of forming a high resistance portion on a conductive film provided between electrodes.
【請求項30】 前記活性化工程は、前記フォーミング
工程の後に行われる請求項22に記載の電子放出素子の
製造方法。
30. The method of manufacturing an electron-emitting device according to claim 22, wherein the activation step is performed after the forming step.
JP14167094A 1993-12-28 1994-06-23 Electron emitting device, method of manufacturing the same, and electron source and image forming apparatus using the electron emitting device Expired - Fee Related JP3416266B2 (en)

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