JPH07234827A - Timer mechanism of packet communication interface device - Google Patents

Abstract

PURPOSE:To improve the speed of packet transfer between a computer and an external device. CONSTITUTION:When data are outputted from a computer 10, a counter circuit 1 measures the interval of generation time between a 1st and a 2nd strobe signal. Consequently, the speed of data transfer to a packet communication interface device 11 by the computer 10 connected to the packet communication interface device 11 can be measured. This measured value is stored in a register 2, and its specific multiple is set as a time-out decision value in a time-out setting circuit 3. Consequently, the time when data are not sent from the computer 10 any more, can be measured by using the decision value corresponding to the data transfer speed of the computer 10. A final packet can, therefore, be sent at a proper period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timer mechanism of a packet communication interface device for connecting a computer and a printer.

[0002]

2. Description of the Related Art Conventionally, packet communication is used when the interface between a computer and an external device such as a printer is wireless. In such packet communication, when one packet of data output from the computer is collected, packet transmission is sequentially performed. In addition, the interface constantly measures the time after receiving the final data from the computer, and if the data for one packet unit is not accumulated even after the lapse of the predetermined time, it is determined that no more data will be sent. Then, the final packet is transmitted. Conventionally, the time-out determination time in this case has been set to a fixed value or has to be changed by a switch or the like before using the interface.

[0003]

However, the above-mentioned conventional techniques have the following problems. That is, when there is a difference in the data transfer rate depending on the computer, the interval between the data becomes long in the computer having the low data transfer rate. Therefore, even though it is not the final packet, it is determined as the final packet by the timeout determination. Therefore, it is considered that the data to be transmitted is complete, and the transmission is started. Therefore, there is a possibility that time loss will occur and the packet transfer rate will decrease. Further, in the case of a computer having a high data transfer rate, it takes more time than necessary from the transmission of the final packet to the determination of the final packet. Therefore, although the high-speed data transfer is possible, there is a possibility that the determination time of the final packet will be a time loss and eventually the transfer speed of the packet will decrease.

[0004]

In order to solve the above-mentioned problems, the timer mechanism of the packet communication interface apparatus of the present invention transmits a packet every time one packet of data output from the computer is accumulated, and the packet is transmitted from the computer. When the data is no longer output, the packet communication interface device that transmits the data accumulated up to that point as the final data is characterized by the following. A counter circuit is provided for measuring the interval between strobe signals output when data is output from the computer. A register for storing the time interval measured by the counter circuit is provided. A time-out setting circuit for multiplying the value stored in the register by a predetermined number and using it as a time-out judgment value for judging the final packet is provided.

[0005]

When the data is output from the computer, the counter circuit measures the generation time interval between the first strobe signal and the second strobe signal. As a result, the data transfer rate of the computer can be measured. The measured value is stored in the register, and a predetermined multiple of the measured value is set in the timeout setting circuit as the timeout determination value. As a result, the time when data is not sent from the computer can be judged using the judgment value according to the data transfer speed of the computer. Therefore, the transfer of the final packet can be performed at an appropriate time.

[0006]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of a timer mechanism of a packet communication interface device of the present invention.
In FIG. 1, a packet communication interface device 11 is connected to the computer 10, and the packet communication interface device 11 includes a counter circuit 1, a register 2, and a timeout setting circuit 3. The counter circuit 1 receives data 1 from the computer 10.
The interval of the strobe signal output at the time of outputting 2 is measured. The register 2 also stores the time interval measured by the counter circuit 1. Timeout setting circuit 3
Is used as a timeout judgment value for judging the final packet by multiplying the value stored in the register 2 by a predetermined number. Details of each unit will be described later with reference to FIGS. 3, 4, and 5.

The computer 10 stores the data 12 in the packet 13 and stores it in the packet communication interface device 14
To the printer 15 through. That is, the packet communication interface device 11 receives a packet 13 every time one packet of the data 12 output from the computer 10 is collected.
Is sent. Also, data 1 from the computer 10
When 2 is not output, the data accumulated up to that point is transmitted as the final data. The packet communication procedure in this packet communication interface device 11 is shown in the flowchart of FIG.

First, in step S1, it is determined whether or not data is output from the computer 10, and if data is output, the data is stored in step S2.
At this time, in step S3, the timer value for determining the timeout of the data output from the computer 10 is reset. Then, in step S4, it is determined whether or not one packet of data is accumulated. When one packet of data is accumulated, the one packet is transmitted in step S5, and the process returns to step S1. On the other hand, when the data for one packet is not stored, the process returns to step S1 and waits for the output of data from the computer 10. If no data is output from the computer 10 even after the lapse of a predetermined time in step S1 and it is determined that there is a timeout in step S6, the data currently stored is less than one packet in step S7. If there is, send it as the final packet.

FIG. 3 is a circuit diagram showing a configuration of a counter clock generation circuit for controlling the counter circuit 1 shown in FIG. 1, FIG. 4 is a configuration of the counter circuit 1 of FIG. 1, and FIG.
3 is a circuit diagram showing a configuration of register 2 of FIG. In FIG. 3, the strobe signal STB '("'" indicates that the signal is low active. The same applies hereinafter) of the centronics interface signal is applied to the D-flip-flops A and B.
C (hereinafter, referred to as "FF-A, FF-B, FF-C") is connected to each clock terminal to generate an electromotive force (+ 5V).
Is connected to the D terminals of FF-A and FF-D. And F
Connect the output Q of F-A to the D terminal of FF-B, and
Is connected to the D terminal of FF-C, and the inverted output Q'of FF-C is connected to the falling edge detection circuit 30.

Further, the 2-input AND circuit 31 is connected to the output of the falling edge detection circuit 30 and the main reset signal M.
RST 'is input and the output of the 2-input AND circuit 31 is FF
Connect to reset terminals of -A, FF-B, FF-C, and FF-D. On the other hand, the inverted output Q'of FF-B, the inverted output Q'of FF-D and CLK1 are connected to the 3-input NAND circuit 32. Then, as shown in FIG. 4, the 3-input NAND circuit 3
The output of 2 is connected to the input terminal CPUP of 74LS193-A. In FIG. 4, the output terminal TCUP 'of the 74LS193-A is replaced by the input terminal CPUP of the 74LS193-B.
Connect to. In addition, 74LS193-A, 74LS19
3-B input terminals CPdown ', P0-P3,
PL 'is connected to an electromotive force (+ 5V).

Further, counters 74LS193-A, 74
The respective output terminals Q0 to Q3 of the LS193-B are the input terminals 1A1 to 1A1 of the register 74LS244 shown in FIG.
A4, 2A1-2A4 are connected. Further, the reset signal RST 'is connected to the inverters B and C, and the output thereof is connected to the clear terminals Clear of the counters 74LS193-A and 74LS193-B. Where clear terminal Clear
Is grounded via a pull-down resistor. On the other hand, FIG.
Control terminals G1 ', G of the register 74LS244 shown in FIG.
2'is a read signal CountR from a main controller (not shown) of the packet communication interface device 11.
Enter ead '. The control terminals G1 'and G2' are
Connect a pull-up resistor.

Next, the operation of the above-mentioned device will be described. FIG. 6 is a time chart for explaining the operation of the timer mechanism of the packet communication interface device 11 of the present invention. In FIG. 6B, when the first strobe signal is transmitted, the output Q and FF-A of FF-A in FIG.
Both outputs Q of D become "H". At this time, two inputs other than CLK1 of the three-input NAND circuit 32 are "H" (FF-
Since the inverted output Q'of B is the initial value "H"), CLK1 is output to CLK2 via the 3-input NAND circuit 32.
The output of CLK2 causes the counter 74LS193-
A, 74LS193-B starts counting.

Next, in FIG. 6 (b), the second strobe signal is transmitted, so that in FIG.
The output Q of FF-B becomes "H" and the inverted output Q'becomes "L". Since the inverted output of FF-B becomes "L", the output of CLK2 from the 3-input NAND circuit 32 disappears, and the counter 74LS193- in FIG.
A, 74LS193-B stops counting. Therefore,
As shown in FIG. 6C, the first strobe signal and 2
Only between the strobe signal for the first time and FIG.
Is input to the counter circuit of FIG. Therefore, as shown in FIG. 6D, after the second strobe signal is transmitted, the control signal CountRead ′ for reading the value of the counter circuit of FIG. 4 into the data bus is transmitted to display the count data. Read into register 2 of 5.

Next, when the third strobe signal is transmitted, the inverted output of FF-C becomes "L", and when the falling edge detection circuit 30 detects this inverted output Q ', a pulse is generated. The pulse is generated and output as a reset signal RST ', and as shown in FIG.
F-A, FF-B, FF-C, FF-D, 74LS19
3-A and 74LS193-B are reset. After the count data in the register 2 of FIG. 5 is read by software, a time corresponding to a value that is a predetermined number times, for example, 10 times, the count data is set as the determination value of the final packet determination timer.

As a result, in the processing procedure of FIG. 2, a determination value is set according to the time intervals between the first and second strobe signal generations. Therefore, when the data transfer rate of the computer 10 is low, in the past, as shown in FIG. 7A, it was determined that a time-out occurred before the next data transfer was performed. However, such a situation does not occur, and as shown in FIG. 7B, the timeout is always determined after the data transfer is completed. Further, when the data transfer speed of the computer 10 is high, conventionally, it is determined that the time-out occurs only after the same fixed time as shown in FIG. 7A has elapsed even after the data transfer is completed, as shown in FIG. 8A. However, in the present invention, such a situation does not occur, and as shown in FIG. 8B, a timeout occurs after a predetermined time corresponding to the data transfer rate after the data transfer is completed. Judgment is made. As described above, the packet transfer time can be shortened regardless of whether the data transfer speed of the computer 10 is slow or fast.

The present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made. For example, the interface is not limited to the Centronics specification, but may be other specifications such as RS232C. Further, the packet is not limited to being transmitted to the printer 15, but may be transmitted to another external device such as a disk device.

[0017]

As described above, according to the timer mechanism of the packet communication interface device of the present invention, in the packet communication, the setting of the timer for judging the final packet is automatically changed according to the transfer rate of the computer. Since this is done, it is possible to determine the final packet that matches the data transfer rate of the computer, and it is possible to improve the packet transfer rate. That is, the final packet determination time can be shortened regardless of whether the computer has a low data transfer rate or a high data transfer rate, and therefore the time loss can be reduced and the packet transfer rate can be prevented from becoming slow. .

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a timer mechanism of a packet communication interface device of the present invention.

FIG. 2 is a flowchart illustrating a packet communication procedure of the device of FIG.

FIG. 3 is a circuit diagram showing a configuration of a counter clock generation circuit of FIG.

FIG. 4 is a circuit diagram showing a configuration of a counter circuit shown in FIG.

5 is a circuit diagram showing a configuration of a register shown in FIG.

FIG. 6 is a time chart explaining the operation of the timer mechanism of the present invention.

FIG. 7 is a time chart explaining the operation when the data transfer rate of the computer is low.

FIG. 8 is a time chart explaining the operation when the data transfer rate of the computer is high.

[Explanation of symbols]

 1 counter circuit 2 register 3 timeout setting circuit 10 computer 11 packet communication interface device

Claims (2)

[Claims] 1. Data output from a computer is 1
Packets are sent every time a packet is accumulated, and when the computer stops outputting data, the packet communication interface device that transmits the data accumulated up to that point as the final data is output when the computer outputs the data. Counter circuit that measures the strobe signal interval, a register that stores the time interval measured by the counter circuit, and the value stored in the register multiplied by a specified number to determine the timeout judgment value for the final packet judgment. A timer mechanism for a packet communication interface device, comprising a time-out setting circuit used as 2. The timer mechanism of a packet communication interface apparatus according to claim 1, wherein the counter circuit counts clocks generated by the counter clock generation circuit within the strobe signal generation interval.