JPH07234737A - Sync formation circuit - Google Patents

Abstract

PURPOSE: To provide a sink forming circuit which can form a sink for multiple carriers even in the case where a restriction is given when CMOS technology is used. CONSTITUTION: The first electrodes of first and second transistors Q1 and Q2 having the same polarity are connected to either first or second feed line 1 or 2. The second electrode of the first transistor Q1 is connected to the other feed line 2 through a reference current source 3 supplying reference current Ir . The second electrode of the second transistor is connected to the other feed line 2 through a load RL. The multiple carriers are made to flow in a direction detached from the other feed line 2 during an operation. Negative feedback is formed by using an amplifier means 4 and the voltage of a positive input part and that of a negative input part in the amplifier means are made equal. Current I0 in a relation which is previously decided for reference current Ir is supplied to a load.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for forming a sink for majority charge carriers, that is, a current source when the majority charge carriers are electrons, and a current sink when the majority charge carriers are holes.

[0002]

2. Description of the Prior Art In the integrated circuit art, constant (ie, high output impedance) current sources and current sinks are important circuit elements. In general, current sinks are relatively easy to implement by using an n-type device such as a single n-channel enhancement mode MOS transistor or a cascode n-channel MOS transistor,
The current source is also a p-channel enhancement mode MO.
It can be realized by using a p-type device such as an S transistor. However, there are some forms of integrated circuits in which it is technically difficult to provide both n-channel and p-channel enhancement mode MOS transistors, thus forming a current source when only n-channel devices are available. And also difficult to form a current sink if only p-channel devices are available. This is the case, for example, of circuits formed by depositing an amorphous or polycrystalline semiconductor material on an insulating substrate such as glass or plastic. The reason is that currently manufactured p-channel enhancement mode thin film transistors (TFTs) have unacceptably high threshold voltages in addition to extremely poor charge mobility characteristics. Similarly, in the technical field of smart power integrated circuits or power integrated circuits in which a vertical power device is integrated with a control circuit or a logic circuit, the control circuit or the logic circuit is integrated on the same substrate or semiconductor as the power semiconductor device. The requirement that the required p-type device, such as a vertical power device, form an npn bipolar transistor or a p-channel enhancement mote MOS transistor that is an n-channel MOSFET, without resorting to complex processing techniques, Alternatively, it may make it very difficult for a usable n-type device, for example a power device, to form an n-channel enhancement mode MOS transistor which is a pnp bipolar transistor or a p-channel vertical power MOSFET.

Current n-channel TFT digital circuits, which require current sources or load transistors, for example for use in logic gates or shift registers, generally employ a circuit of the form shown in FIG. As is clear from FIG.
The above circuit has an n-channel TFT N1, whose drain electrode is coupled to the first voltage supply line 1, its gate electrode is coupled to the gate voltage supply line G, and whose source electrode is to supply current. It is coupled to the second voltage supply line 2 via RL. The device RL shown in FIG. 1 can be any suitable component of the circuit to be supplied with current. For example, the device RL can be another n-channel enhancement mode TFT as shown, whose main current path, ie the path between its source and drain electrodes, is coupled in series with the source electrode of the TFT N1, The control electrode of the other n-channel enhancement mode TFT is coupled to the input terminal I for the input voltage, and the two TFTs form an inverter circuit for generating an inverted voltage at the output terminal O.

[0004]

However, such a configuration is not suitable when a constant current source is required. The reason is that the gate voltage of the TFT N1 is naturally held at the constant potential supplied to the gate voltage supply line G,
Any change in the output voltage V _{0 at} the output terminal O at the connection between the source electrode of the FT N1 and the device RL is T
This is because the gate-source voltage of FT N1 is changed. If the transconductance of the TFT N1 is g _m and the current flowing through the device RL is i ₀ , the output impedance is

[Equation 1] And can typically be on the order of 10 ⁵ to 10 ⁶ ohms. Furthermore, the output impedance R _out depends on the output voltage V ₀ (ie the source voltage of the TFT N1). The reason is that transconductance is a function of drain current. Moreover, the dependence of the output current i ₀ on the output voltage V ₀ means that this circuit cannot be used to provide a precise current source. Furthermore, the gain of the circuit having such a configuration is

[Equation 2] Given by. Where W and L respectively indicate the width and length of the conducting channel, and thus for high gains,
Needless to say, it is necessary to make the TFT N1 extremely small or the TFT RL extremely large, which may cause a capacitance problem, and the area occupied by the circuit becomes large.

It is an object of the present invention to use complementary techniques such as CMO.
Can be configured under limited circumstances when using S technology,
It is to provide a circuit for obtaining a sink for majority charge carriers.

[0006]

Means and Actions for Solving the Problems First of the Invention
In terms of, a circuit forming a sink for majority charge carriers, the first and second feed lines and first and second of the same polarity each having a control electrode and a first and a second main electrode. Two transistors and an amplifying means having a main and a negative input and an output, the second transistor having a dimension of a predetermined ratio with respect to the corresponding dimension of the first transistor, First of the second transistor
The main electrode is coupled to one of the first and second power supply lines, and the main electrode of the first transistor is connected to the other power supply line via a reference current source that supplies a reference current through the first transistor. And a second main electrode of the second transistor is arranged to be coupled to the other feed line via a load, and during operation of the circuit the majority carrier is passed through the first and second transistors to the other Flowing away from the feed line, the negative input of the amplifying means is coupled to the second main electrode of the first transistor, the positive input is coupled to the second main electrode of the second transistor, and the output Section is coupled to the control electrodes of the first and second transistors to form a negative feedback equalizing the voltage at the positive input and the voltage at the negative input of the amplification means, the second transistor being the second transistor.
A sink forming circuit configured to supply a load coupled between a second main electrode of a transistor and the other power supply line with a current having a predetermined ratio with respect to the reference current.

With the circuit according to the invention, the output current has a predetermined ratio to the reference current due to the negative feedback, ie the circuit acts like a current mirror,
Moreover, the output impedance is increased by a factor determined by the gain of the amplification means (compared to the known circuit described above). Therefore, this circuit provides a constant output current with a very high output impedance. Also, the present invention allows the formation of sinks for multi-stage charge carriers without the use of complementary MOS or bipolar technology. For example, according to the present invention, an n-channel enhancement MO
The current source can be formed even when only the S transistor is used. The first and second transistors are bipolar transistors or enhancement type M
A normally-off type device such as an OS transistor which does not conduct unless an appropriate voltage is applied between the first main electrode and the second main electrode and an appropriate voltage is applied to the control electrode.

In the preferred embodiment, the first and second transistors are n-channel enhancement MOS transistors and the source electrode of the first n-channel MOS transistor is coupled to the negative input of the amplifying means to provide a second n-channel The source electrode of the MOS transistor is coupled to the positive input of the amplification means. In this case, according to the present invention, the current source can be formed using only the n-channel enhancement type MOS transistor. Of course, if desired, a bipolar n-type device or npn bipolar transistor can be used in place of the n-channel enhancement type MOS transistor.

Here, "n type" or "n type device" means
Npn where majority charge carriers are electrons during conduction of the device
A device such as a bipolar transistor or an n-channel MOS transistor, "P-type" or "P-type device"
Is p where the majority charge carriers are holes during device conduction.
It means an np bipolar transistor or a P-channel MOS transistor.

The first and second transistors can be similar to each other, but preferably the first and second transistors.
Transistors are matched to each other so that the output current is equal to the reference current. Here, "matching" means that the first and second transistors are manufactured in the same process and have the same size, and thus have the same operation characteristics as much as possible and the same current at a predetermined voltage. Means to flush. On the other hand, “similar” means that the first and second transistors are manufactured in the same process and have predetermined ratio dimensions that are not equal to each other, and 2 means that the current carried by the transistor is in a predetermined ratio. For MOS or TFT transistors, the important dimension is the channel length L
And the channel width W.

The amplifying means comprises an inverting circuit having an input transistor circuit coupled to the positive input and the negative input, and a load device having a photo-sensing element illuminated during operation of the inverting circuit. be able to.

For example, the amplifying means comprises third, fourth and fifth transistors, the nuclear transistor comprises first and second main electrodes and a control electrode, the control electrode of the third transistor being the positive input. The control electrode of the fourth transistor is coupled to the negative input, the control electrode of the fifth transistor is coupled to the bias voltage source, and the third and fifth transistors are coupled to the first feed line and the first feed line. It is also possible to connect the fifth transistor in series with the second power supply line, to couple the fifth transistor in series to the fourth transistor and the photo-sensing element, and to couple the photo-sensing element to the output of the amplification means. With this configuration, it is possible to configure a high output impedance amplifying means without using a complementary transistor.

As an example, the photo-sensing diode may consist of a photo-sensing non-linear resistance device coupled between the first main electrode of the fourth transistor and the first feed line. In this circuit, the photocurrent produced by illuminating the light-sensing element can be made independent of the inverting bias voltage across the light-sensing diode, which results in the amplifying means having a very high output impedance. . The gain of the amplification means is determined by the output impedance and can be about 30.

In a second embodiment, a photo-sensing element is coupled to at least one of the second main electrode and the control electrode of another transistor in series with the fourth transistor.
It can be configured to have a plurality of light sensing devices so that when light is incident, a voltage is generated between the second main electrode and the control electrode of the another transistor. In this embodiment, the gate-source voltage of the other transistor is not a function of the output voltage, so a higher gain would result in the amplifying means taking on a more increased output impedance. During operation of this circuit, illumination of the light sensitive element produces a voltage across the light sensitive element, which is equal to the forward bias required to provide a forward current equal to the photocurrent.

In the second embodiment, the photo-sensing element is formed of a series of photo-sensing elements, which generally turns on another transistor when the photo-sensing element is illuminated, depending on the characteristics of the photo-sensing diode. Sufficient voltage can be applied. In this second embodiment, the current flowing through the inverter circuit formed by the fourth transistor, the photo-sensing element and another transistor, ie the current charging the load capacitance, is photo-sensing when the output voltage of this inverter circuit increases. It is not determined by the current flowing through the device. Therefore, in the second embodiment, the light coupled by increasing the channel length to channel width ratio W / L of another transistor or between the control electrode and the first main electrode of another transistor or load transistor. Larger capacitive loads can be driven at the same predetermined speed by adding photosensitive elements to the array of sensing elements. On the other hand, it is not necessary to increase the size or surface area of the light-sensing diode. The reason for this is that the photosensitive diode does not produce an output current.

The circuit according to the invention can be used in any situation where a constant current is required, for example a switched current circuit, in particular a smart power device or an intelligent power device or storage elements arranged in rows and columns. Can be used when it is difficult to use complementary transistors such as a thin film device such as a control circuit for controlling access of storage elements when individually accessing a two-dimensional array by row conductors and column conductors.

The present invention comprises at least one photo-sensing element, a sink forming circuit according to any one of claims 1 to 7, first and second main electrodes and an insulated gate electrode. A second transistor connected in series with the first transistor between the first power supply line and the second power supply line to form a reference current source, and the first power supply line and the second power supply line. An additional transistor coupled in series to the second transistor between the two to provide an output to the connection between the second transistor and said another transistor to the load of the circuit, and switching means. The switching means couples the light-sensing element between a power supply line and a control electrode of the another transistor to cause the another transistor to act as a light-sensing element when the light-sensing element is not illuminated. And generating a first current representative of the first signal generated by said photosensing element and coupling said photosensing element between the feed line and the control electrode of said additional transistor. A third current which, when illuminated, produces a second current which is representative of the second signal produced by the light sensitive element and which is representative of the difference between the first and second signals which should occur at the output. There is provided an image sensor configured to generate a current.

Although the circuit according to the invention can be manufactured using bulk semiconductor technology, the invention provides that the light-sensitive element is for example a pin diode, a Schottky diode or a metal-insulator-metal (M- I-M) devices, which have at least one thin film diode and can be used in thin film technology where one transistor or each transistor is composed of n-channel thin film transistors.

Of course, in an attempt to improve the accuracy of a conventional current mirror circuit, a diode connected first transistor and a second transistor have a control gate coupled to each other, and a current flowing through the first transistor is converted into a second current. It is known to cause the transistor to reflect through the amplifying means to the diode feedback path to reduce the input impedance and increase the output impedance. As is well known, the diode connection means to couple a gate and a drain in the case of a MOS transistor, and to couple a collector and a base in the case of a bipolar transistor. In such a circuit, for example, US Pat.
2551 specification or European Patent Application Publication No. 523266.
As shown in the specification, a diode coupling is inserted in the path between the positive input and the output of the amplifying means, and the negative input of the amplifying means is connected to the drain or collector of the second transistor. ing. On the other hand, this circuit cannot form a sink or supply a majority carrier,
That is, a current source cannot be formed in the case of n channels. Therefore, in this circuit, only one conductivity type transistor can be used and a high gain inverter cannot be formed. The reason for this is that an active load is required in this situation, and the active load coupled to the output of the circuit described in U.S. Pat. No. 4,642,551 or EP 523266 is always the source (emitter). This is because it is not possible to achieve a desired high gain by having a floor configuration.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The drawings are not drawn to scale, and the same components will be denoted by the same reference symbols throughout the drawings. With reference to FIG. 2, FIG. 3 or FIG. 4, circuits 10, 10a, 10b forming a sink for a majority carrier are shown. In each of the illustrated embodiments, the circuit forming the current source comprises first and second feed lines and first and second transistors Q1 and Q2 of the same polarity. Each transistor has control electrodes g1 and g2 and first and second main electrodes d1 and s1 and d2 and s2, the second transistor Q2 being predetermined relative to the corresponding dimensions of the first transistor Q1. Has a ratio dimension. First and second
The first electrodes d1 and d2 of the transistors Q1 and Q2 of the first transistor Q1 are coupled to one of the first and second power supply lines 1 and 2, and the second electrode s1 of the first transistor Q1 is connected to the first transistor Q1. Via the reference current source 3 which supplies the reference current I _r via the.
The second electrode s2 of the second transistor is coupled to the second feed line 2 via the load RL to supply majority carriers to the second feed via the first and second transistors Q1 and Q2 during circuit operation. Run away from the line. Amplifying means 4
Has positive and negative inputs 4a and 4b and an output 4c, the negative input 4b being coupled to the second main electrode s1 of the first transistor Q1 and the positive input 4a being the second transistor The output part 4c is coupled to the second main electrode s2 of Q2, and the output part 4c is a control electrode g1 of the first and second transistors Q1 and Q2.
And g2 to form a negative feedback. This allows the positive and negative inputs 4a and 4b of the amplifying means 4 during circuit operation.
Are equalized, and the load RL coupled between the second main electrode s2 of the second transistor Q2 and the second feed line 2 has a predetermined proportional relationship with respect to the reference current I _r . Supply a current I _o at

In these circuits 10, 10a and 10b, the output current I _o is set to a predetermined ratio with respect to the reference current I _r by negative feedback. As a result, these circuits behave like current mirror circuits and the output impedance is increased by a factor defined by the amplifying means 4. Therefore, a sink for majority carriers can be formed without using complementary MOS or bipolar technology. As a result, for example, the current source can be formed only in the portion where the n-channel enhancement MOS transistor is required. The first and second transistors are normally-off type devices, i.e. bipolar transistors or enhancement type MOSs that do not conduct until a suitable voltage is applied to the control electrode and the first and second main electrodes.
Use as a transistor.

Referring to FIG. 2, in this embodiment, the first and second transistors have channel regions composed of a suitable semiconductor material such as amorphous silicon or polycrystalline silicon, eg, coplanar TFT, inverted TF.
It consists of a suitable type of n-channel thin film transistor (TFT) such as a T or inverted staggered TFT. Since the structure of these TFTs is well known to those skilled in the art, detailed description will be omitted.

Drain charge of the first and second transistors
The poles d1 and d2 are coupled to the first feed line 1 and the gate
The electrodes g1 and g2 are both coupled to the output section 4c of the amplification means 4.
To do. The source electrode s1 of the first TFT Q1 is an appropriate reference
It is coupled to the second feed line 2 via a current source 3. this
The reference current source can consist of any suitable current source.
Wear. Therefore, for example, this reference power source is a normal individual constant voltage
Known using source (eg, external precision resistor)
Method, or circuit 10 is part of a larger circuit
To form as another circuit part of this circuit
be able to. In some applications, two or more
Place the circuit 10 in the same larger circuit and
The reference current for one circuit of path 10 is applied to the other circuit 10
Can be formed by the output current of Second tran
The source electrode s2 of the transistor Q2 is the load impedance RL.
Via the second power feed line. This load is a constant current
I _oCan be any device or circuit desired
It

Source electrode s1 of the first transistor Q1
Is coupled to the negative input 4b of the amplifying means 4, and the source electrode of the second transistor Q2 is also the positive input 4a of the amplifying means 4.
Bind to. The output of the amplification means is coupled to the gate electrodes g1 and g2 of the first and second transistors Q1 and Q2, respectively.

The amplifying means 4 is of a suitable type with sufficient gain, an example of which will be described with reference to FIGS.

First and second transistors Q1 and Q2
Respectively constitute the reference device and the output device of the circuit, which in this example are matched such that they have the same channel length and channel width and thus the same current in the circuit of FIG.

During operation of the circuit of FIG. 2, the reference current source 3 acts to pass the reference current I _r through the reference transistor Q1 having the gate voltage V _g and the source voltage V _sr . Due to the negative feedback formed by the amplification means 4, the amplification means 4
The voltage of the positive and negative input portions 4a and 4b are equal to each other, first and second transistor becomes the same operating conditions, thus the source voltage V _sr and V _so these transistors are equal to each other. Therefore a current I _o equal to I _r
Flows to the load RL through the second transistor, that is, the output transistor Q2. Since the change of the output voltage, that is, the change of the source voltage of the output transistor Q2 occurs in the source voltage V _sr of the reference transistor, that is, the first transistor by the action of the amplifying means 4, the reference transistor Q1 and the output transistor Q2 have the same operating condition. It will be. Therefore, the output current I _o is always the same as the reference current I _r, and this circuit acts as a current mirror circuit.

Furthermore, the output impedance of this circuit 10 increases by a factor equal to the gain of the amplification means. This output impedance can be calculated by small signal analysis. Therefore, the gate voltages of the first and second transistors are given by the following equation.

[0029]

[Equation 3] Here, A _o is a high open loop gain of the amplification means 4, and Δ represents a minute change amount. Output impedance R
_out is given by the following formula.

[0030]

[Equation 4] The output current I _o is determined by the transconductance g _m of the output transistor Q2, and therefore the gate-source voltage is given by the following equation.

[0031]

[Equation 5] From the above equation, the following equation is obtained.

[0032]

[Equation 6]

The reference current I _r is defined by the constant current source 3 and is therefore constant. That is, the gate-source voltage of the reference transistor, that is, the first transistor does not change, and ΔV _g = ΔV _sr . As a result, the following equation is established.

[0034]

[Equation 7]

The voltage V _g is the voltage of the output section 4c of the amplifying means 4, and the output impedance is given by the following equation.

[0036]

[Equation 8] Expression (6) is expressed by the following expression for a large amplification gain.

[0037]

[Equation 9]

Therefore, as described above, the circuit 10 acts as a high output impedance current source that reflects a predetermined input current I _r .

FIGS. 3 and 4 are circuit diagrams showing the preferred embodiments 10a and 10b of the circuit 10 shown in FIG. 2, in which the amplifying means 4'and 4 "(FIGS. 3 and 4) are shown inside broken lines). The suitable form of is shown.

In the embodiment shown in FIGS. 3 and 4, the amplifying means 4 is in the form of a long-tiled pair using the inverter circuit 5 as an example, the inverter circuit includes an input transistor circuit and a load device, and the load is the inverter circuit. It is composed of a photo-sensing element that receives light during operation.
This inverter circuit is disclosed in European patent application No. 94201881.3 filed by the present applicant. As shown in FIGS. 3 and 4, the input transistor circuit has third, fourth and fifth transistors Q3, Q4 and Q5,
Each transistor has first and second main electrodes and a control electrode. The control electrode g3 of the third transistor is coupled to the positive input 4a of the amplification means 4 and the control electrode g4 of the fourth transistor is coupled to the negative input 4b of the amplification means 4. The third and fifth transistors Q3 and Q5 are coupled in series between the first and second feed lines 1 and 2, and
Transistor is coupled in series with the fourth transistor and the photodiode D1. The photodiode D1 is also coupled to the output 4c of the amplification means 4. In the embodiment shown in FIG. 3, transistors Q3 to Q5 are all n-channel enhancement TFTs. The drain electrode d3 of the third transistor Q3 is coupled to the first power supply line 1, and the source electrode s3 is connected to the source electrode s4 of the fourth transistor and the drain electrode d5 of the fifth transistor. The source electrode s5 of the fifth transistor is coupled to the second power supply line 2, and the drain electrode d4 of the fourth transistor Q4 is coupled to the anode of the photodiode D1. The cathode of the photodiode D1 is coupled to the first power supply line 1.

The control electrodes g3 and g4 of the third and fourth transistors Q3 and Q4 constitute the positive and negative input parts 4a and 4b of the amplifying means 4 ', the anode of the photodiode D1 and the drain electrode of the fourth transistor Q4. The connection to d4 is coupled to the output 4c of the amplification means 4. The bias voltage _Vb is applied to the control electrode g5 of the fifth transistor. The bias voltage V _b can be derived in any suitable way, for example using a suitable voltage divider from the voltage between the first and second feed lines. This voltage divider is a diode-connected n-channel TFT
The column is provided with a tap-off connection to the control gate of the fifth TFT Q5 to supply the required bias voltage. The use of the diode-connected n-channel TFT has an advantage that the TFTs Q1 to Q5 can be manufactured by using the same process with a slight modification of the metal processing mask.

The inverter circuit 5 is a photodiode D1.
Is inactive until illuminated. When the photodiode D1 receives light, a photocurrent that does not depend on the reverse bias of the photodiode D1 is generated. Therefore, the photodiode D1 generates a photocurrent that does not depend on the applied voltage, and the photodiode D1 has an extremely high impedance, and the gain of the inverter circuit 5 is determined by the output impedance of the transistor Q3.

The amplifying means 4'shown in FIG. 3 generates a high output giving a gain of about 30. The actual value of this gain is
Performance of fourth transistor Q4 and photodiode D1
It cannot be well defined because it is affected by many factors including the characteristics of On the other hand, in this example, a higher gain is required for the amplifier, but it is not necessary to well define the gain of the amplifier.

The amplifying means 4 "shown in FIG. 4 is likewise in the form of a long-tiled pair, but replaces the light-sensing element or diode D1 with a load which is another transistor, which is an n-channel enhancement. Shown as TFT Q6 The drain electrode d6 of another TFT Q6 is coupled to the first power supply line 1, and the source electrode s6 is coupled to the drain electrode d4 of the fourth transistor Q4.

A photo-sensing nonlinear resistance device D2, in this example a column of photo-responsive P-i-n diodes, is connected to the control (gate) electrode g6 of the transistor Q6 and the first main electrode (source electrode) s.
6, each light-sensing diode D2 is coupled to the cathode of the adjacent diode, the anode of the first diode in the diode string is coupled to the control electrode g6, and the cathode of the diode in the last stage of the diode string is connected to the load transistor Q6. It is so coupled that it is coupled to the output 4c of the amplifier stage 4 "'" via the first main electrode and the connection J3.

In this example, during operation of the inverter circuit 5 ',
The gate-source voltage of the load transistor Q6 is applied by the photo-sensing diode array when light is incident on the photo-sensing diode D2. Since the gate-source voltage of the transistor Q6 is not a function of the output voltage of the inverter circuit,
The output voltage of this inverter circuit increases.

The small voltage drop across each photoresponsive diode D2 is equal to the forward bias required to provide a forward current equal to the magnitude of the photocurrent. The number of photo-sensing diodes D2 required depends on the characteristics of this photo-sensing diode and the required characteristics of the inverter circuit (which may be, for example, one), but is sufficient to turn on the load transistor Q6. It must provide a gate-source voltage.

If a larger gain is required, the amplifying means 4'and 4 "shown in FIGS. 3 and 4 can be modified by adding an inverter output stage to the Ronda Tiller pair. 5 '
It can be configured with one of the circuits.

Of course, any other suitable amplification means can be used. On the other hand, the embodiment shown in FIG. 3 and FIG.
There is an advantage that high gain and high output impedance can be obtained by using only transistors having the same polarity as the transistors Q1 and Q2, and this advantage is extremely beneficial in this example. The reason for this is that P-channel TFTs with acceptable threshold voltage and operating characteristics are not currently available.

The current source circuit according to the invention can be used in any situation where a constant current source has to be constructed. In particular, in the current source circuit of the present invention, complementary transistors cannot be used, and for example, in the situation where the thin film circuits described above or the processing technology used for configuring the smart power integrated circuit becomes extremely complicated. It is useful.

An area in which a constant current source or a bias current source is needed is the publication "Switched-Carrents-Analog Technic for Digital Technology".
(Switched-currents an analogue for digital technol
ogy) "is the field of switched current technology. Briefly, this switched current technology is
It is a current mode signal processing technique that utilizes the performance of an S-transistor (which can be a TFT) to maintain the drain current by using the charge stored in the gate oxide film capacitor.

By using this technique, an integrator and
Bias elements such as delay lines are described in the publications mentioned above.
It can be shaped like Circuit according to the invention
Is any switched current that requires a constant bias current.
It can be used in any suitable part of the flow circuit. Figure 5 is loss
An example of a non-inverted integrator 20 without a switch is shown. In this circuit, 2
The individual current sources 21 and 20 provide suitable bias currents.
The circuit of the present invention is configured as follows.
The effective load RL of this circuit is the n-channel enhancement.
N-type MOS transistors Q7 and Q8 array value n channel
It consists of a Ru enhancement type MOS transistor Q9.
It Each of these transistors Q7 to Q9 is a TFT.
It Transistors Q7 and Q8 are the same
However, the transistor Q9 has a channel width / length ratio of
Ratio of transistor Q7 α₁It has a double ratio. Figure 5
The operation of the circuit 20 shown in FIG.
Although it is described on page 41, here is a brief explanation:
In the phase φ2 of the clock period (n-1), the switch
23 and 24 (these switches are of any suitable form)
Can be a switch, for example a MOS transistor
Will be closed and switch 25 will be opened.
The transistor Q7 is diode-connected and this transistor Q7
7 is the current i (n-1) from the input unit and the bus ass current
Current 2J from source 21 and current from transistor Q8
-(Ji_o(N-1) / α₁) And
Brush off. In the next phase φ2 of the clock period (n),
Switches 23 and 24 open and switch 25 closes.
Therefore, the transistor Q8 is diode-connected.
The transistor Q8 passes L2 = 2J-L1 and outputs
Flow i _out(N) is α₁(J-L1).

Of course, such an integrator can be used in any associated circuit, such as a video signal processing circuit.

The switched current circuit using the circuit according to the invention and the integrator circuit is of particular importance in connection with the two-dimensional active matrix address array 10 formed using thin film technology. FIG. 6 shows an example of such an array 30. The array 30 comprises an array of storage elements 31 arranged in n rows and m columns. Each storage element 31 may be a display element when the array 30 constitutes, for example, a liquid crystal display device, and may be a light sensing element such as a transistor or a pin diode when the array 30 constitutes an image sensor. You can Of course, the array 30 can also be a combination of two or more by providing various types of storage elements 31.

In FIG. 6, the storage element 31 is shown simply as a capacitor. In the case of a display device, this capacitor can be used as a capacitor of a display element, in the case of an image sensor, an intrinsic photodiode (or another capacitor added thereto) as a capacitor, and in the case of a thin film memory, a memory. It can be a storage capacitor for the device.

In the embodiment shown in FIG. 6, one electrode of each capacitor 31 is coupled to a common electrode which is maintained at a reference potential (ground in this example) and the other plate is n.
Channel enhancement type TFT switching element 3
This switching element 32 is connected to one of the two main electrodes.
Together with the storage element 31 form an array element, that is, a pixel. The gate electrodes, ie, control electrodes, of all the TFTs 32 associated with the memory elements 31 in the n-th row are coupled to the conductor portions 33 in the same row, and the other main electrodes of all the TFTs associated with the memory elements 32 in the m-th column are in the same column. Coupled to the conductor portion 34 of. By providing the row address circuit 35 and the column address circuit 36, each memory element can be individually accessed through the switching element TFT 32. The actual performance of the row address circuit and the column address circuit is determined according to the accuracy of the array, for example, whether it is a display device or an image sensor. It is necessary to supply signal information, and in the case of an image sensor, it is necessary to be able to read out the charges accumulated in the photosensitive element. Examples of row and column address circuits for these two devices can be found in many publications. Therefore, for example, the driving method of the liquid crystal display device can be referred to European Patent Application Publication No. 391655 or British Patent Application Publication No. 2186414, and the driving method of the image sensor can be described in, for example, US Pat.
Reference can be made to 3167, U.S. Pat. No. 4,382,187, and U.S. Pat. No. 4,945,243. Of course, other types of switching elements (diodes, TFTs)
Etc. (eg US Pat. No. 4,945,243).
It is obvious to those skilled in the art that other circuit configurations are also possible. In addition, the storage element 31
3 × 3 active area 3 as matrix array
Although only 0a is shown in FIG. 4, in practice the array can be made up of more storage elements, the actual number of elements being determined by the desired application.

The row address circuit and the column address circuit of such an array device generally use shift registers and the like, and these shift registers and the like do not usually need to use the current source circuits of the forms shown in FIGS. Both row and column drive circuits need to be integrated on the same substrate (typically glass or plastic substrate) as well as
Especially in the case of an image sensor, it is necessary to incorporate additional functions into the image sensor array. This additional feature
For example, image processing such as pixel level gain, A / D conversion, and closest averaging processing can be included. Many of these pixel level signal processing functions require a means to process the signals originating from the pixels that require a constant current source (high output impedance), which constant current source is beneficially implemented using the circuit according to the invention. can do.

FIG. 7 shows an example in which the circuit 10 according to the present invention is used in an image sensor. In this example, the circuit 10 is used to remove a signal generated in the light-sensing element of the image sensor from the signal generated when light is incident on the light-sensing element, that is, a "black" signal, so that an output signal is obtained. It is configured to accurately represent the sensed light.

As shown in FIG. 7, the circuit 10 is the circuit shown in FIG. 2, but in this example, the reference current source 3 is composed of an n-channel enhancement type TFT Q7 and the load resistance RL is composed of another n-channel enhancement TFT Q8. To do. Capacitors C ₁ and C ₂ are coupled between the source and gate electrodes of TFTs Q7 and Q8, respectively. TFT Q7
, And the control electrode of Q8 is coupled to the pixel of the image sensor 40, that is, the photosensitive element D3 of the image pickup element 41 via the switches SW1 and SW2, respectively. In this example, each switch SW1 and SW2 is a TFT.
The gate electrodes of Q7 and Q8 are coupled to the anode of the light sensitive diode D3 and the cathode of this diode D3 is coupled to the reference potential V _ref . The anode of the photosensitive diode D3 is also reset voltage _Vrst via the third switch SW3.
Bind to. Switches SW1 to SW3 are n-channel TF
T, which is controlled by applying an appropriate voltage to each gate electrode by a known method.

To understand the operation of the "black" signal extraction circuit shown in FIG. 7, assume that the photosensitive diode D3 is reset by closing (conducting) the switch SW3. Initially, the light-sensing diode D3 is shielded from light and the switch SW3 is opened (non-conducting state). Next, the switch SW1 is closed (conducting state) for a predetermined time, and the photo-sensing diode D3 is turned on by the TFT Q.
The charge (“black” signal) generated in the light-sensing diode which is coupled to the control electrode of No. 7 and is not irradiated with light is accumulated in the capacitor C1. Next, the switch SW1 is opened. If desired, it can be reset again before illuminating the light sensitive diode. Next, light is incident on the photo-sensing diode D3, the switch SW2 is closed for a predetermined time, and the charges generated during the light irradiation to the photo-sensing diode are transferred to the insulated gate of the TFT Q8. TF
TQ8 is a current I representing the sum of the light signal sensed by the light sensing diode during light irradiation and the "black" signal.
Pass _{s + d} . TFTQ7 passes the current I _d that represents the "black" signal by the charge accumulated in the capacitor C1, the current I _d will give a reference current to the circuit 10. The effect of the circuit 10 is that the same current I _d can flow through the TFTs Q1 and Q2. Of course, TF
Since the TQ8 causes the current I _{s + d} to flow, in order to make the current continuous at the output portion O, it is necessary to flow the current I _s to the connection portion J1 according to Kirfihoff's law. Therefore, the output section O
Generates a current signal I _s of the current signal I _s or "black" signal is removed to represent the actual light sensed by the light sensing diodes.

Photosensitive diode D of amplifier 4 of circuit 10
1 and D2 charge the capacitor C2 to represent the "black" signal.
Although it is not always necessary to irradiate light during the period of accumulation in the storage area, the circuit 10 is operated by irradiating light during the light irradiation of the photo-sensing diode D3. It is possible to irradiate the light-sensing diode D1 or D2 with the light irradiating the light-sensing diode D3, but since the light incident on the image sensor changes, a light source that generates individual constant light is used as the light-sensing diode. It is desirable to use it for D1 or D2. In such a configuration, the light-sensing diode D3 receives only the light incident on the upper surface of the diode and receives the light-sensing diode D3.
This can be achieved by designing the light-sensing diode to be metallized such that 1 or D2 receives only the light incident on the bottom surface of the diode.

FIG. 8 shows an insulating substrate 42 (generally glass).
FIG. 3 is a schematic cross-sectional view showing an image sensor formed by a thin film technique with a part thereof removed, showing a configuration in which different light sensing diodes can receive light from different directions.

In particular, FIG. 8 illustrates a photosensitive diode D1 and associated n-channel enhancement TFT (eg TF).
An example of a TQ4) and an example of a related n-channel enhancement TFT that constitutes one of the photo-sensing diode D3 and the switches SW1 to SW3 is shown. All TFTs can have the same structure.

FIG. 8 shows an inverted staggered structure for TFTs SW1 and Q4. Each TFT has a chromium gate electrode g formed on a chromium conductor track 43 for proper connection to the rest of the circuit. In general, the gate electrode g is covered with a gate insulating layer 44 of silicon nitride, and a channel forming layer 45 which is generally an intrinsic semiconductor layer (a semiconductor to which impurities are not added) of polysilicon is formed on the gate insulating layer by a normal deposition and lithography technique. Form. A conventional etch stop insulating region 46 is formed in the control area of the channel forming layer 45 and then an n-type semiconductor region 47.
And source and drain electrodes (usually chromium) s and d are deposited and defined. An insulating layer 48 is formed on the source and drain electrodes, a contact window is formed in the insulating layer, and a metal layer made of chromium and aluminum is deposited to define the source and drain electrodes. Also connect to the part.

The metal layer which constitutes one of the source and drain electrodes 49 also forms one of the electrodes 50a or 50b of the associated photo-sensing diode. In this case, the photosensitive diodes D1, D2 and D3 are n-i-p by depositing and patterning a layer of appropriately doped semiconductor material, typically a layer of amorphous silicon.
Consists of a diode. Then another insulating layer 51 of silicon nitride is deposited and patterned to deposit and pattern another metal layer to form another electrode 5 for the photosensitive diode.
2a and 52b are formed. As is clear from FIG.
An opening A is formed in the lower electrode 50a of the light-sensing diode D1 or D2 so that light from a suitable backlight BL is incident on the light-sensing diode D1 or D2, while light is emitted by the lower electrode 50b of the light-sensing diode D3. Sensing diode D
3 is shielded so that the direct light from the backlight BL does not enter. On the contrary, the upper electrode 52a of the light sensing diode D1 or D2 shields these diodes from incident light, and the upper electrode 52b of the light sensing diode D3.
Is formed so that light is incident on the upper side surface of the diode D3. As shown, the image sensor can be covered with a protective insulating layer 53 of a material such as polyimide, on which the document D to be imaged can be placed. In this case, the document D can be illuminated with light from another light source, that is, light from another backlight, which is incident through the light transmitting portion of the image sensor 40.

Of course, when the object to be imaged is not in direct contact with the image sensor, the object can be imaged by the light from the surroundings. On the other hand, in order to form the "black" signal, a suitable shutter such as a mechanical shutter or a liquid crystal display shutter is used to detect the photo-sensing diode D3.
Need to be shaded.

Although FIG. 7 shows only the pixel 41, the circuit of FIG. 7 can of course be applied to a two-dimensional active matrix image sensor having a matrix array of pixels 41. In this case, each pixel is accessed by the row conductor 54 and the column conductor 55, and in this example, the cathode of the photosensitive diode D3 is coupled to each row electrode 54. Also, n
It is also possible to configure a single circuit 10 to share for all the pixels in one column of the array by using the additional switches of the channel TFTs. FIG. 9 shows a part of the m columns of the two-dimensional array as an example. Each light sensing diode D3 has a capacitor C1 and C2 and a switch S.
W1 to SW3, one TFT for each pixel column
Only Q7 and TFT Q8 are provided. Each capacitor C1 is coupled to the first column conductor 55 coupled to the control electrode of the TFT Q7 via the switch SW4, and each capacitor C1
2 is coupled to the second column conductor 55b coupled to the control electrode of the TFT Q8 via the switch SW5. By using an appropriate timing signal for controlling the operation of the switches SW1 to SW5, the charge stored in the capacitor C2 of the N rows of light sensing diodes D3 is read out, and in the meanwhile, the N−1th row of light sensing diodes D3 is reset. At the same time, the light-sensing diodes in the N + 1th row can be illuminated to store charge in the associated capacitor C2. Capacitor C
Depending on the length of time that 1 can hold the accumulated charge and the length of time required to read out the photo-sensing diodes of the entire array, the “d” of each photo-sensing diode D3 is read before the photo-sensing diodes D3 forming the array are read. A "black" signal can be obtained, or can be obtained in the manner described above before the individual photo-sensing diodes D3 are read out. When an individual circuit 10 is provided for each column, m columns of photo-sensing diodes D3
Can be read simultaneously, or a single circuit 10 can be used for the entire array with suitable multiplexer circuits.

As pointed out above, the present invention provides a high impedance which constitutes the sink for the majority carriers required in a unipolar transistor (generally an n-channel enhancement type MOS transistor which requires a current source). The present invention can be useful in thin film technology circuits, such as thin film displays, control circuits for image sensors and memories, and in bulk semiconductor technology, for example in the field of smart power. A current mirror circuit can be realized using such a sink for majority charge carriers, and of course the value of the output current can be adjusted by using known current mirror technology. The present invention is
It can also be used to apply a constant voltage to a suitable load.

In the embodiment described above, the transistor Q
1 and Q2 are matched so that the same current flows,
It is also possible to make appropriate changes to the circuit so that currents having a predetermined ratio (not equal to each other) are made to flow so that the output current has a predetermined ratio with respect to the reference current I _r .

In general, all elements of the circuit 10 according to the invention can be integrated on the same substrate. On the other hand, one or more elements may have a separate structure.

In principle, according to the present invention, a transistor that can be used by appropriately changing the voltage polarity and the like is, for example, a pnp bipolar transistor or a P-type transistor.
It can also be applied in the case of P-types such as channel enhancement MOS transistors, so that it is possible to form a circuit which constitutes a difficult current sink when only P-type devices are used. The situation in which such a P-type device is necessary or desirable occurs only if, for example, a logic circuit requiring a current source for a special purpose is integrated with a P-channel vertical power device.

Of course, especially when the circuit according to the invention is formed using bulk technology rather than thin film technology, the enhancement MOS transistors can be replaced by bipolar transistors of suitable polarity (except transistor Q6 of FIG. 4). That is, the n-channel MOS transistor is replaced with an npn bipolar transistor).

The present invention is not limited to the above-described embodiments, and various changes and modifications can be made.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a known circuit that constitutes an NMOS inverter.

FIG. 2 is a circuit diagram showing a circuit constituting a current source according to the present invention.

FIG. 3 is a circuit diagram showing a circuit constituting a current source according to the present invention.

FIG. 4 is a circuit diagram showing another circuit constituting the current source according to the present invention.

FIG. 5 is a circuit diagram showing an example of a switched current circuit having a current source circuit according to the present invention.

FIG. 6 is a circuit diagram showing a configuration of a two-dimensional storage element array having one or more circuits according to the present invention.

FIG. 7 is a circuit diagram showing a configuration of an example of an image sensor using a circuit according to the present invention.

8 is a sectional view showing a part of an image sensor in which the circuit according to the present invention shown in FIG. 7 is incorporated.

FIG. 9 is a circuit diagram showing a configuration of a two-dimensional image sensor incorporating a circuit according to the present invention.

[Explanation of symbols]

 1, 2 feeding line Q1 first transistor Q2 second transistor RL load Q3 third transistor Q4 fourth transistor Q5 fifth transistor Q6 another transistor 4 amplifying means D1, D2, D3 light sensing diode C1, C2 capacitors SW1 to SW3 switches

Claims (10)

[Claims] 1. A circuit forming a sink for majority charge carriers, the first and second feed lines and first and second polarities of the same polarity each having a control electrode and a first and a second main electrode. A second transistor and an amplifying means having a main and negative input and an output, the second transistor having a dimension of a predetermined ratio with respect to the corresponding dimension of the first transistor; And a first main electrode of the second transistor is coupled to one of the first and second power supply lines, and a main electrode of the first transistor supplies a reference current through the first transistor to supply a reference current source. Via a load, and a second main electrode of the second transistor is arranged to be coupled to the other feed line via a load, and during operation of the circuit the majority carrier is 2's Via Njisuta flowed in a direction away from the other feed line, the negative input of the amplifying means coupled to the second main electrode of the first transistor, a positive input second second transistor
Forming a negative feedback for equalizing the voltage at the positive input and the voltage at the negative input of the amplifying means by coupling the output to the control electrodes of the first and second transistors, A sink forming circuit configured to supply a current having a predetermined ratio to the reference current to a load coupled between the second main electrode of the second transistor and the other power supply line. 2. The first and second transistors comprise n-channel enhancement MOS transistors having source electrodes coupled to the negative and positive inputs of the amplifying means, respectively, to form a current source. The sink forming circuit according to claim 1. 3. The sink forming circuit according to claim 1, wherein the first and second transistors are matched with each other. 4. An inverting circuit, wherein the amplifying means has an input transistor circuit coupled to the positive input portion and the negative input portion, and a load device having a light sensing element illuminated during the operation of the inverting circuit. The sink forming circuit according to claim 1, further comprising: 5. The third and fourth input transistor circuits are provided.
And a fifth transistor, the nuclear transistor comprising first and second main electrodes and a control electrode, the control electrode of the third transistor being coupled to the positive input, and the control electrode of the fourth transistor being A negative input, a control electrode of a fifth transistor coupled to a bias voltage source, and third and fifth transistors connected in series between the first and second feed lines, The sink forming circuit according to claim 4, wherein a fifth transistor is coupled in series with the fourth transistor and the light sensing element, and the light sensing element is coupled to the output of the amplifying means. 6. The sink formation according to claim 5, wherein the photo-sensing element comprises a photo-sensitive nonlinear resistance device coupled between the first main electrode of the fourth transistor and the first feed line. circuit. 7. The light-sensing element comprises at least one light-sensing device coupled between a second main electrode and a control electrode of another transistor in series with the fourth transistor, the light-sensing device comprising: 6. The sink forming circuit according to claim 5, wherein a voltage is generated between the second main electrode and the control electrode of the other transistor when is input. 8. A switched current circuit having a current source circuit configured based on the sink forming circuit according to claim 1. Description: 9. A two-dimensional array device of storage elements arranged in rows and columns, comprising row conductors and column conductors for accessing individual storage elements, and access to the storage elements by these row conductors and column conductors. A two-dimensional array device of storage elements, comprising a control circuit for controlling, wherein the control circuit has at least one sync forming circuit according to any one of claims 1 to 8. 10. At least one photosensitive element, the sink forming circuit according to claim 1, a first and a second main electrode, and an insulated gate electrode, Between the first power supply line and the second power supply line
Another transistor connected in series with the second transistor to form a reference current source, and connected in series to the second transistor between the first power supply line and the second power supply line, and to a load of the circuit. A second transistor and an additional transistor for providing an output at the connection between the second transistor and the further transistor, and switching means, the switching means connecting the photosensitive element to the feed line and the further transistor. A second transistor coupled to a control electrode of the photosensor to generate a first current representative of a first signal generated by the photosensing element when the photosensing element is not illuminated and power the photosensing element. Caused by a line coupled to the control electrode of the additional transistor when the additional photo-sensing device is illuminated. A second current representing the second signal is generated, the third image sensor adapted to generate a current representative of the difference between the first and second signals which may arise in the output section.