JPH07229910A - Pulse counter circuit - Google Patents

Abstract

PURPOSE:To provide a pulse counter circuit which generates pulse signals of a high resolution thereby to reduce influences of quantization errors which are influential when an input pulse signal is used as it is, for example, in order to control a motor using an encoder of a low accuracy. CONSTITUTION:In a pulse counter circuit having a counter register 20 which integrates pulses received by a receiver circuit 10 and reading the pulses with a predetermined sampling cycle tau, there are provided a counter buffer 30 which stores a previous count value of the counter register 20, a differential calculator 40 which operates a differential value of count data from a current count value of the counter register 20 and a stored value in the counter buffer 30, a differential buffer 50 which stores (n) differential values operated by the calculator 40, a differential average-operating part 60 which operates an average value of the stored values of the differential buffer 50, and a pulse count-generating device 70 for adding the average value to a previous output value, thereby generating a current pulse count.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse counter circuit for counting the number of pulses of a pulse signal input at a constant cycle, and more particularly to improvement in obtaining a count value having a resolution higher than the input pulse.

[0002]

2. Description of the Related Art The applicant of the present application has proposed an encoder for detecting the rotation angle of a rotary shaft in Japanese Unexamined Patent Publication No. 2-242116. In this prior application, a first counter for obtaining a rough phase difference and a fine counter are provided. The angle detection with high accuracy is performed in combination with the second counter for obtaining the phase difference. Such a motor control encoder has a resolution of 2000 to 8000 pulses per rotation.

[0003]

However, exceptionally, there is a motor using an encoder with a very low accuracy of about 200 pulses per rotation. For such a motor, if a servo control device that controls the motor with a pulse count value counted at a constant sampling period is used, as with a motor having an ordinary high-precision encoder, quantization error due to low resolution Is observed as the rotation ripple of the motor. Then, especially when the servo gain is large, the motor rotates at an irregular speed,
There is a problem that it adversely affects the motor control. The present invention has solved the above-mentioned problems, and if the input pulse signal is used as it is, as in the case of controlling a motor using an encoder with low accuracy, a higher resolution can be obtained when it is affected by a quantization error. An object of the present invention is to provide a pulse counter circuit that generates a high pulse signal and reduces the influence of quantization error.

[0004]

The present invention which achieves the above object has a receiver circuit 10 for receiving a pulse and a counter register 20 for accumulating the pulses received by the receiver circuit. In a pulse counter circuit that reads the integrated value of the counter at a predetermined sampling period τ, a counter buffer 30 that stores the previous count value of the counter register, a current count value of the counter register, and count data from the stored value of the counter buffer. Difference calculator 40 for calculating the difference value of N and the difference value calculated by this difference calculator is stored n times by tracing back n times (n is a natural number of 2 or more) from this time with the sampling cycle as a unit. A buffer 50 and a difference average value calculator for calculating an average value of n stored values stored in the difference buffer. 0, the previous output value of the average value computed for difference average value calculating section and the own station are added, is characterized by comprising a current pulse number generator 70 for generating a pulse count value.

[0005]

A difference buffer and a difference average value calculation unit are provided in order to obtain the increase number of the number of pulses received by the receiver circuit for each sampling period. The precision of the fraction is determined by n. If the value of n is increased, the precision of the fraction is increased, but the response speed becomes slow due to the calculation of the moving average. Therefore, the precision is set to an appropriate value. The pulse number generator adds and outputs the number of pulses in the current sampling period and the current number of increased pulses having the fraction obtained by the difference average value calculation unit.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. Figure 1
FIG. 3 is a configuration block diagram showing an embodiment of the present invention. In the figure, a receiver circuit 10 is a circuit that receives a pulse signal supplied from an incremental encoder or the like. The counter register 20 integrates the pulses received by the receiver circuit 10, and the external device reads the pulses at a predetermined sampling period τ. This sampling period τ
Is, for example, about 10 ms, and is a value that enables the servo control calculation to the extent that it is not affected by the quantization error in the above-described encoder with the normal accuracy.

The counter buffer 30 stores the count value N _-1 of the counter register 20 in the previous sampling cycle. The difference calculator 40 calculates the current count value N ₀ of the counter register 20 and the stored value N _{−1 of the} counter buffer 30.
From this, the difference value ΔN ₀ of the count data is calculated. ΔN ₀ = N ₀ -N _-1 (1)

The difference buffer 50 retroactively stores n difference values (n is a natural number of 2 or more) from the current value, which is the difference value calculated by the difference calculator 40. The difference average value calculator 60 calculates the average value ΔN _AV of the n stored values stored in the difference buffer 50. ΔN _AV = (ΔN ₀ + ΔN _-1 + ... + ΔN _n-1 ) / n (2)

[0009] Preferably, if n is a power of 2 2 ⁱ (i is a natural number), there is no remainder when calculating the average value ΔN _AV , and therefore a shift operation using a shift register is possible. Therefore, the configuration of the difference average value calculation unit 60 is simplified. Further, the calculation accuracy of the average value ΔN _AV is such that a resolution of 1 / n can be obtained.

The pulse number generator 70 adds the average value ΔN _AV calculated by the difference average value calculator 60 and the previous output value N ₋₁ of its own station to generate the current pulse count value, and the pulse number Output as. Here, since ΔN _AV is a pulse number including a fraction, the reception side includes a fraction part corresponding to the ripple.

The operation of the thus constructed device will be described below. FIG. 2 is an explanatory diagram of the pulse signal input to the receiver circuit 10 and the sampling period τ. (A) is the input pulse, (B) is the counter register integrated value, (C) is the sampling period τ, (D). Is the reading of the difference calculator. In the figure, the sampling periods τ ₁ , τ ₂ , ..., τ ₆ are represented by “↑”.

The count value of the counter register 20 in each sampling cycle increases like 0, 3, 5, 7, 9, 12, .... The difference increment value of the difference calculator 40 in each sampling period τ ₁ , τ ₂ , ..., τ ₆ is 3,2,2,2,3,2 ,.
As described above, it is assumed that three pulses are generated once every four sampling periods and two pulses are generated in the rest. Then,
If the integrated value of the counter register 20 is read as it is, ripples occur at a frequency four times the sampling period. Here, assuming that the number of storages n of the difference buffer 50 is 4, the difference average value calculation unit 60 sets the average value ΔN _AV to 2/4
Output pulse.

Then, from the pulse number generator 70, the integrated value of the counter register 20 is practically averaged to 0, 2.25,
The number of pulses including the fraction such as 4.50,6.75,9.00,11.25, ... Is output. The number n stored in the difference buffer 50 functions as a filter to improve the resolution and reduce the ripple component. Further, the larger n is, the higher the resolution becomes, but the response of the pulse count is delayed. Therefore, particularly when the frequency fluctuation of the generated pulse is small or the sampling frequency is high, it is possible to select a large n. it can.

FIG. 3 is a block diagram showing the configuration when a pulse signal is transmitted from an encoder including A phase and B phase. The rotation angle of the motor 2 is detected by the encoder 4, and the rotation direction is CW (clockwise) by two signals of A phase and B phase.
It is possible to determine whether it is CCW (counterclockwise). The A phase / B phase signal of the encoder 4 is supplied to the A phase receiver circuit 11
To the B-phase receiver circuit 12, respectively. The quadrupling circuit 13 inputs the pulse signals from the receiver circuits 11 and 12, converts the pulse signals into signals having a resolution four times as high as the pulse signals, and sends the signals to the counter register 20.
Since there is a 90 degree shift between the A-phase signal and the B-phase signal of the encoder 4, this phase difference is used to increase the resolution. For example, MSM5210R supplied by Oki Electric.
A dedicated IC such as S is used. With this configuration, the pulse signals can be integrated even when they have polarities.

FIG. 4 is a block diagram showing the configuration when the pulse signal includes an up pulse and a down pulse. The rotation angle of the motor 2 is detected by the encoder 4, and the encoder 4
Using the up pulse and down pulse of, the two information of the rotation direction and the rotation angle are sent to the counter circuit side. The up pulse receiver circuit 14 receives the up pulse signal sent from the encoder 4, and the down pulse receiver circuit 16 receives the down pulse signal sent from the encoder 4 and sends them to the adder circuit 18, respectively. Adder circuit 18
Then, the integrated value of the up pulse receiver circuit 14 and the integrated value of the down pulse receiver circuit 16 are added and sent to the counter register 20. As a result, the counter register 20 substantially receives two pieces of information about the rotation direction and the rotation angle of the motor 2.

[0016]

As described above, according to the present invention,
With respect to an integrating counter register 20 suitable for use in an incremental encoder or the like, a difference is calculated for each reading sampling cycle, the difference value is averaged over several sampling cycles, and a pulse number generator 70 is used. Since smoothing is performed, there is an effect that the rotational ripple of the motor is reduced even when performing motor control with a low-resolution encoder. Therefore, good controllability is maintained even when the command value is determined by the number of pulses below the decimal point or when the servo gain is high.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing a configuration of the present invention.

FIG. 2 is an explanatory diagram of a pulse signal input to a receiver circuit 10 and a sampling period τ.

FIG. 3 is a configuration block diagram when a pulse signal is transmitted from an encoder including A phase and B phase.

FIG. 4 is a configuration block diagram in the case where a pulse signal includes an up pulse and a down pulse.

[Explanation of symbols]

 10 receiver circuit 20 counter register 30 counter buffer 40 difference calculator 50 difference buffer 60 difference average calculator 70 pulse number generator

Claims (1)

[Claims] 1. A receiver circuit (10) for receiving pulses.
And a counter register (20) for accumulating pulses received by the receiver circuit. The pulse counter circuit reads the integrated value of the counter register at a predetermined sampling period (τ). A counter buffer (30) for storing a numerical value, a difference calculator (40) for calculating a difference value of count data from the present count value of the counter register and a stored value of the counter buffer, and a difference calculator for calculation. The difference value is n times from this time with the sampling cycle as a unit (n is a natural number of 2 or more)
Of the difference buffer (50) that stores only n number of values stored retroactively, a difference average value calculation unit (60) that calculates an average value of the n stored values stored in the difference buffer, and a difference average value calculation unit of the difference average value calculation unit. A pulse counter circuit, comprising: a pulse number generator (70) for adding the calculated average value and the previous output value of the own station to generate a current pulse count value.