JPH07225783A - Function design support device and method therefor - Google Patents

Abstract

PURPOSE:To provide a function design support device having a user-friendly interface which is capable of inputting the operations of a logic circuit by using graphics, tables and characters, etc., performing a function verification by using these graphics, tables and characters, etc., and generating function description languages from these graphics, tables and characters, etc. CONSTITUTION:A functional chart expressing the operation of a logic circuit is prepared on the screen of a CRT monitor 2 by a functional chart editor part 5 by using the graphics, tables and characters, etc., displayed on the screen of the CRT monitor 2. In the prepared functional chart, the presence or absence of the contradiction is verified in a functional chart check part 6. When no contradiction exists in the function drawing, a function verification is performed for this functional chart by a function simulation part 7. When no error exists in a circuit operation as the result of the function verification, a function description language is generated from the functional chart by a function description language conversion part 6 and net list information 9 is generated from the function description language by a logical synthetic part 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention, when designing a logic circuit,
A functional design support device that performs functional design and functional design verification using a functional diagram that expresses the operation of a logic circuit with figures, tables, characters, etc., and a function that performs functional design and functional design verification using the functional design support device Design support method.

[0002]

2. Description of the Related Art In the design of a logic circuit, the logic design occupies most of the design. Conventionally, as shown in FIG. 58, by arranging a figure showing a logic element on the screen of a display and connecting the figures to each other. The logic design is performed by a logic design support device that creates a logic design drawing and generates netlist information from the logic design drawing.

FIG. 58 is a block diagram showing the structure of a logic design support device.

In FIG. 58, 501 is an input device, and 50
2 is a CRT monitor, and the CRT monitor 502 is
Displays the logical design drawing described by the logical design drawing editor section. Reference numeral 503 denotes a processing unit of the logic design support device, 504
Is a logic design drawing information storage device, and the logic design drawing information storage device 504 stores logic design drawing information regarding the logic elements expressing the logic of the logic circuit and the connection relationship between the logic elements.

Reference numeral 505 is a logical design drawing editor section,
A function of writing a logical design drawing on the screen of the CRT monitor 502, a function of storing logical design drawing information relating to the described logical design drawing in the logical design drawing information storage device 504, and logical design drawing information It has a function of reading from the storage device 504.

A logical design drawing check unit 506 reads the logical design drawing information from the logical design drawing information device 504 and verifies whether or not there is a contradiction in the logical design drawing indicated by the logical design drawing information.

Reference numeral 507 is a logic simulation section,
From the logic design drawing information device 504, the logic design drawing information relating to the logic design drawing which has been verified by the logic design drawing checking unit 506 and has no contradiction is read, logic simulation is executed for this logic design drawing, and the logic of the logic circuit is executed. Perform verification.

Reference numeral 508 denotes a netlist conversion unit, which transfers information from the logic design drawing information device 504 to the logic simulation unit 5
The logic design drawing information regarding the logic design drawing whose logic verification has been completed is read by 07, and netlist information is generated from this logic design drawing.

Reference numeral 509 denotes netlist information generated by the netlist conversion unit 508.

However, when the logic circuit becomes complicated on a large scale, it becomes necessary to design at a higher level than the logic design. Under such circumstances, in recent years, the operation of a circuit is described in a functional description language by a text editor, and netlist information is generated from the functional description language by using logic synthesis.

In addition, like SPeeDCHART-VHDL introduced in Nikkei Electronics (October 12, 1992, No. 565, p239), input a state transition diagram expressing the operation of the control unit of the logic circuit. As a result, a tool for automatically verifying an operation on a state transition diagram and automatically generating a function description language for expressing the operation, and a computer-aided design system for ASIC disclosed in Japanese Patent Laid-Open No. 1-309185, data flow of a logic circuit. Is expressed using a flow chart, the function is verified on the flow chart,
It is known to use a tool for automatically generating a netlist from a flowchart to design part of the operation of a logic circuit in a graphic representation.

[0012]

In the above logic design support apparatus, the logic of the logic circuit is represented by arranging figures showing logic elements and connecting the figures to each other.
In functional design, higher-level concepts such as state transition diagrams and data transfer to storage elements must be used for designing, and replacing the logic elements in the logic design support device with storage elements is sufficient for functional design. It is difficult to adapt the logic design support device to the functional design because it is not possible.

Further, in the case of designing using a function description language, it is very troublesome for a logic circuit designer who is familiar with circuit diagrams because the user interface for describing the operation of the logic circuit in the language is unreasonable. It takes a lot of time and work.

Further, in the case of designing using a state transition diagram or a flow chart, only a part of the operation of the logic circuit can be designed, so that the other operation must be designed by using the function description language.

For example, the state transition diagram can describe only the control operation of the logic circuit. Further, the flow chart expressing the data flow can describe only the control operation. However, in order to describe all the operations of the logic circuit, it is necessary to describe the data processing operation, the control operation, and the combinational logic.
Designing with traditional graphic representations is not enough.

The present invention has been made in view of the above, and all operations of a logic circuit can be input by using figures, tables, characters, etc. without using any functional description language. Design support apparatus having a user-friendly interface that can perform function verification using characters, characters, etc., and can generate a function description language from figures, tables, characters, etc., and such a function design support apparatus It is an object of the present invention to provide a functional design support method that makes it possible to realize.

[0017]

In order to achieve the above-mentioned object, the solving means specifically implemented by the invention of claim 1 is intended for a functional design support device for supporting functional design of a logic circuit, and A display device that displays chart elements such as tables and characters, a storage device that stores functional diagram information related to a functional diagram that expresses the operation functions of a logic circuit by the chart elements, and a chart element on the screen of the display device. Function diagram editor means having a function of describing a function diagram by using the function diagram, a function of storing function diagram information related to the described function diagram in the storage device, and a function of reading the function diagram information from the storage device, and the function diagram. A function diagram check means for reading the function diagram information relating to the function diagram described by the editor means from the storage device and verifying whether or not there is a contradiction in the function diagram, and the function diagram check means. A functional simulation means for reading functional diagram information relating to a functional diagram whose presence or absence has been verified from the storage device and performing functional verification for the functional diagram; and a functional diagram for which functional verification has been performed by the functional simulation means. The functional description information is read from the storage device, and the functional description language conversion means for generating a functional description language from the functional diagram and the functional description language generated by the functional description language conversion means are input to generate netlist information. And a logic synthesis means.

The invention of claim 2 is, specifically, claim 1
In the structure of the invention, the display device has a multi-window composed of first, second, third and fourth windows,
The function diagram editor means, on the first window of the display device, state transition diagram editor means for describing the control unit of the logic circuit in the form of a state transition diagram, and on the second window of the display device, Data path editor means for describing the data path part of the logic circuit in the form of a data path diagram expressed by the arrangement of the functional elements and the connection relationship between the functional elements, and the logic circuit on the third window of the display device. A truth table editor means for describing the combination circuit section of the logic circuit in the form of a truth table, and a combination of the combination circuit section of the logic circuit which is difficult to be represented by the truth table on the fourth window of the display device. And a logical expression editor means for describing the circuit in the form of a logical expression table.

The invention of claim 3 is, specifically, claim 1
In the configuration of the invention described above, the function diagram checking means reads the function diagram information from the storage means, and determines whether or not there is a contradiction in the function diagram indicated by the function diagram information based on a check rule. Checking means having function of creating result information, check result screen displaying means for displaying check result information on the screen of the display device, and check result error report file creating check result error report file from check result information And a structure having means.

The invention of claim 4 is, specifically, claim 1
In the configuration of the invention described above, the functional design support device further includes a language-based functional simulator that inputs the functional description language generated by the functional description language conversion means and performs a functional simulation on the functional description language. The language conversion means converts the functional diagram information into a functional description language for a language-based functional simulator that converts the functional diagram information into a functional description language for a language-based functional simulator suitable for the language-based functional simulator, and the functional diagram information after logical synthesis of the functional diagram information. Convert to a logic synthesis function description language suitable for the logic synthesis means, which guarantees that the operation of the logic circuit is the same as the result of the function simulation on the function description language for the language base function simulator by the language base function simulator. It is equipped with a configuration that has a function description language conversion means for logic synthesis. It is intended to.

The invention of claim 5 is, specifically, claim 4
In the configuration of the invention described above, the logic synthesizing function description language converting means realizes the function diagram information as a selector without priority after the logic transfer of the condition transfer in the data path diagram indicated by the function diagram information. Priority-less selector configuration suitable for the synthesizing unit Priority-less selector configuration logic synthesizing function description language converting unit and the same function diagram information are represented by the data path diagram shown by the function diagram information. In order to realize the condition transfer in the above-mentioned condition as a selector with priority order after logic synthesis, a selector structure with priority order suitable for the logic synthesis means is converted to a functional description language for logic synthesis function selector means with logic structure for priority synthesis The same function diagram information as the priority order after the condition transfer in the data path diagram indicated by the function diagram information is logically synthesized. A priority-less tri-state configuration logic synthesis function description language conversion means for converting into a priority-less tri-state configuration logic synthesis function description language realized as a tri-state, and the same function diagram information, There is a priority order suitable for the logic synthesizing unit that realizes the condition transfer in the data path diagram indicated by the function diagram information as a tristate with a priority order after the logic synthesis. A configuration having a tristate configuration logic synthesis function description language conversion means is added.

The invention of claim 6 is, specifically, claim 4
In the configuration of the invention described above, the logic synthesizing unit includes a state transition diagram-oriented logic synthesizing unit, a data path-oriented logic synthesizing unit, and a random logic-oriented logic synthesizing unit. , A state transition diagram function description language conversion means for converting information about the state transition diagram in the function diagram information into a state transition diagram function description language suitable for the state transition diagram oriented logic synthesis means, and Data path diagram function description language conversion means for converting information related to the data path diagram into a data path diagram function description language suitable for the data path oriented logic synthesis means, and information regarding the truth table in the function diagram information is randomized. Truth table functional description language conversion means for converting into a truth table functional description language suitable for logic-oriented logic synthesis means, and information relating to a logical expression table in the same functional diagram information It is intended to add a configuration and a logical expression hardware description language conversion means for converting the logical expression hardware description language suitable for the logical direction logic synthesis means.

The invention of claim 7 is, specifically, claim 4
In the configuration of the invention described above, the functional description language conversion means for logic synthesis logically synthesizes the data transfer diagram information for each facility such as a register or a terminal on the data path diagram among the function diagram information and condition transfer for each facility. A priority-less selector configuration suitable for the logic synthesizing means, which is later realized as a selector without priority, is converted to a logic description function description language, and a priority-less selector configuration logic synthesis function description language conversion means is provided. Selector structure with priority order for converting data path diagram information into a selector with priority order, which realizes condition transfer for each facility as a selector with priority order after logic combination The function description language conversion means for logic synthesis and the data path diagram information for each facility are provided in the facility. A non-priority tristate configuration logic synthesis function description for converting each condition transfer into a non-priority tristate configuration logic synthesis function description language suitable for the logic synthesis means, which is realized as a priority-less tristate after logic synthesis Language conversion means and data path diagram information for each facility are realized as tristates with priority after condition transfer for each facility after logic synthesis. A function description language conversion means for tri-state logic synthesis having a priority for converting to a language, and reading the function diagram information from the storage device, and for each facility on the data path diagram indicated by the function diagram information , Considering the circuit model configuration you want to obtain after logic synthesis, the selector configuration without priority Physical synthesis function description language conversion means, said priority There selector configuration logic synthesis function description language conversion means, said priority without tristate configuration logic synthesis function description language conversion means, or,
A configuration for driving the tristate configuration logic synthesis function description language conversion means with priority is added.

The invention of claim 8 is, specifically, claim 1
In the configuration of the invention described above, the function simulation means simulates the operation function of the logic circuit for a predetermined simulation time t based on the state value at the simulation time T, thereby simulating the simulation time T +.
Function simulator means for executing the time advance step functional simulation for obtaining the state value at t, and input for inputting test data used at the time of execution of the function simulator means and displaying the result of the function simulation obtained by the execution of the function simulator means. Display means and control means for controlling the transfer of the test data from the input display means to the functional simulator means and for controlling the transfer of the functional simulation result from the functional simulator means to the input display means. The configuration is added.

The invention of claim 9 is, specifically, claim 8
In the configuration of the invention described above, the function simulator means further has a function of executing a time backward function simulation for obtaining a state value at a simulation time T−n × t (where n is an integer of 1 or more). It is something to add.

According to a tenth aspect of the invention, specifically, in the configuration of the eighth or ninth aspect of the invention, the input display means is a test in a function description language in which an operation function of a logic circuit is described in a text base. A function description language input display means for inputting data and displaying the function simulation result on the function description language is provided, and the control means controls the function description language input display means. Is added.

The eleventh aspect of the invention is, specifically, in the configuration of the eighth or ninth aspect of the invention, in which the input display means expresses the operation function of the logic circuit by means of graphic elements such as figures, tables and characters. A functional diagram format pattern inputting means for inputting the functional diagram format pattern on the functional diagram as the test data and displaying the functional simulation result on the functional diagram is provided, and the control means inputs the functional diagram format pattern input. A configuration having a functional diagram type pattern input display control means for controlling the display means is added.

According to a twelfth aspect of the present invention, specifically, in the configuration of the eleventh aspect of the present invention, the function diagram format pattern input display means is a data path diagram format for expressing an operation function of a logic circuit in a data path diagram. A data path diagram format pattern inputting means for inputting a data path diagram format pattern on the representation diagram as the test data and displaying the functional simulation result on the data path diagram format representation diagram is provided. The input display control means is to add a configuration having a data path diagram format pattern input display control means for controlling the data path diagram format pattern input display means.

According to a thirteenth aspect of the present invention, specifically, in the configuration of the eleventh aspect of the present invention, the function diagram format pattern input display means is a state transition diagram format in which an operation function of a logic circuit is represented by a state transition diagram. A state transition diagram format pattern inputting means for inputting a state transition diagram format pattern on the representation diagram as the test data and displaying the functional simulation result on the state transition diagram format representation diagram is provided. The input display control means adds a configuration having a state transition diagram format pattern input display control means for controlling the state transition diagram format pattern input display means.

In a fourteenth aspect of the present invention, specifically, in the configuration of the eleventh aspect of the invention, the functional diagram format pattern input display means is a logical expression format expression diagram for expressing the operation function of the logic circuit by a logical expression. The above logical expression format pattern is input as the test data, and the logical expression format pattern input display means for displaying the functional simulation result on the logical expression format representation diagram is provided, and the functional diagram format pattern input display control means is provided. A configuration having a logical expression format pattern input display control means for controlling the logical expression format pattern input display means is added.

According to a fifteenth aspect of the present invention, specifically, in the configuration of the eleventh aspect of the present invention, the function diagram format pattern input display means is a truth table format for expressing an operation function of a logic circuit in a truth table. A truth table format pattern inputting means for inputting the truth table format pattern on the representation diagram as the test data and displaying the functional simulation result on the truth table format representation diagram is provided. The input display control means adds a configuration having truth value table format pattern input display control means for controlling the truth value table format pattern input display means.

According to a sixteenth aspect of the present invention, specifically, in the configuration of the eighth or ninth aspect of the invention, the input display means controls execution of functional simulation of the functional simulator means and input control of the test data. The control means has a simulation control panel display means for displaying a simulation control panel to be executed, and the control means has a configuration having a simulation control panel display control means for controlling the simulation control panel display means.

In a seventeenth aspect of the present invention, specifically, in the configuration of the eighth or ninth aspect of the invention, the function simulator means stores the state value change history at all simulation times for each circuit model forming the logic circuit. A configuration having a state value storage table to be held is added.

The invention of claim 18 is, specifically, in the structure of the invention of claim 8 or 9, wherein the functional simulator means is an event list composed of a list of events for storing change information of state values. , An event processing means for extracting an event from the event list and selecting a process according to the type of the event to update the state value, and an element that may cause a new state value change by updating the state value of the event processing means And an evaluation unit that stores the change information in an event and adds it to the event list when a new state value change occurs, the event processing unit extracting the event from the event list. Processing means, and event type determination processing means for determining the type of event extracted by the event extraction processing means , A normal event processing means for updating the state value, a clock event processing means for updating the state value of the clock signal, and a register input data event processing means for updating the state value of the input data signal of the register. The configuration is added.

In a nineteenth aspect of the present invention, specifically, in the configuration of the eighth or ninth aspect of the invention, the input display means has each bit of one of logical signals 0, 1, X and Z. An input signal having an n-bit width (n ≧ 2) represented by a logic signal is input, and each bit of the input signal is a 0 drive bit indicating whether the bit can take a logical value 0 and the bit. By encoding into a coded bit consisting of 1 drive bit indicating whether or not a logical value of 1 is possible, n
Coding means for generating a coded input signal composed of 0 drive words consisting of 0 drive bits and 1 drive word consisting of n 1 drive bits;
A coded output signal composed of a 0 drive word consisting of 0 drive bits and a 1 drive word consisting of n 1 drive bits is input, and the m-th (1 ≦ 1) 0 drive word of the coded output signal is input. The combination of the 0 drive bit of m ≦ n) and the mth drive bit of the 1 drive word of the same encoded output signal is expressed by any one of the logic signals 0, 1, X and Z. Decoding means for generating an output signal having an n-bit width by restoration, and the functional simulator means receives the coded input signal and outputs n coded bits of the coded input signal. ZX conversion means for generating a conversion coded input signal by converting coded bits corresponding to the logical signal Z into coded bits corresponding to the logical signal X, and the converted coded input signal. The encoded output by calculating the 0 drive word and the 1 drive word corresponding to the operation result of the logical operation that is the target of the functional simulation based on the 0 drive word and the 1 drive word of the conversion encoded input signal. A configuration having an output signal evaluation means for generating a signal is added.

The invention of claim 20 is, in the structure of the invention of claim 19, wherein the ZX conversion means receives an encoded input signal from the encoding means, and drives the encoded input signal by 0 drive. A logical sum of a word and one drive word of the same encoded input signal is calculated, and a logical sum evaluation means for outputting the calculation result as an intermediate result;
A bit inverting means for calculating a logical NOT of the intermediate result and outputting the operation result as a ZX conversion mask, the encoded input signal and the ZX conversion mask are input, and a 0 drive word of the encoded input signal is input. The logical sum of the ZX conversion mask is calculated, the calculation result is output as the 0 drive word of the conversion coded input signal, and the logical sum of the 1 drive word of the coded input signal and the ZX conversion mask is calculated. , ZX conversion mask processing means for outputting the operation result as one drive word of the same conversion encoded input signal is added.

The invention of claim 21 is, specifically, in the configuration of the invention of claim 8 or 9, wherein the functional design support device describes a test vector describing the contents of the test data based on the functional simulation result. The configuration further includes a test vector generating unit for generating

In a twenty-second aspect of the invention, specifically, in the configuration of the eighth or ninth aspect of the invention, the control means controls the function simulator control section for controlling the function simulator means and the input display means. The input display control unit is divided into two parts.

In a twenty-third aspect of the present invention, specifically, in the configuration of the eighth aspect of the invention, the function simulator means calculates a simulation time m × t (where m is 2) based on the state value at the simulation time T. Further, the control means further has a function of executing a time advance jump function simulation for obtaining a state value at a simulation time T + m × t by simulating the operation function of the logic circuit by the above integer). Forward step execution control means for controlling the execution of the time forward jump function simulation, forward jump execution control means for controlling the execution of the time forward jump function simulation, pattern setting control means for setting the test data in the functional simulator means, and the functional system. A configuration having a function simulation result fetch control means for fetching the simulation result from the function simulator means is added.

In a twenty-fourth aspect of the present invention, specifically, in the configuration of the ninth aspect of the invention, the functional simulator means is based on a state value at a simulation time T, and a simulation time m × t (where m is 2). Further, the time backward jump function simulation of the function simulator means is further provided by performing a time forward jump function simulation for obtaining a state value at a simulation time T + m × t by simulating the operation function of the logic circuit by the above integer). , Simulation time T
The time-reverse step function simulation for obtaining the state value at −t and the time backward jump function simulation for obtaining the state value at the simulation time T−L × t (where L is an integer of 2 or more) are provided. A forward step execution control means for controlling execution of the time forward step functional simulation, a forward jump execution control means for controlling execution of the time forward jump functional simulation, and a backward step for controlling execution of the time backward step functional simulation Execution control means, backward jump execution control means for controlling execution of the time backward jump functional simulation, and pattern setting control hand for setting the test data in the functional simulator means. If is intended to add a configuration and a function simulation result capture controls means for capturing the functional simulation results from the function simulator means.

According to a twenty-fifth aspect of the invention, specifically, in the configuration of the eighth or ninth aspect of the invention, the input display means inputs a table format pattern as the test data, and displays the functional simulation result as a table. The table format pattern input display means for displaying in a format is provided, and the control means is added with a configuration having a table format pattern input display control means for controlling the table format pattern input display means.

According to a twenty-sixth aspect of the present invention, specifically, in the configuration of the eighth or ninth aspect of the invention, the input / display means inputs a waveform format pattern as the test data, and outputs the functional simulation result as a waveform. A waveform format pattern input display means for displaying in a format is provided, and the control means is provided with a configuration having a waveform format pattern input display control means for controlling the waveform format pattern input display means.

According to a twenty-seventh aspect of the present invention, specifically, in the configuration of the eighth or ninth aspect of the invention, the input display means inputs a memory pattern of a memory of a logic circuit as the test data, and the functional simulation. The memory pattern input display means for displaying the resultant memory pattern is provided, and the control means is added with a configuration having a memory pattern input display control means for controlling the memory pattern input display means.

The invention of claim 28 is, specifically, in the configuration of the invention of claim 8 or 9, wherein the input display means displays past test data used in past execution of the function simulator means. Pattern history input display means for displaying in a format and inputting test data selected from the past test data as new test data, wherein the control means is a pattern for controlling the pattern history input display means. A structure having a history input display control means is added.

The invention of claim 29 is specifically directed to a functional design support method for supporting functional design of a logic circuit,
The test data input process for inputting test data, the time advance function simulation process for simulating the operation function of the logic circuit for a predetermined simulation time based on the input test data, and the time advance function simulation process. And a function simulation result display process for displaying the obtained function simulation result.

A thirty-third aspect of the present invention is specifically the configuration of the twenty-ninth aspect of the present invention, wherein the test data in the test data input process is a chart element such as a figure, a table, or a character indicating the operation function of the logic circuit. Is a functional diagram format pattern on the functional diagram expressed by, and the functional simulation result display processing adds a configuration for displaying the functional simulation result on the functional diagram.

Specifically, the invention of claim 31 is directed to a functional design support method for supporting functional design of a logic circuit,
The state values at all simulation times up to the current simulation time of the logic circuit are stored in advance, and the state values at the past simulation time of the logic circuit are set as the functional simulation results by returning the simulation time to the past simulation time. The configuration is provided with a time backward movement function simulation process to be obtained and a function simulation result display process for displaying the function simulation result obtained by executing the time backward movement function simulation process.

A thirty-second aspect of the invention is specifically the configuration of the thirty-first aspect of the invention, in which the time backward function simulation process is performed immediately before the logic circuit by returning the simulation time to the immediately previous simulation time. A configuration for obtaining the state value at the past simulation time as the result of the functional simulation is added.

The thirty-third aspect of the present invention is, specifically, in the configuration of the thirty-first aspect of the invention, wherein the functional simulation result display processing expresses the operation function of the logic circuit by a chart element such as a figure, a table or a character. A configuration for displaying the result of the functional simulation on the functional diagram is added.

Specifically, the invention of claim 34 is directed to a functional design support method for supporting functional design of a logic circuit,
A state value storage table capable of holding state values at all simulation times of the logic circuit is provided in advance, test data input processing for inputting test data, and the input test data are input to the simulation time of the logic circuit. A test data setting process for setting a state value in the state value storage table as a state value at T; a state value reading process for reading the state value from the state value storage table for holding the state value at the simulation time T of the logic circuit; The time advancing function simulation process for simulating the operation function of the logic circuit for a predetermined simulation time t based on the state value thus obtained, and the time advancing function simulation result obtained by the execution of the time advancing function simulation process. simulation And time forward function simulation result writing process for writing the state value to the state value storage table in time T + t, simulation time T + t of logic circuits written in the state value storage table
The time advance function simulation result display process for displaying the time advance function simulation result as a state value in the above, and the simulation time T + t is set as a new simulation time T after the execution of the time advance function simulation result display process. By repeatedly executing the reading process, the time advance function simulation process, the time advance function simulation result writing process, and the time advance function simulation result display process, the state value storage table is displayed at all simulation times up to the simulation time T0 of the logic circuit. The process of setting the state value and the current simulation time of the state value storage table are changed from the simulation time T0 to the simulation time T0-n × t (where n is 1 or more). Number) to obtain the state value at the simulation time T0-n × t of the logic circuit held in the state value storage table as the time backward function simulation result, and the time backward function simulation process. And a time-reverse function simulation result display process for displaying the time-reverse function simulation result obtained by executing the above.

A thirty-fifth aspect of the present invention is specifically the configuration of the thirty-fourth aspect of the present invention, wherein the test data in the test data input process indicates the operation function of the logic circuit as a graphic element such as a figure, a table or a character. Is a functional diagram format pattern on the functional diagram expressed by, the time forward function simulation result display process displays the time forward function simulation result on the functional diagram, the time backward function simulation result display process, A configuration for displaying the result of time backward function simulation on the functional diagram is added.

A thirty-sixth aspect of the present invention is, specifically, in the configuration of the first aspect of the invention, the functional design support apparatus is described by the function of inputting design constraint information from the outside and the functional diagram editor means. Design constraint information input means having a function of reading functional diagram information related to the functional diagram from the storage device and a function of setting design constraint information on the functional diagram, and design constraint information is set by the design constraint information input device. A design constraint information check unit that reads the functional diagram information regarding the created functional diagram from the storage device and verifies whether or not there is a contradiction in the design constraint information; and a functional diagram in which the design constraint information is set by the design constraint information input unit. A design constraint description word that reads functional diagram information from the storage device, analyzes the design constraint information on the functional diagram, and generates a design constraint description language. A conversion means, a language base function for inputting the function description language generated by the function description language conversion means and the design constraint description language generated by the design constraint description language conversion means, and performing a function simulation on the function description language. Further equipped with a simulator,
The functional simulation means reads the functional diagram information relating to the functional diagram in which the design constraint information is set by the design constraint information input device from the storage device, and performs a delay simulation on the functional diagram based on the design constraint information to perform timing. After verification, the logic synthesis means inputs the functional description language generated by the functional description language conversion means and the design constraint description language generated by the design constraint description language conversion means, and generates netlist information. The configuration is added.

According to a thirty-seventh aspect of the invention, specifically, in the configuration of the thirty-sixth aspect of the invention, the design constraint information input means has a function of inputting a periodic waveform to a clock input pin of a logic circuit and a functional diagram. And a function of setting a periodic waveform to the clock input pin of the register, the design constraint description language conversion means sets the register setup time and the register setup time for the periodic waveform set on the functional diagram by the design constraint information input means. A configuration for generating a design constraint description language for setting timing constraint information such as hold time in the logic synthesizing means is added.

A thirty-eighth aspect of the invention is specifically the configuration of the thirty-sixth aspect of the invention, wherein the design constraint information input means responds to a fan-out capacitance for an external input pin of the logic circuit and an external output pin of the logic circuit. It has a function of inputting a fan-in capacity, a function of setting a fan-out capacity for an external input pin on the functional diagram, and a function of setting a fan-in capacity for an external output pin on the functional diagram, The design constraint description language conversion means adds a configuration for generating a design constraint description language for setting the fan-out capacity and fan-in capacity information set on the functional diagram by the design constraint information input means in the logic synthesis means. To do.

A thirty-ninth aspect of the invention is specifically the configuration of the thirty-sixth aspect of the invention, in which the design constraint information input means is a terminal in the logic circuit that does not have a state value storage capability, and a storage unit. The function to input the delay value to the register and the external pin which are parts having the capability, the function to set the delay value to the terminal on the functional diagram, and the function to set the delay value to the register on the functional diagram. , A function to set a delay value to an external pin on the functional diagram, the functional simulation means based on the delay value set to the terminal, the register and the external pin on the functional diagram by the design constraint information input means. The delay simulation based on the delay value set on the functional diagram by the design constraint information input means is performed by the design constraint description language conversion means. It is intended to add a configuration for generating a design constraint description language to be set in the logic synthesis means.

Specifically, the invention of claim 40 is directed to a functional design support method for supporting functional design of a logic circuit,
Functional diagram creation processing that creates functional diagrams using figures, tables, characters, and other diagram elements, function diagram error check processing that verifies the existence of inconsistencies in the function diagrams, and function diagrams that use the chart elements Function constraint correction process, design constraint information input process for inputting design constraint information and setting the design constraint information on the function diagram, and design constraint information error check for verifying whether or not there is an error in the design constraint information Processing, design constraint information correction processing for correcting design constraint information on the functional diagram, functional verification processing for performing functional verification and timing verification of the logic circuit on the functional diagram from the functional diagram and the design constraint information, and the functional diagram. The configuration includes a function description language and a language conversion process for generating a design constraint description language from the design constraint information.

[0057]

According to the configuration of the invention of claim 1, by using the chart element such as the figure, the table or the character displayed on the screen of the display device,
The functional diagram editor means can create a functional diagram representing the operation of the logic circuit on the screen of the display device. In this way, it becomes possible to design the function of the logic circuit without using the function description language. Further, it is possible to automatically generate a function description language from the function diagram, and it is possible to obtain netlist information from the generated function description language.

With the configuration according to the second aspect of the present invention, it is possible to simultaneously describe a plurality of functional diagrams of the state transition diagram, the data path diagram, the truth table and the logical expression table on the multi-window of the display device. .

According to the configuration of the third aspect of the invention, in the functional design using the functional diagram information, the connection, definition and reference status of the functional diagram can be easily confirmed, and mistakes at the initial stage can be easily checked. is there.

According to the configuration of the invention of claim 4, in the functional design using the functional diagram information, from the functional diagram information, the functional description language suitable for the logic synthesis means is suitable for the logic synthesis or the language-based functional simulator. By creating a functional description language suitable for functional simulation, it is possible to obtain a circuit that guarantees the same operation in logic synthesis and functional simulation.

According to the configuration of the fifth aspect of the present invention, in the functional design using the functional diagram information, a functional description language suitable for a logic composition suitable for a circuit configuration to be realized after the logic composition is created from the functional diagram information. After logic synthesis, it is possible to obtain a logic circuit having a desired circuit configuration.

According to the configuration of the sixth aspect of the invention, in the functional design using the functional diagram information, the control unit of the circuit is changed to the state transition diagram function description language suitable for the state transition diagram oriented logic synthesis means,
Logic synthesis is performed by converting the data path portion of the circuit into a data path diagram functional description language suitable for data path oriented logic synthesis means, and by converting the random logic of the circuit into a combinational circuit functional description language suitable for random logic oriented logic synthesis means. After that, it is possible to obtain an optimum logic circuit.

According to the configuration of the invention of claim 7, in the functional design using the functional diagram information, a functional description language suitable for a logic composition suitable for a circuit configuration to be realized after the logic composition is created for each facility from the functional diagram information. After logic synthesis, a logic circuit having a desired circuit configuration for each facility can be obtained.

According to the configuration of the invention of claim 8, the functional simulation can be executed for a limited time,
The test data can be input each time, and the simulation result can be displayed each time. For this reason, it becomes possible to verify the operation function in the middle stage, and it is possible to detect an error in the test data early.

With the configuration according to the ninth aspect of the invention, the simulation time can be returned to the past. For this reason,
Since it is possible to execute the functional simulation again, it is not necessary to restart the functional simulation from time 0 even when the input test data has an error or when the input test data is desired to be changed.

According to the structure of the invention of claim 10, for example,
It becomes possible to input the test data and display the functional simulation result on the functional description language of the functional simulation target circuit displayed in the multi-window of the display device. Therefore, it is possible to easily verify the operation function of the circuit in the function description language.

According to the configuration of the invention of claim 11, for example,
It is possible to input patterns and display functional simulation results on the functional diagram of the functional simulation target circuit displayed in the multi-window of the display device. Therefore, it is possible to easily know the state value of each circuit model that operates in parallel, and it becomes easy to verify the operation function of the logic circuits that operate in parallel.

According to the twelfth aspect of the invention, for example,
It is possible to input patterns and display functional simulation results on the data path diagram of the functional simulation target circuit displayed in the multi-window of the display device. Therefore, it is possible to easily verify the operation function of the logic circuit on the data path diagram format representation diagram.

According to the configuration of the invention of claim 13, for example,
It is possible to input patterns and display functional simulation results on the state transition diagram of the functional simulation target circuit displayed in the multi-window of the display device. Therefore, it is possible to easily verify the operation function of the logic circuit on the state transition diagram format representation diagram.

According to the structure of the fourteenth invention, for example,
It is possible to input patterns and display functional simulation results on the logical expression form representation diagram of the functional simulation target circuit displayed in the multi-window of the display device. Therefore, it is possible to easily verify the operation function of the logic circuit on the logical expression form representation diagram.

According to the structure of the fifteenth aspect of the invention, for example,
It is possible to input a pattern and display the result of the functional simulation on the truth table format representation diagram of the functional simulation target circuit displayed in the multi-window of the display device. Therefore, it is possible to easily verify the operation function of the logic circuit on the truth table format representation diagram.

According to the structure of the sixteenth invention, for example,
On the simulation control panel displayed in the multi-window of the display device, it becomes possible to perform execution control of functional simulation and input control of test data. Therefore, it is possible to interactively execute the functional simulation.

According to the configuration of the seventeenth aspect of the invention, in the functional simulation processing, not only the time forward functional simulation, but also the time backward functional simulation can be quickly returned from the middle of the processing to the past time.

According to the eighteenth aspect of the present invention, in a memory element such as a register or a RAM which operates in synchronization with a rising or falling edge of a clock signal, when the clock signal and the input signal change at the same time, Even if there is a time difference between the event processing for a change in the clock signal and the event processing for a change in the input signal, the same functional simulation result can be obtained.

According to the structure of the nineteenth aspect of the invention, each bit of the input signal having a plurality of bit widths, which is represented by any one of the four values of the logical signals 0, 1, X and Z, is converted into a logical value by the encoding means. It is encoded by two bits, a 0 drive bit indicating whether 0 can be taken and a 1 drive bit indicating whether a logical value 1 can be taken. Further, in the coded input signal, the ZX conversion means converts the coded bit corresponding to the logical signal Z into the coded bit corresponding to the logical signal X. Based on the 0-drive word and the 1-drive word of the conversion-encoded input signal, the output signal evaluation means obtains and encodes the 0-drive word and the 1-drive word corresponding to the operation result of the logical operation that is the target of the functional simulation. Generate an output signal. At that time, since both drive words of the conversion encoded input signal are composed of binary logic signals of 0 and 1, all bits of the encoded output signal corresponding to the operation result of the logical operation to be the target of the functional simulation. Can be collectively obtained by a logical operation. 0 of the encoded output signal thus obtained
Each drive bit in the drive word and one drive word is converted by the decoding means into logical signals 0, 1, X.
, And Z, and the output signal is generated.

According to the twentieth aspect of the invention, the intermediate result output from the logical sum evaluation means becomes a ZX conversion mask in which each bit is inverted by the bit inverting means. Then, the ZX conversion mask processing means receives the encoded input signal and Z
The X conversion mask is input, the logical sum of the 0 drive word of the encoded input signal and the ZX conversion mask is obtained, and the logical sum of the 1 drive word of the encoded input signal and the ZX conversion mask is obtained. As a result, the former is output as the 0 drive word of the transform-coded input signal, and the latter is output as the 1 drive word of the transform-coded input signal. As a result, ZX for converting the coded bit corresponding to the logical signal Z in the coded input signal into the coded bit corresponding to the logical signal X
The conversion can be easily realized.

According to the twenty-first aspect of the present invention, a test pattern for a language-based functional simulator can be generated from a functional simulation result obtained by interactively functionally simulating test data input to interactively debug a logic circuit. . For this reason, it becomes possible to interactively create and modify test data while simultaneously debugging the logic circuit and verifying the operation function of the logic circuit.
It is possible to interactively create and modify test vectors for language-based functional simulators.

According to the structure of the twenty-second aspect, the control means is divided into an input display control section for controlling the input display means and a function simulator control section for controlling the function simulator means, whereby the function of the input display means is divided. When changing or adding functions, only the input display control unit needs to be changed, and it is possible to easily cope with the change without changing the function simulator control unit. Conversely, when changing the function of the function simulator means, adding a function, or replacing the function simulator means with another function simulator means, it is sufficient to change the function simulator control section and change the input display control section. Can be easily dealt with.

With the structure of the twenty-third aspect, it is possible to appropriately select and execute from the time forward step function simulation and the time forward jump function simulation. Also, for the function simulator means,
It is possible to set test data and capture functional simulation results.

According to the twenty-fourth aspect of the present invention, it is possible to appropriately select and execute the time forward step functional simulation, the time forward jump functional simulation, the time backward step functional simulation, and the time backward jump functional simulation. Further, it is possible to set the test data and take in the functional simulation result to the functional simulator means.

According to the structure of the twenty-fifth aspect of the invention, for example,
In the window of the display device, it becomes possible to input a table format pattern and display the functional simulation result. For this reason, it is possible to easily know the state value of each circuit model that operates in parallel from the table instead of the character arrangement,
It is possible to verify the operation function of the logic circuit more easily than the display of only characters.

According to the structure of claim 26, for example,
In the window of the display device, it is possible to input a waveform format pattern and display the functional simulation result. Therefore, it is possible to easily verify the operation function of the logic circuit as compared with the case of displaying only characters.

According to the structure of the invention of claim 27, for example,
With the cursor mode function, the copy function, the count function, and the change function, the memory pattern can be easily input, and the memory pattern can be displayed each time the functional simulation is executed. Therefore, it is possible to easily verify the operation function of the logic circuit including the memory.

According to the invention of claim 28, for example,
It is possible to display the test data input in the past in the window of the display device or to reuse the test data input in the past by selecting from the displayed test data. Therefore, when the functional simulation is re-executed, it is not necessary to manually input the test data from the beginning, and only by selecting the test data displayed by the pattern history input display means, the test data can be automatically converted into the functional simulator means. It is possible to transfer to and perform a functional simulation. Further, even if the selected test data has an error, it is only necessary to correct the error data in the displayed test data. Even if the logic circuit is changed, the functional simulation result of the previous functional simulation is saved in a file and the functional simulation result is loaded, so that the test data can be reused in the same manner.

According to the configuration of the twenty-ninth aspect of the invention, the functional simulation can be executed for a limited time, the test data can be input each time, and the simulation result can be displayed each time. For this reason,
It is possible to verify the operation function in the middle stage, and it is possible to detect an error in the test data at an early stage.

Further, with the configurations of the inventions of claims 31 and 32, it is possible to confirm the state value at the past simulation time. Therefore, for example, even if there is an error in the logic circuit or the test data, traceback can be easily performed in order to find the cause.

Further, according to the configuration of the thirty-fourth aspect of the present invention, it is possible to set the state values at all simulation times up to the current simulation time of the logic circuit in the state value storage table by repeatedly executing the functional simulation. The simulation time can be easily returned to the past by using such a state value storage table. Therefore, even if there is an error in the input test data or if it is desired to change the input test data, it is not necessary to perform the functional simulation again from time 0.

According to the inventions of claims 30, 33 and 35, for example, a pattern can be input and a result of the functional simulation can be displayed on the functional diagram of the functional simulation target circuit displayed in the multi-window of the display device. It will be possible. Therefore, it is possible to easily know the state value of each circuit model that operates in parallel, and it becomes easy to verify the operation function of the logic circuits that operate in parallel.

With the configurations of the thirty-sixth and forty-third aspects, design constraints such as timing constraint information, fan-out capacitance, fan-in capacitance, delay constraint information, etc. are provided on the functional diagram expressing the operation of the logic circuit. It becomes possible to set information.

According to the thirty-seventh aspect of the present invention, it is possible to set constraints such as the setup time and hold time of the registers of the logic circuit in the logic synthesizing means as design constraints.

According to the structure of the thirty-eighth aspect, it is possible to set the fan-out capacitance for the external input pin and the fan-in capacitance for the external output pin of the logic circuit as design constraints in the logic synthesizing means.

With the structure of the thirty-ninth aspect of the present invention, it is possible to set a delay value in a component forming a logic circuit, and to set this delay value in the logic synthesizing means as a design constraint.
Further, the function simulation means makes it possible to perform delay simulation on the functional diagram.

[0093]

【Example】

(First Embodiment) A functional design support apparatus according to a first embodiment of the present invention will be described below with reference to the drawings.

<Overall Structure of Functional Design Support Device> FIG.
It is a block diagram which shows the whole structure of the functional design assistance apparatus which concerns on a 1st Example.

In FIG. 1, 1 is an input device for inputting data from the outside.

Reference numeral 2 is a CRT monitor for displaying information.

Reference numeral 3 denotes a processing unit of the functional design support apparatus. The processing unit 3 includes a functional diagram information storage device 4, a functional diagram editor unit 5, a functional diagram checking unit 6, a functional simulation unit 7, and a functional description language conversion unit 8. It has and.

The functional diagram information storage device 4 stores the functional diagram information relating to the functional diagram which expresses the operation of the logic circuit in the form of figures, tables, characters and the like.

The function diagram editor section 5 stores the function diagram information on the screen of the CRT monitor 2 by using the figures, tables, characters, etc. and the function diagram information relating to the described function diagram. And a function of reading the functional diagram information from the functional diagram information storage device 4.

The functional diagram checking unit 6 reads the functional diagram information from the functional diagram information storage device 4 and verifies whether or not there is a contradiction in the functional diagram indicated by this functional diagram information. Here, the functional diagram information read is functional diagram information regarding the functional diagram described by the functional diagram editor unit 5, functional diagram information regarding the functional diagram described in another device, and the like.

The functional simulation unit 7 receives the functional diagram information about the functional diagram from the functional diagram information storage device 4 which has been verified by the functional diagram checking unit 6 for the presence or absence of contradiction and corrected by the functional diagram editor unit 5 to eliminate the contradiction. The function of the logic circuit is verified by reading and performing a functional simulation on this functional diagram.

The function description language conversion unit 8 reads the function diagram information relating to the function diagram whose function verification has been completed by the function simulation unit 7 from the function diagram information storage device 4, and generates the function description language from this function diagram.

Reference numeral 9 is a function description language generated by the function description language conversion unit 8.

Reference numeral 10 is a language-based functional simulator which receives the functional description language 9 and a test vector as input and performs high-speed functional simulation on the functional description language.

Reference numeral 11 is a test vector input to the language-based functional simulator 10.

Reference numeral 12 is a logic synthesizer, which is a function description language 9
Is input to generate netlist information.

Reference numeral 13 is netlist information generated by the logic synthesis unit 12.

FIG. 2 is a flow chart showing a functional design support method using the functional design support apparatus configured as described above.

As shown in FIG. 2, first, step SA1
At, the function diagram editor unit 5 creates a function diagram using figures, tables, characters and the like.

Next, in step SA2, the functional diagram checking unit 6 inputs the functional diagram created in step SA1 and verifies whether or not there is a contradiction in this functional diagram. Next, in step SA3, it is determined whether or not there is a contradiction in the functional diagram, and if there is no contradiction, step S3
On the other hand, if there is a contradiction while proceeding to A4, the process proceeds to step SA9, where the functional diagram is corrected using figures, tables, characters, etc., and the process returns to step SA2.

In step SA4, the functional simulation section 7 executes functional simulation on the functional diagram to verify the function of the logic circuit.

Next, in step SA5, it is determined whether or not there is an error in the operation of the logic circuit. If there is no error, the process proceeds to step SA6. If there is an error, the process proceeds to step SA9 and step SA9. At step SA2, the functional diagram is corrected using figures, tables, characters, etc. and the process returns to step SA2.

If there is a contradiction in the functional diagram or there is an error in the circuit operation represented by the functional diagram, the above steps SA2 to SA5 and SA9 are repeatedly executed.

When there is no contradiction in the functional diagram and there is no error in the circuit operation represented by the functional diagram, in step SA6, the function description language conversion unit 8
The function description language 9 is generated from the function diagram.

Next, in step SA7, the language-based function simulator 10 inputs the function description language 9 and the test vector 11 generated in step SA6 and performs a function simulation on the function description language.

Next, in step SA8, the logic synthesis unit 12 inputs the function description language 9 to generate the netlist information 13.

As described above, in the functional design support apparatus of this embodiment, the functional design of the logical circuit is realized by creating a functional diagram of the operation of the logical circuit by using figures, tables, characters, etc. without using the functional description language. It is possible to automatically generate a functional description language from the functional diagram, and it is possible to obtain netlist information from the functional description language generated by using the logic synthesis unit.

It should be noted that this embodiment can be realized by dedicated hardware or a computer having a CPU and a memory.

<Function Diagram Editor Unit> The details of the function diagram editor unit 5 of the functional design support apparatus according to the first embodiment will be described below.

FIG. 3 is a block diagram showing an example of the configuration of the functional diagram editor unit 5. In FIG. 3, reference numeral 4 denotes a functional diagram information storage device, which stores functional diagram information relating to a functional diagram that expresses the operation of a logic circuit in the form of figures, tables, characters,
It is similar to that shown in FIG.

The logic circuit can be designed separately for the control section for controlling the operation, the data path section for showing the flow of data, and the combinational circuit section. The functional diagram editor unit 5
Corresponding to the state transition diagram editor section 5a provided corresponding to the control section of the logic circuit, the data path editor section 5b provided corresponding to the data path section of the logic circuit, and the combination circuit section of the logic circuit. The combinational logic editor section 5c is provided, and the combinational logic editor section 5c has a truth table editor section 5d and a logical expression editor section 5e.

The state transition diagram editor unit 5a describes the control unit of the logic circuit on the multi-window of the CRT monitor 2 in the form of a state transition diagram. In addition, the state transition diagram editor unit 5a stores a function diagram in the form of the described state transition diagram in the function diagram information storage device 4, and a function diagram in the form of the state transition diagram from the function diagram information storage device 4. It has a reading function.

The data path editor section 5b describes the data path section of the logic circuit on the multi-window of the CRT monitor 2 in the form of a data path diagram showing the arrangement of the functional elements and the connection relationship between the functional elements. Further, the data path editor unit 5b has a function of storing the described functional diagram in the form of the data path diagram in the functional diagram information storage device 4 and reading the functional diagram in the form of the data path diagram from the functional diagram information storage device 4. With function.

The truth table editor section 5d describes the combination circuit section of logic circuits in the form of a truth table on the multi-window of the CRT monitor 2. In addition, the truth table editor unit 5d stores a function of storing the described functional diagram in the form of the truth table in the functional diagram information storage device 4 and a functional diagram in the form of the truth table from the functional diagram information storage device 4. It has a reading function.

The logical expression editor unit 5e describes, in the multi-window of the CRT monitor 2, a combinational circuit, which is difficult to be expressed by a truth table, among the combinational circuits of the logic circuit in the form of a logical expression table. Further, the logical expression editor unit 5e has a function of storing the described functional diagram in the form of the logical formula table in the functional diagram information storage device 4, and reads the functional diagram in the form of the logical formula table from the functional diagram information storage device 4. With function.

Reference numeral 2a is a state transition diagram window, CR
It is a window that displays a state transition diagram edited by the state transition diagram editor unit 5a among the windows forming the multi-window of the T monitor 2.

Reference numeral 2b is a data path diagram window, C
Of the windows forming the multi-window of the RT monitor 2, the window displays a data path diagram edited by the data path editor unit 5b.

2c is a truth table window, which is a CRT
Of the windows forming the multi-window of the monitor 2, it is a window for displaying a truth table edited by the truth table editor section 5d.

Reference numeral 2d denotes a logical expression window, which is a window for displaying a logical expression table edited by the logical expression editor unit 5e among the windows forming the multi-window of the CRT monitor 2.

As described above, in the functional design support apparatus of this embodiment, the CRT monitor 2 is used by using the state transition diagram editor section 5a, the data path editor section 5b, the truth table editor section 5d, and the logical expression editor section 5e. On the multi-window of, state transition diagram, data path diagram, truth table,
It is possible to describe the formula table and the formula table at the same time.

Here, a functional diagram described by each editor unit will be described with reference to FIGS. 4, 5, 6 and 7.

FIG. 4 is a concrete example of the state transition diagram described by the state transition diagram editor section 5a. In FIG. 4, reference numeral 300 designates a state transition clock signal, which designates a clock signal for controlling the state transition. A reset signal designation 301 describes a signal for forcibly returning the state of state transition to the initial state, and designates the initial state of state transition with an arrow. Reference numerals 302, 303, and 304 are states of state transition, and an arrow emerging from the state indicates a state transition destination. A state 302 is an initial state of state transition designated by the reset signal designation 301. Reference numerals 305 and 306 are arrows indicating unconditional state transitions, and indicate unconditionally transiting to the next state in synchronization with the clock signal designated by the state transition clock signal designation 300. Reference numeral 307 denotes a condition label of a conditional state transition. When the signal value of this condition label is 1, the state 302 changes from “START” to state 3
"ST1" of 03 indicates that the transition is made in synchronization with the clock signal designated by the state transition clock signal designation. An else label 308 is added to an arrow indicating a transition destination when an unconditional state transition does not occur and a conditional state transition does not occur.

FIG. 5 is a specific example of a data path diagram described by the data path editor section 5b. In FIG. 5, reference numerals 310 and 311 denote input pins for inputting signal values from the outside. An output pin 312 outputs a signal value to the outside. 313 and 314 are terminals. 315
Is a register, which stores the signal value in synchronization with the rising edge of the clock signal CLK, and resets the stored signal value to 0 when the reset signal RST is 1. 316, 31
Reference numerals 7 and 318 are arrows indicating unconditional propagation destinations of signal values, and indicate that signal values are unconditionally propagated. 319,
Reference numeral 320 denotes a condition label added to the conditional propagation destination arrow, and the conditional propagation destination arrow indicates that the signal value is propagated when the signal value of this conditional label is 1. Other,
The data path diagram is composed of a logical operation unit for performing an OR operation, an AND operation, an arithmetic operation unit for performing addition and subtraction, a comparison operation unit, a memory such as a RAM or a ROM, and a plurality of units. There are inter-page connectors, sub-modules, etc. for connecting signals that span the data path diagram of. In addition,
The logical operation unit includes a negative logic operation unit, a logical product operation unit,
There are a logical sum operator, an exclusive logical sum operator, a logical product negation operator, a logical sum negation operator, an exclusive logical sum negation operator, and the like. In addition, the arithmetic operation unit includes an incrementer, a decrementer, an adder without carry, an adder without borrow, an adder with carry, an adder with borrow, a multiplier, and a divider. , A shift calculator, etc. The comparison computing unit includes a magnitude comparison computing unit that compares the magnitudes of signal state values, a coincidence comparison computing unit that determines whether the signal state values are equal, and a decision whether the signal state values are not equal. There is a mismatch comparison calculator.

FIG. 6 is a specific example of the truth table described by the truth table editor section 5d. In FIG. 6, 3
Reference signal names 30, 331 describe the signal names referred to by the truth table. 332 and 333 are labels, and the signal values are determined by the conditions of the truth table. 334,
335, 336, and 337 are condition value fields, and describe a condition value. A plurality of conditions can be described in each condition value field, and in that case, the condition is the logical sum of the values of all the conditions described in the condition value field.
Reference numerals 338 and 339 denote logical product condition fields, which take a logical product of the condition values in the condition value field. In the case of this example, the activation condition of the label a is that sel1 is 0, and s
It means that el2 [1: 0] is 0 or 1.
The activation condition of label b is that sel1 is 1 and sel
2 [1: 0] is 2 or 3. The name of the state transition diagram can be described as the reference signal name, and in this case, the state name described in the state value transition diagram is described in the condition value field. In the truth table, it is possible to describe a plurality of reference signal names and labels.

FIG. 7 is a specific example of the logical expression table described by the logical expression editor section 5e. In FIG. 7, reference numerals 340 and 341 denote conditional expression fields in which a label name indicating a label and a conditional expression in which the condition for activating the label is expressed in the form of a logical expression are described. 342, 34
3 is a label name. 344 and 345 are conditional expressions,
It represents the conditions under which the label is activated. The logical symbols “&”, “|”, “==”, and “()” used in FIG.
Represents logical product, logical sum, comparison, and parentheses, respectively. The logical symbols that can be used in the drawings are not limited to those described above, and any symbol that represents a logical operation may be used.

In the truth table or logical expression table,
The condition for activating the condition label of the conditional state transition in the state transition diagram and the condition for activating the condition label added to the conditional propagation arrow in the data path diagram are defined.

<Function Diagram Checking Unit> Details of the function diagram checking unit 6 of the functional design support apparatus according to the first embodiment will be described below.

FIG. 8 is a block diagram showing an example of the configuration of the functional diagram check unit 6. In FIG. 8, reference numeral 4 denotes a functional diagram information storage device, which stores functional diagram information relating to a functional diagram expressing the operation of the logic circuit in the form of figures, tables, characters, etc., and is similar to that shown in FIG.

The functional diagram check unit 6 includes a check unit 20, a check result screen display unit 22, and a check result error report file creation unit 23.

The checking unit 20 includes the functional diagram information storage device 4
The function diagram information is read from, and whether or not there is an error in the function diagram indicated by this function diagram information is determined based on a check rule, and check result information 21 is created.

The check result screen display section 22 displays the check result information 21 on the screen of the CRT monitor 2 by reflecting the check result information 21 on the connection information, definition information, reference information, etc. for each circuit component. Cross-probing between the error location and the circuit component related to the error is possible.

The check result error report file creating section 23 creates a check result error report file 24 from the check result information 21.

On the screen of the CRT monitor 2, the functional diagram information includes a plurality of windows forming a multi-window, that is, a state transition diagram window showing a control part of a logic circuit and a data path showing a data path part of the logic circuit. It is embodied by a figure window and a truth table window or a logical expression window representing a combinational circuit portion of a logic circuit, and the same name in a plurality of windows is treated as the same component. 9 (a), 9 (b) and 9
FIG. 9C and FIG. 9D show this state.
9A is an example of a state transition diagram window, FIGS. 9B and 9C are examples of a data path diagram window, and FIG.
(D) shows an example of a truth table window. As shown in FIGS. 9A to 9D, for example, as shown in FIG.
The state transition diagram window (St_Machine) of (a) and FIG.
The condition label Label1 referred to in the data path diagram window (RT1) in (b) is the truth table window in FIG. 9 (d) using RegA in the data path diagram window (RT1) in FIG. 9 (b). Defined by (TABLE). Therefore, in addition to the conventional error check of the connection relation in one window, error check across a plurality of windows is required.

FIG. 10 is a block diagram showing an example of the configuration of the check unit 20 in the functional diagram check unit 6. In this example, in checking the functional diagram, it is possible to perform an error check across a plurality of windows.

In FIG. 10, reference numeral 21 represents check result information, which is the same as that shown in FIG.

In the functional diagram information storage device 4, as the functional diagram information, the state transition diagram information corresponding to the state transition diagram window 346, the data path diagram information corresponding to the data path diagram window 347, and the truth table window. Truth table information corresponding to 348 and logical expression information corresponding to the logical expression window 349 are stored.

The checking unit 20 includes a name error checking unit 20a, a name undecided checking unit 20b, a name duplication checking unit 20c, and a component non-connection checking unit 20d.
A bit width error check unit 20e and a condition label setting error check unit 20f.

The name error check unit 20a uses the state transition diagram information, the data path diagram information, the truth table information, and the logical expression information to determine whether there is a description error in the bit width definition following the name for all windows. , The presence or absence of an error that a reserved word is used in the name is checked, and if there is an error, that fact is output as the check result information 21.

The undetermined name checking unit 20b uses the state transition diagram information, the data path diagram information, the truth table information, and the logical expression information to determine the conditions referred to in the state transition diagram window 346 or the data path diagram window 347. It is checked whether or not the label is defined in the truth table window 348 or the logical expression window 349, and if it is undefined, the fact is output as the check result information 21.

The name duplication check unit 20c uses the state transition diagram information, the data path diagram information, the truth table information, and the logical formula information to determine whether the same name is defined for different types of parts for all windows. Whether or not the names are duplicated is output as check result information 21.

The component non-connection check unit 20d uses the state transition diagram information, the data path diagram information, the truth table information and the logical expression information to determine whether or not there is a state without a transition arrow in the state transition diagram window 346. Whether or not there is a functional element without a transfer arrow in the data path diagram window 347, and whether or not there is a label that is not referenced in any window in the truth table window 348 or the logical expression window 349. Respectively, and if they exist, check that information 2
Output as 1.

The bit width error checking unit 20e uses the data path diagram information, truth table information and logical expression information to
Whether or not there is a transfer arrow between the functional elements having different bit widths in the data path diagram window 347, or the functional element defined in the data path diagram window 347 is displayed in the truth table window 348 or the logical expression window 349. When referring to the part select, it is checked whether or not the selected bit is within the range of the bit width at the time of definition. If there is a bit width error, the fact is output as the check result information 21.

Condition label setting error check unit 20f
Uses the state transition diagram information and the data path diagram information to determine whether a condition label is set for all transition arrows of states having a plurality of transition destination states in the state transition diagram window 346, or the data path diagram. In the window 347, it is checked whether or not a condition label is set for all transfer arrows of the functional elements having a plurality of transfer source functional elements, and if there is an arrow for which no condition label is set, a check result to that effect is given. The information 21 is output.

For example, when the concrete contents of the function diagram information read from the function diagram information storage device 4 into the check unit 20 correspond to the window as shown in FIG. 10, a static error of the function diagram is generated. As the condition label Label5 referenced in the data path diagram window 347, the truth table window 348 and the logical expression window 349 are displayed.
Undefined error not defined in the table and 4 in the input of 8-bit adder Add1 in the data path diagram window 347
There are a bit width error in which the bit register RegB is connected and a condition label setting error in which there is a transition arrow in which no condition label is set in all transition arrows from the state St2 in the state transition diagram window 346. The error is output as the check result information 21, and this check result information 21 is displayed on the screen of the CRT monitor 2 by the check result screen display unit 22.

FIG. 11 shows a screen display of the check result information 21. In FIG. 11, 350 is state transition information, 351 is functional element connection information, and 352 is condition label definition and reference information. .

The state transition information 350 shows the transition destination state name of each state in the state transition diagram window 346. The functional element connection information 351 indicates a transfer source element name and a transfer destination element name for each functional element in the data path window 347, and also indicates a start signal name when the functional element is a storage element. The condition label definition and reference information 352 indicates the defined window name and the referenced window name for each label condition defined in the truth table window 348 or the logical expression window 349. The check result information 21 is added to the connection information, definition and reference information for each circuit component.

Here, when a label error in the screen display of the check result information shown in FIG. 11 is designated, the state St2 of the state transition diagram window 346 related to the label error is specified.
And the transition arrow from state St2 to state St4, which has no transition condition label, is highlighted. Further, when a bit width error in the screen display of the check result information shown in FIG. 11 is designated, the functional elements RegB and Add1 of the data path diagram window 347 and the transfer arrow between the functional elements regarding the bit width error are high. Light is displayed. When the condition label undefined error in the screen display of the check result information shown in FIG. 11 is specified, the condition label Label5 of the data path diagram window 347 regarding the condition label undefined error is displayed.
Is highlighted. In this way, the location where the error has occurred can be easily specified.

In addition to the highlighting display method, the error location display method includes a blinking display method and a color change display method. Any method can be used as long as the error location is clearly indicated.

As described above, in the functional design support apparatus of this embodiment, by providing the check unit 20, in the functional design using the functional diagram information, the check result is displayed on the screen to connect, define and The reference status can be easily confirmed, and the design error can be easily found by the screen display of the check result, the cross-probing display of the error part, and the output report file.

<Function Description Language Conversion Unit> The details of the function description language conversion unit 8 of the function design support apparatus according to the first embodiment will be described below.

Generally, in a functional description language, the support range for logic synthesis is narrower than the support range for language-based functional simulation, so the function description language generated for a language-based functional simulator is not available in the logic synthesis section. There is a problem that you can not enter. On the other hand, the functional description language generated for the logic synthesis unit can be input to the language-based functional simulator, but the execution speed of the functional simulation is higher than that when the functional description language generated for the language-based functional simulator is used. There is a problem of being late. Moreover, even if the same function description language is input to the logic synthesis unit and the language-based function simulator, the meaning of the operation in the logic synthesis unit and the meaning of the operation in the language-based function simulator are different. There is a problem that the function cannot be verified.

FIG. 12 is a block diagram showing an example of the configuration of the function description language conversion unit 8. This configuration example solves the above problems all at once.

In FIG. 12, 4 is a function diagram information storage device, 9 is a function description language, 10 is a language-based function simulator, and 12 is a logic synthesis unit, which is the same as that shown in FIG.

The function description language conversion unit 8 includes a logic synthesis function description language conversion unit 30 and a language base function simulator function description language conversion unit 31.

The logic synthesis function description language conversion unit 30 reads the function diagram information from the function diagram information storage device 4, and generates a logic synthesis function description language 32 suitable for the logic synthesis unit 12 from the function diagram information. Further, the logic synthesis function description language conversion unit 30 includes a logic synthesis unit 1 different from the logic synthesis unit 12.
It has a function of generating a logic synthesis function description language 32A suitable for 2A and a function of generating a logic synthesis function description language 32B suitable for a logic synthesis unit 12B different from the logic synthesis units 12 and 12A. There is.

The function description language conversion unit 31 for language-based function simulator reads the function diagram information from the function diagram information storage device 4, and the function description language for the language-based function simulator 10 suitable for the language-based function simulator 10 from this function diagram information. 33 is generated. Further, the function description language conversion unit 31 for language-based function simulator generates a function description language 33A for language-based function simulator suitable for the language-based function simulator 10A different from the language-based function simulator 10, and the language-based function. It has a function of generating a language-based functional simulator function description language 33B suitable for a language-based functional simulator 10B different from the simulators 10 and 10A.

As described above, in the functional design support apparatus of the present embodiment, the logic synthesis function description language conversion unit 30 can convert the function diagram information into a logic synthesis function description language suitable for the logic synthesis unit. At the same time, the function description language conversion unit 31 for language-based function simulator can convert the function diagram information into a function description language for language-based function simulation suitable for the language-based function simulator.
As a result, it is possible to obtain a circuit that operates in the logic synthesis unit and the language-based functional simulator in the same manner without considering the operation of each function description language, and the above problems can be solved at once.

FIG. 13 is a block diagram showing an example of the configuration of the logic synthesis function description language conversion unit 30 in the function description language conversion unit 8.

In FIG. 13, 4 is a functional diagram information storage device for storing functional diagram information, 30 is a logic synthesis function description language conversion unit, 32 is a logic synthesis function description language, and 12 is a logic synthesis unit. It is similar to that shown in FIG.

The function diagram information storage device 4 stores state transition diagram information 4a and data path diagram information 4b as function diagram information.
And truth table information 4c defining condition labels used in the state transition diagram information 4a or the data path diagram information 4b, and the state transition diagram information 4a or the data path diagram information 4b.
The logical expression information 4d that defines the condition label used in FIG.

The logic synthesis function description language conversion unit 30 includes a state transition diagram function description language conversion unit 40, a data path diagram function description language conversion unit 41, and a truth table function description language conversion unit 4.
2 and a logical function description language conversion unit 43.

44 is a state transition diagram function description language, 45 is a data path diagram function description language, 46 is a truth table function description language, and 47 is a logical expression function description language.

The logic synthesis unit 12 includes a state transition diagram-oriented logic synthesis unit 12a, a data path-oriented logic synthesis unit 12b, and a random logic-oriented logic synthesis unit 12c.

The state transition diagram function description language conversion unit 40 reads the state transition diagram information 4a from the function diagram information storage device 4, and uses this state transition diagram information 4a as a logic suitable for the state transition diagram suitable logic synthesis unit 12a. It is converted into the state transition diagram function description language 44 which realizes the state transition operation without contradiction by using the comment etc. which the state machine recognizes at the time of synthesis.

The data path diagram function description language conversion unit 41
The data path diagram information 4b is read from the function diagram information storage device 4, and the data path diagram information 4b is used for the data path operation suitable for the data path oriented logic synthesis unit 12b according to the change of the edge signal or the establishment of the transfer condition. It is converted into a data path diagram function description language 293 that is realized without contradiction.

The truth table function description language conversion unit 42 reads the truth value table information 4c from the function diagram information storage device 4, and the truth value table information 4c is stored in the random logic oriented logic synthesis unit 1.
The condition definition of the truth table information 4c suitable for 2c is converted into a truth table function description language 46 which is realized by a combinational circuit without contradiction.

The logical expression function description language conversion unit 43 reads the logical expression information 4d from the functional diagram information storage device 4, and converts this logical expression information 4d into the logical expression information 4d suitable for the random logic oriented logic synthesis unit 12c. The condition definition is converted into a logical expression function description language 47 which is realized by a combinational circuit without contradiction.

14 (a) and 14 (b) show specific examples of the operation of the state transition diagram function description language conversion unit 40, and FIG. 14 (a) shows information transitions indicated by the state transition diagram information. FIG. 14B shows a state transition diagram function description language obtained by converting the state transition diagram of FIG. 14A into a state transition diagram function description language.

For example, the state transition diagram function description language conversion unit 4
0 is a synthesis comment that is valid for the logic synthesis part for one state transition diagram, such as "// synopsys state_vector" and "//
"synopsys_enum" etc. are inserted, and registers "SMACHINE1", "S that indicate the current state and transition state of the state machine
14 by declaring "MACHINE1_next".
The state transition diagram of (a) is converted into the state transition diagram function description language of FIG. 14 (b).

FIGS. 15A and 15B show specific examples of the operation of the data path diagram function description language conversion unit 41, and FIG. 15A shows the data path indicated by the data path diagram information. FIG. 15B shows a data path diagram function description language obtained by converting the data path diagram of FIG. 15A into a data path diagram function description language.

For example, the data path diagram function description language conversion unit 41 uses the register RegA in the data path diagram of FIG.
15A is described by describing a statement that realizes an edge operation by a clock signal, a clear operation by a reset signal, a data transfer operation, and the like, and a statement that realizes an operation operation is described for the arithmetic unit Add1. 15 is converted into the data path diagram function description language of FIG. 15B.

16 (a) and 16 (b) show specific examples of the operation of the truth table function description language conversion unit 42, and FIG. 16 (a) shows the truth value indicated by the truth table information. The table and FIG. 16B show a truth table function description language obtained by converting the truth table of FIG. 16A into a truth table function description language.

For example, the truth table function description language conversion unit 42
Is a truth table function of FIG. 16 (b) that satisfies the constraints of the logical product and the logical sum, which means the logical product in the horizontal direction and the logical sum in the same item. Convert to description language.

FIGS. 17A and 17B show a concrete example of the operation of the logical expression function description language conversion unit 43.
17A shows a logical expression table indicated by logical expression information, and FIG. 17B shows a logical expression functional description language obtained by converting the logical expression table of FIG. 17A into a logical expression functional description language. There is.

For example, the logical expression function description language conversion unit 43.
Converts the logical expression table of FIG. 17A represented by a state machine and its state or by an operator into the logical expression function description language of FIG. 17B in consideration of the priority of the operator.

As described above, in the functional design support apparatus of this embodiment, the logic synthesis function description language conversion unit 30 causes the state transition diagram, data path diagram, truth table, or logical expression table indicated by the functional diagram information. It is possible to realize each operation in the above, without any inconsistency, and to convert to a function description language suitable for a state transition diagram dedicated, data path dedicated, or random logic dedicated logic synthesis unit, and obtain an optimum logic circuit after logic synthesis. it can.

FIG. 18 is a block diagram showing an example of the configuration of the data path diagram function description language conversion unit 41.

In FIG. 18, reference numeral 4 is a functional diagram information storage device for storing functional diagram information created by the functional diagram editor unit and error-checked by the functional diagram check unit without design error, and 48 is a desired circuit configuration and conditions. Desired circuit configuration information indicating the priority of the data path diagram functional description language 41, 45 data path diagram functional description language, 12
Represents a logic synthesizing unit and is similar to that shown in FIG.

The data path diagram function description language conversion unit 41
Non-priority selector configuration logic synthesis function description language conversion unit 41a, priority selection selector configuration logic synthesis function description language conversion unit 41b, non-priority tri-state configuration logic synthesis function description language conversion unit 41c, priority It is provided with a function description language conversion unit 41d for ordering tristate configuration logic synthesis.

45a is a function description language for selector configuration logic synthesis without priority, 45b is a function description language for selector configuration logic synthesis with priority, 45c is a function description language for tri-state configuration logic synthesis without priority, and 45d is priority order. Yes Represents a functional description language for tri-state logic synthesis.

The data path diagram function description language conversion unit 41
The functional diagram information is read from the functional diagram information storage device 4, and the conditional label transfer of the functional element in the data path diagram information of the functional diagram information becomes effective in the logic synthesis unit 12 in consideration of the desired circuit configuration information 48. It is converted into the data path diagram function description language 45 while inserting a synthetic comment.

FIG. 19, FIG. 20 (a), FIG. 20 (b), FIG. 21 (a) and FIG. 21 (b) show specific examples of the operation of the data path diagram functional description language conversion unit 41. FIG. 19 is a data path diagram indicated by the data path diagram information, and FIG.
FIG. 20A is a data path diagram function description language obtained by converting the data path diagram of FIG. 19 with a selector-configured logic synthesis function description language with priority, and FIG. 20B is a data path diagram function of FIG. 20A. A circuit obtained by logically synthesizing the description language, FIG. 21A is a data path diagram functional description language obtained by converting the data path diagram of FIG. 21B shows a circuit obtained by logically synthesizing the data description diagram function description language of FIG.

Here, a case will be described in which a data path diagram in which a plurality of conditions exist for transfer to the register RegA is converted into a data path diagram function description language realized by a selector.

The priority of the condition label is Label1, Label2,
In the case of else, the selector-configured logic synthesis function description language conversion unit 41b with priority order converts the operation in the register into a data path diagram function description language as shown in FIG. Then, for example, one logic synthesizing unit logically synthesizes the description of the condition labels below the case statement in the data path diagram functional description language of FIG. 20A as if they are described in descending order of priority. Therefore, in the logic synthesis result, as shown in FIG.
It becomes a logic circuit that realizes the condition transfer operation to the register.

Further, when the default is set to else without setting the priority of the condition label, the non-priority selector configuration logic synthesis function description language conversion unit 41a indicates the operation in the register as shown in FIG. Data path diagram function description language. When converting the function description language, "//
When “synopsys parallel_case” and a logic synthesis comment are inserted, for example, one logic synthesis unit realizes a case statement as a demultiplexer by this synthesis comment. Therefore, the logic synthesis result is shown in FIG. As shown in, the logic circuit realizes the operation of condition transfer to the register, which has no priority.

The present embodiment can be easily applied to the case where a circuit configuration other than the selector and the tristate is set in the circuit configuration of the circuit configuration information.

As described above, in the functional design support apparatus of this embodiment, the data path diagram function description language conversion unit 41 transfers the condition label in the functional element of the data path diagram indicated by the function diagram information after the logic synthesis. Since the data path diagram functional description language can be converted in consideration of the circuit configuration to be realized and the condition priority order, a logic circuit having a desired circuit configuration can be obtained after the logic synthesis.

FIG. 22 is a block diagram showing another example of the configuration of the data path diagram function description language conversion unit. here,
The same parts as those shown in FIG. 18 are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 22, the functional diagram information storage device 4 is shown.
Stores functional diagram information including circuit model type information for each facility, which is error-checked by the functional diagram check unit 6 and has no design error.

Data path diagram Function description language conversion unit 41A
Is a non-priority selector configuration logic synthesis function description language conversion unit 41a, a priority order selector configuration logic synthesis function description language conversion unit 41b, and a non-priority tri-state configuration logic synthesis function description language conversion unit 41c. , A tristate configuration logic synthesis function description language conversion unit 41d with priority, and a circuit model type discriminator 49.

The circuit model type discriminator 382 discriminates the circuit model type set for each facility (register or terminal) based on the circuit model type information in the functional diagram information. Then, the data path diagram function description language conversion unit 41A inserts a synthesis comment that is valid in the logic synthesis unit 12 in consideration of the circuit configuration to be realized by logic synthesis and the priority order of conditions for each circuit model type. Meanwhile, the data path diagram information in the function diagram information is converted into the data path diagram function description language 45.

23, 24 (a), 24 (b) and 25 show specific examples of the operation of the data path diagram function description language conversion unit 41A, and FIG. 23 is shown by the data path diagram information. FIG. 24 (a) is a data path diagram shown in FIG. 24. FIG. 24 (a) is a selector configuration logic synthesis function description language with priority obtained by converting the register RegA in the data path diagram of FIG. Figure 24
FIG. 25B is a priority-less tristate configuration logic synthesis function description language obtained by converting the register RegB in the data path diagram of FIG. 23 by a priorityless tristate configuration logic synthesis function description language, and FIG. 24. (a) Function selector language for selector configuration logic synthesis with priority and FIG.
3B shows a circuit obtained by logically synthesizing the non-priority tristate configuration logic synthesis function description language of FIG.

Here, a data path diagram in which there are a plurality of conditions for transfer to the registers RegA and RegB is shown in the register R
A case of converting egA and RegB into a data path diagram functional description language realized by different circuit configurations will be described.

The desired circuit configuration information after logic synthesis of each facility of the data path diagram information in the functional diagram information is RegA.
Then, it is assumed that the transfer condition is a selector configuration with higher priority, and R
In the case of egB, it is assumed that the transfer condition has a tri-state structure with no priority, and the condition labels are L1, L2, and L3. The circuit model type discriminator 49 discriminates the model type of the desired circuit, and for RegA, the selector with priority order is selected by the selector for logical configuration description logic for logical synthesis 41b with priority order as shown in FIG. A configuration logic synthesis function description language is created, and for RegB, a priority-less tristate configuration logic synthesis function description language conversion unit 41c is used for priority-free tristate configuration logic synthesis as shown in FIG. A functional description language is created. The logic synthesis is performed by the logic synthesis unit 12, and as shown in FIG. 25, from the selector configuration with priority order logic synthesis function description language of FIG. By providing “wire” as in the function description language for tri-state configuration logic synthesis without priority in FIG. 24B, the logic synthesis result of Reg B realizes a tri-state configuration. It becomes a logic circuit.

The present embodiment can be easily applied to the case where a circuit configuration other than the selector and the tristate is set in the circuit configuration of the circuit configuration information.

As described above, in the functional design support apparatus of this embodiment, the data path diagram functional description language conversion unit 41A
For each functional element of the data path diagram indicated by the function diagram information, the condition label transfer can be converted into the data path diagram function description language in consideration of the circuit configuration and the condition priority order to be realized after the logic synthesis. After combining, a logic circuit having a desired circuit configuration can be obtained for each functional element.

<Function Simulation Unit> The details of the function diagram simulation unit 7 of the function design support apparatus according to the first embodiment will be described below.

First, the overall structure of the functional simulation section 7 will be described with reference to FIG.

FIG. 26 is a block diagram showing the overall structure of the function simulation section 7. In FIG. 26, 4
Is a functional diagram information storage device, which stores functional diagram information which is information regarding a functional diagram in which the functional operation of the logic circuit is designed by using figures, tables, characters and the like. As the function diagram information, in addition to information such as figures, tables and characters for expressing the function diagram, terminals for function simulation, registers that store state values, and bits that transfer signal values in bit units, for functional simulation. Device information about devices such as connectors, logic calculators, arithmetic calculators, comparison calculators, memories, state machines, truth tables, and logical expressions, and the signals obtained by evaluating the devices. The signal information regarding the state value and the fan-out information indicating the element information of the element to be evaluated next when the state value of the signal changes are stored. Note that the logical operation unit includes a negative logical operation unit, a logical product arithmetic unit, an logical sum arithmetic unit, an exclusive logical sum arithmetic unit, an logical product negation arithmetic unit, an logical sum negation arithmetic unit, and an exclusive logical unit. There is a logical sum negation operator. In addition, the arithmetic operation unit includes an incrementer, a decrementer, an adder without carry, an adder without borrow, an adder with carry, an adder with borrow, a multiplier, and a divider. , A shift calculator, etc. The comparison computing unit includes a magnitude comparison computing unit that compares the magnitudes of signal state values,
There are a coincidence comparison arithmetic unit that determines whether the signal state values are equal, a non-coincidence comparison arithmetic unit that determines whether the signal state values are not equal, and the like. RAM and RO
There are M etc.

Reference numeral 50 denotes a function simulator section, which receives function diagram information and performs a function simulation. The function simulator unit 50 performs backward execution for returning the simulation state to the past and forward execution for advancing in the future time direction.

Reference numeral 51 is functional simulation result information, which is the result information of the functional simulation performed by the functional simulator section 50. As the functional simulation result information 51, at all simulation times,
State value of all signals, periodic pattern setting, RAM and RO
A memory pattern that is data of memory such as M, a force setting for forcibly setting a signal state to a certain state value,
Information such as unforce setting for releasing it is stored.

Reference numeral 52 denotes an input display section for displaying the result of function simulation performed by the function simulator section 50 and inputting test data and control commands to be input to the function simulator section 50. Each time the simulation is executed, the window of the CRT monitor 2 and the input device 1 are used for interactive execution. As the test data, there are a test pattern input to the signal state value, a periodic pattern representing a periodic test pattern such as a clock, a memory pattern which is pattern data of a memory, and the like. Below, the test data is
A test pattern, a periodic pattern, and a memory pattern are shown. The control command for the function simulator unit 50 includes a forward step execution command for instructing the time advance step execution of the function simulator unit 50, a forward jump execution command for instructing the time advance jump execution of the function simulator unit 50, and a function simulator. A backward step execution command for instructing the time backward step execution of the unit 50, a backward jump execution command for instructing a time backward jump execution of the functional simulator section 50, a test data input command for inputting test data to the functional simulator section 50, There is a function simulation result import command and the like for importing the result of the function simulation by the function simulator unit 50. Further, as the test data input command, a test pattern input command for inputting a test pattern to be input to a signal state value to the functional simulator unit 50 or a periodic pattern representing a periodic test pattern such as a clock is the functional simulator unit 50. There is a periodic pattern input command input to the function simulator 50 and a memory pattern input command inputting a memory pattern, which is pattern data of the memory, to the function simulator unit 50. As a display method, there are a display of signal values in a table format, a display on a functional diagram, a display in a waveform format, and the like.

Reference numeral 53 is a control unit, which controls the flow of data and commands between the function simulator unit 50 and the input display unit 52, and controls the execution of the function simulator unit 50 and the input display unit 52.

Next, the operation of the functional simulation section 7 configured as described above will be described.

When the control unit 53 controls the input, the input display unit 52 inputs test data, control commands for the functional simulator, etc. from the input device 1, and the control unit 53 controls the data transfer. Test data, control commands, etc. are input to the function simulator 50, and the function simulator unit 50 executes the function simulation. Then, the function simulation result executed by the function simulator unit 50 is transferred to the input display unit 52 by the control unit 53 and displayed on the CRT monitor 2. Here, input of test data, control commands, etc. can be performed each time the functional simulation is executed by the input control of the control unit 53, and display of the functional simulation result is executed by the data transfer control of the control unit 53. You can do it each time. Therefore, it is possible to interactively execute the functional simulation.

As described above, in the functional design support apparatus of the present embodiment, the functional simulation section 7 can input the test data each time while performing the functional simulation and display the simulation result on the functional diagram each time. It is possible. Further, at the past time, if an error in the input test data is found or if different test data is desired to be input, the simulation time can be returned to an arbitrary past time.

Details of the function simulator section 50 included in the function simulation section 7 will be described below with reference to the drawings.

First, the structure of the function simulator section 50 will be described with reference to FIG.

FIG. 27 is a block diagram showing the structure of the function simulator section 50. In FIG. 27, reference numeral 60 denotes a state value storage table, and as shown in FIG. 28, the state value change history at all times is held for each model constituting the circuit. Reference numeral 61 denotes a state value updating unit, which updates the state value storage table 60 during execution of the time advance simulation, and 62
Is a reverse time selection unit, which returns the time in the state value storage table 60 when the time reverse simulation is executed.

During execution of the time advance simulation, the state value updating unit 61 controlled by the control unit 53 changes the state values of all models in the circuit generated in the simulation process at a certain time interval (a unit time or a change in the signal value of the model occurs. At intervals of different times), the time and the state value at that time are added to the state value storage table 60 by the model number. On the other hand, when the time backward simulation is executed, the time in the state value storage table 60 is changed to the past target time by the backward time selecting unit 62 controlled by the control unit 53.

In the state value updating unit 61, 63 is an event list in which an event for storing state value change information is registered. An event processing unit 64 takes out an event from the event list 63, selects a process according to the type of the event, and updates the state value. 65 is
The evaluation unit evaluates elements that may cause a new state value change to update the state value of the event processing unit 64. If a new state value change occurs, the change information is used as the event list. Register at 63. Reference numeral 66 is circuit information in which functional diagram information is processed, fetched, and stored.

Next, a specific functional simulation operation by the functional simulator section 50 will be described with reference to FIG.

FIG. 29 is a specific example of the state value storage table 60 and shows changes in the state value due to the functional simulation operation. As shown in FIG. 29, from time T1 to T
In the execution of the time advance simulation to 2, the state value update unit 61 causes the state value storage table 60 to store the new time T2.
And the state values V12, V22, and V at time T2
Add 32. Execution of the time backward simulation from time T4 to T2 is realized by the backward time selecting unit 62 only by returning the time of the state value storage table 60 from T4 to T2, and the state value of each model becomes V12, V22, V32. .

Incidentally, in the past, in order to obtain the state value of the model other than the designated observation point, the simulation had to be executed again, but the state value storage table 60
By using, the state value of the signal not designated as the observation point can also be obtained.

Further, both the time forward and time backward simulations can be executed by skipping not only one unit time interval but several unit time.

As described above, in the functional simulation section 7, the functional simulator section 50 is provided with the state value storage table 60 for holding the state value change history in each circuit model, thereby interactively debugging the logic circuit. At this time, the time backward simulation can be quickly returned to the past time and the time forward simulation can be executed again, so that the verification efficiency of the operation function of the logic circuit can be improved.

Next, a specific time advance simulation operation by the state value updating section 61 of the function simulator section 50 will be described with reference to FIGS. 30 (a) and 30 (b).

FIG. 30A shows a logic circuit which is the target of the time advance simulation, and FIG.
The input data and the simulation result are shown. Here, the logic circuit that is the target of the time advance simulation is a register having an input signal Din, an output signal Dout, and a clock signal CLK, as shown in FIG. This register stores the value of the input signal Din in synchronization with the rising edge of the clock signal CLK and outputs it as the output signal Dout.

In FIG. 30B, reference numeral 360 is the waveform of the clock signal CLK. 361 is an input signal Din
Is the waveform of. Here, the change of the state value of the input signal Din and the rising of the clock signal CLK occur simultaneously.

Reference numeral 362 denotes the state value of output signal Dout in the case where the evaluation section 65 performs the element evaluation based on the state value change of clock signal CLK and then the element evaluation based on the state value change of input signal Din. Shows changes. Reference numeral 363 indicates a change in the state value of the output signal Dout when the evaluation unit 65 performs the element evaluation based on the state value change of the input signal Din and then the element evaluation based on the state value change of the clock signal CLK. ing.

In the conventional case, since the evaluation of the element is not controlled according to the type of event, it is not uniquely determined which of the state value change 362 and 363 of the output signal Dout is taken. However, in this embodiment, even if the input signal Din of the register and the clock signal CLK change at the same time,
Since the state value of the input signal Din is always updated after the element evaluation is performed according to the state value change of the clock signal CLK, the state value change of the output signal Dout of the register in FIG. , The result is unique.

As described above, in the function simulation section 7, by providing the function simulator section 50 with the state value updating section 61 having the event processing section 64,
When the clock signal and the input signal change at the same time in a storage element that operates in synchronization with the rising or falling edge of the clock signal such as a register or a RAM, the event processing and the input signal change due to the change of the clock signal Even if there is a time difference between the event processing and the event processing, it is possible to obtain the same functional simulation result. In addition, even if the registers and the like are connected one after another, such as pipeline operation, the operation works properly.

FIG. 31 is a block diagram showing the structure of the event processing unit 64. In FIG. 31, 70 is an event extraction processing unit that extracts events one by one from the event list 63. An event type determination processing unit 71 determines the type of the event extracted by the event extraction processing unit 70 and determines the subsequent processing. Reference numeral 72 is a normal event processing unit that updates the state value, 73 is a clock event processing unit that updates the state value of the clock signal, and 74 is a register input that updates the state value of the input data signal of the register. It is a data event processing unit.

As a result of the determination of the event type by the event type determination processing unit 71, if the event is for a state value other than the clock signal and the input signal of the register, the normal event processing unit 72 immediately determines the state value. Update. When the event is a change in the state value of the clock signal, the clock event processing unit 73 updates the state value of the clock signal after the event processing by all the normal event processing units 72 is completed. When the event is a change in the state value of the input data signal of the register, after the event processing by all the normal event processing units 72 and the event processing by all the clock event processing units 73 are completed, the register input data event processing unit 74 The state value of the input data signal of the register is updated by.

FIG. 32 is a block diagram showing a configuration example of the evaluation unit 65.

In the functional simulation of a circuit, for example, when simulating a logical operation circuit, it is not necessary to handle a binary logical operation consisting of logical signals 0 and 1, and various states in an actual circuit may be used. It is necessary to consider and simulate. That is, in an actual circuit, a logic signal is a don't care (hereinafter represented by a symbol X) or a high impedance (hereinafter represented by a symbol Z). Therefore, in a functional simulation, for example, a logic value is 0. ,
It becomes necessary to handle it as a four-valued logic signal that takes any one of 1, X, and Z.

Here, an example of an evaluation unit for evaluating a logical operation circuit for performing a logical operation between multi-bit width input signals represented by such a four-valued logical signal will be described.

In FIG. 32, the evaluation section 65 includes a logical operation evaluation section 81 having a ZX conversion section 82 and an output signal evaluation section 83, and an arithmetic operation evaluation section 80 for evaluating an arithmetic operation circuit. The display unit 52 includes an encoding unit 84 and a decoding unit 85. Each input signal of the input signal group input from the input device 1 is encoded by the encoding unit 84,
The encoded input signal group is sent to the logical operation evaluation section 81 via the control section 53. Then, the logical operation evaluation unit 81
, Each encoded input signal of the encoded input signal group is ZX
The conversion result is converted by the conversion unit 82, and the operation result of the logical operation is obtained by the output signal evaluation unit 83 and output as a coded output signal group. The encoded output signal group is sent to the decoding unit 85 via the control unit 53, is decoded by the decoding unit 85, and is displayed on the CRT monitor 2 as an output signal group.

The encoding unit 84 has a logical signal of 0 for each bit.
An input signal group including a plurality of multi-bit width input signals represented by any one of four values of 1, X, and Z is input from the input device 1, and for each bit of each input signal of the input signal group, A drive bit indicating whether the bit can take the logic signal 0 and a bit 1 indicating whether the bit can take the logic signal 1
It is encoded by two bits including a drive bit.

FIG. 33 shows the input / output correspondence when the encoding unit 84 performs encoding. In FIG. 33,
The “logic signal” indicates four values of 0, 1, X (don't care), and Z (high impedance). "0 drive bit"
Indicates that there is a high possibility that the corresponding "logic signal" will take a logical value of 0 when "1", and that there is a small possibility that it will take a logic signal 0 when "0". A "bit" indicates that the corresponding "logic signal" is likely to take a logical value of 1 when "1", and conversely has a low possibility of taking a logical value of 1 when "0".

Further, FIG. 34 shows a specific example of encoding for a logical signal having a 4-bit width. In FIG. 34, “logic signal” is an example of a 4-bit width logic signal,
It is "01XZ". The "0 drive word" is a collection of 0 drive bits when each bit is encoded, and the "1 drive word" is a collection of 1 drive bits when each bit is encoded.

When the logical signal "01XZ" is encoded in accordance with the encoding correspondence shown in FIG. 33, the encoded signal is two drive words of 0 drive word "1010" and 1 drive word "0110". Represented by a word. The result of encoding the input signal (group) by the encoding unit 84 as described above is the encoded input signal (group).
Call.

The ZX conversion section 82 receives the coded input signal group and, for each bit of each coded input signal, when the bit is a coded bit for the logical signal Z, sets the coded bit to the logical signal X. Convert to encoded bits for. The result of conversion of the coded input signal (group) by the ZX conversion unit 82 is referred to as a conversion coded input signal (group). FIG. 35 is a block diagram showing a detailed configuration example of the ZX conversion unit 82. Here, the ZX converter 82 does not need to perform ZX conversion for each bit and is configured to perform ZX conversion collectively.

In FIG. 35, reference numeral 90 denotes a logical sum evaluation unit, which inputs the coded input signal group coded by the coding unit 84 of FIG. 32 and inputs 0 drive word and 1 drive word of each coded input signal. And the logical sum of. The result obtained by the logical sum evaluation unit 90 from the encoded input signal is called an intermediate result.

Reference numeral 91 is a bit inversion unit which inputs an intermediate result and obtains bit inversion of each bit of the intermediate result.
The result obtained by the bit inverting unit 91 from the intermediate result is called a ZX conversion mask.

Reference numeral 92 denotes a ZX conversion mask processing section, which inputs a coded input signal and a ZX conversion mask, obtains a logical sum of the 0 drive word of the coded input signal and the ZX conversion mask, and coded the input. The logical sum of one drive word of the signal and the ZX conversion mask is calculated. Then, a conversion coded input signal having the former logical sum result as 0 drive word and the latter logical sum result as 1 drive word is output.

The output signal evaluation section 83 inputs the transform coded input signal group, evaluates the function of the logical operation (simulation) using the 0 drive word and the 1 drive word of each transform coded input signal, An encoded output signal consisting of 0 drive word and 1 drive word representing the evaluation result is obtained and output. The evaluation (simulation) referred to here is performed corresponding to various logical operations including multiple bit widths, multiple inputs and multiple outputs.

Here, regarding the evaluation of the function of the logical operation,
This will be described more specifically.

(1) When evaluating the logical product operation of 2 inputs and 1 output, the 0 drive word of the encoded output signal is 0 drive words of the conversion encoded input signal A and 0 of the conversion encoded input signal B. It is obtained by taking the logical sum with the drive word. Further, one drive word of the encoded output signal is obtained by taking the logical product of one drive word of the conversion encoded input signal A and one drive word of the conversion encoded input signal B.

(2) When evaluating the logical OR operation of 2 inputs and 1 output, the 0 drive word of the encoded output signal is 0 drive words of the conversion encoded input signal A and 0 of the conversion encoded input signal B. It is obtained by taking the logical product with the drive word. Further, one drive word of the encoded output signal is obtained by taking the logical sum of one drive word of the conversion encoded input signal A and one drive word of the conversion encoded input signal B.

(3) When evaluating the logical NOT operation,
The 0 drive word that collects the 0 drive bits of the encoded output signal is the 0 drive word and the 1 of the conversion encoded input signal.
It is obtained by exchanging the drive word.

The decoding section 85 inputs the coded output signal group, and outputs each coded output signal consisting of 0 drive word and 1 drive word as one of four values of logical signals 0, 1, X and Z. Decode into the represented output signal.

Next, the evaluation unit 65 configured as described above.
The operation of will be described.

FIG. 36 is a schematic diagram showing a process in which each signal group is converted. Here, as an operation example to be subjected to functional simulation, 2-input 1 with 4-bit width
Take output AND operation.

As shown in FIG. 36, first, the input signal group is a 4-bit input signal A whose logical value is "01XZ".
And a 4-bit input signal B whose logical value is "0101"
And two input signals to be calculated. This input signal group is processed by the encoding unit 84 as shown in FIG.
3 is converted into a coded input signal group according to the coding correspondence shown in FIG. That is, the input signal A has a logical value of “10”.
0 drive word which is 10 "and logical value is" 011 "
Is converted into a coded input signal A consisting of 0 drive word and 1 drive word. Similarly, the input signal B is converted into a coded input signal B consisting of 0 drive word “1010” and 1 drive word “0101”. It is converted (see the “coded input signal group” in FIG. 36).

Next, this coded input signal group is converted into a coded input signal group by the ZX conversion section 82.

FIG. 37 shows the process of ZX conversion of the input signal A by the ZX conversion unit 82 of FIG.

In FIG. 37, the "logic signal" is the input signal A, and the "coded input signal" is the coded input signal A obtained by coding the input signal A. From the encoded input signal A, the logical sum evaluation unit 90 outputs 0 drive word “10”.
The logical sum of 10 ”and one drive word“ 0110 ”is obtained to obtain the intermediate result“ 1110 ”(see“ Intermediate result ”in FIG. 37).

Furthermore, from this intermediate result "1110",
The ZX conversion mask "0001" in which each bit is inverted is obtained by the bit inversion unit 91 (see "ZX conversion mask" in FIG. 37).

Subsequently, the ZX conversion mask processing section 92 performs conversion code on "1011" obtained by ORing the 0 drive word "1010" of the encoded input signal A and the ZX conversion mask "0001". Set as 0 drive word of the encoded input signal A, and "0111" obtained by ORing the 1 drive word "0110" of the encoded input signal A and the ZX conversion mask "0001" is converted and encoded and input. It is set as one drive word of the signal A (refer to "transform coded input signal" in FIG. 37).

In the above ZX conversion mask, logical value 1
Is a bit corresponding to the logical value Z in the original input signal. Therefore, by taking the logical sum of each drive word of the encoded input signal and the ZX conversion mask,
The coded bits for the logical signal Z have been converted into the coded bits for the logical signal X. The “logic signal corresponding to the transform-coded input signal” in FIG. 37 is the “transform-coded input signal” inverse-coded (decoded) based on the coding correspondence shown in FIG. 33. Z in the "logic signal" is converted to X.

Similarly, for the encoded input signal B, Z
The Z conversion unit 82 performs the ZX conversion as described above.

As a result of the ZX conversion, the first bit of the encoded input signal A is converted into the encoded bit for the logical signal X, and the 0 drive word of the converted encoded input signal A is "1".
011 ”, one drive word becomes“ 0111 ”, because the first bit of the input signal A is the logical signal Z. Further, the encoded input signal B remains as it is, and the conversion encoding input is performed. 0 drive word of signal B is “10
10 "and one drive word are" 0101 "because the input signal B does not have the logical signal Z (see" Conversion-encoded input signal group "in FIG. 36).

As described above, the ZX conversion section 82 converts the logic signal Z into the logic signal X by batch processing without performing ZX conversion for each bit.

After that, with respect to the transform-coded input signal A and the transform-coded input signal B, the output signal evaluation section 83 evaluates (ie, simulates) various logical operations using these as inputs.

To simulate the 2-input 1-output logical product operation in this embodiment, if at least one of the two input signals is 0, the operation result is 0. Therefore, the logical value 0
The logical sum of the 0 drive bits that are likely to be is the 0 drive bit of the operation result, and the operation result is 1 if both of the two input signals are 1, so the logical value 1
The logical product of the 1 drive bits with high probability is 1 drive bit of the operation result. That is, the 0 drive word of the encoded output signal corresponding to the operation result is obtained by the logical sum of the 0 drive words of the transformed encoded input signal A and the converted encoded input signal B. Further, one drive word of the encoded output signal corresponding to the operation result is obtained by the logical product of the one drive words of the transformed encoded input signal A and the converted encoded input signal B.

In the example of FIG. 36, the 0 drive word of the encoded output signal is the 0 drive word “1011” of the conversion encoded input signal A and the 0 drive word “1010” of the conversion encoded input signal B. The logical sum “1011” is obtained, and one drive word of the encoded output signal is equal to one drive word “0111” of the conversion encoded input signal A.
One drive word “0101” of the conversion encoded input signal B
And the logical product “0101” (see “Encoding output signal group” in FIG. 36).

Finally, each coded bit of each coded output signal of the coded output signal group is decoded by the decoding unit 85 into any of four-valued logical signals 0, 1, X, and Z. It
In the case of the present embodiment, when each coded bit is represented by (0 drive bit, 1 drive bit), it is decoded as follows.

The fourth bit of the coded bit is (1, 0) and the corresponding logic signal is 0. 3 of encoded bits
The bit is (0, 1) and the corresponding logic signal is 1. The second bit of the encoded bit is (1, 0),
The corresponding logic signal is 0. The first bit of the coded bit is (1, 1), and the corresponding logic signal is X.

As a result, the output signal becomes "010X" (see "Output signal group" in FIG. 36).

In this way, it is possible to carry out a simulation in a batch without drawing the operation table for realizing the target logical operation for each bit.

Details of the control section 53 and the input display section 52 included in the function simulation section 7 will be described below with reference to the drawings.

First, the configurations of the control section 53 and the input display section 52 will be described with reference to FIG.

FIG. 38 is a block diagram showing the configurations of the control section 53 and the input display section 52. In the control unit 53 shown in FIG. 38, reference numeral 100 denotes an input display control unit, which is a functional simulation execution command,
It controls the input display unit 52 that receives a control command such as a time backward command and a pattern input command to the function simulator unit 50 and displays the result of the function simulation by the function simulator unit 50.

Reference numeral 101 denotes a function simulator control section, which inputs a control command to the function simulator section 50 input to the input display section 52 to the input display control section 100.
The control command is input to the function simulator unit 50 from the receiver, or after the control command is executed, the data returned from the function simulator unit 50 is received and the data is transferred to the input display control unit 100.

The data transfer and data control between the input display control unit 100 and the function simulator control unit 101 may be interprocess communication.

By thus dividing the control unit 53 into the input display control unit 100 for controlling the input display unit 52 and the function simulator control unit 101 for controlling the function simulator unit 50, the function of the input display unit 52 is changed. When adding or adding a function, it is only necessary to change the input display control unit 100, and it is possible to easily cope with the change without changing the function simulator control unit 101. On the contrary, when changing the function of the function simulator unit 50, adding a function, or replacing the function simulator unit 50 with another function simulator, it is only necessary to change the function simulator control unit 101, and the input display control unit 100 is changed. It becomes possible to cope easily without doing.

In the input display section 52 shown in FIG. 38, 1
Reference numeral 10 denotes a simulation control panel display unit, which is controlled by the input display control unit 100,
On the window of the CRT monitor 2, a simulation control panel for controlling execution of functional simulation and inputting test data is displayed.

Reference numeral 111 denotes a table format pattern input / display section, which is controlled by the input / display control section 100 to input a table format pattern, and the function simulator section 50 performs a functional simulation on the window of the CRT monitor 2. The value of each signal is displayed in a table format each time (see FIG. 39).

Reference numeral 112 denotes a waveform format pattern input display section, which is controlled by the input display control section 100,
A pattern in a waveform format is input, and the result of the functional simulation is displayed in the waveform format on the window of the CRT monitor 2 every time the functional simulation is performed by the functional simulator section 50.

Reference numeral 113 denotes a functional diagram format pattern input / display unit, which is controlled by the input display control unit 100, inputs a pattern on the functional diagram, and outputs the value of each signal each time a functional simulation is performed by the functional simulator unit 50. It is displayed on the functional diagram on the window of the CRT monitor 2.

Reference numeral 114 denotes a memory pattern input / display section, which is controlled by the input / display control section 100 to input a circuit memory pattern, and the function simulator section 50 performs a functional simulation on the window of the CRT monitor 2. The memory pattern of the memory is displayed each time.

Reference numeral 115 is a pattern history input display section, which is controlled by the input display control section 100,
The test data input in the past is displayed in a tabular format on the window of the CRT monitor 2, and the test data is input by selecting them. For example, when the function simulator unit 50 executes the backward movement and then the forward movement, or when the functional diagram information is changed, the test pattern, the periodic pattern, the memory pattern, etc. input in the previous functional simulation are displayed on the CRT monitor 2 Is displayed in a tabular form on the window of and the pattern is input by selecting it.

Although not shown, the input display section 52
Further, as one functional unit, test data in a functional description language is further input, and each time a functional simulation is performed by the functional simulator unit 50, the result of the functional simulation is displayed on the functional description language on the window of the CRT monitor 2. A function description language input display unit is provided.

Further, in the input display control section 100 shown in FIG. 38, reference numeral 120 denotes a simulation control panel display control section, which is a simulation control for displaying a simulation control panel for performing functional simulation execution control and test data input control. The panel display unit 110 is controlled.

Reference numeral 121 denotes a table format pattern input display control section, which controls a table format pattern input display section 111 for inputting a table format pattern and displaying a functional simulation result in a table format.

Reference numeral 122 denotes a waveform format pattern input display control section, which controls the waveform format pattern input display section 112 for inputting a waveform format pattern and displaying the functional simulation result in the waveform format.

Reference numeral 123 is a function diagram format pattern input display control unit, which controls the function diagram format pattern input display unit 113 for inputting a pattern on the function diagram and displaying the result of the function simulation on the function diagram.

Reference numeral 124 denotes a memory pattern input / display control section, which controls the memory pattern input / display section 114 for inputting the memory pattern of the circuit and displaying the memory pattern of the memory after the functional simulation.

Reference numeral 125 is a pattern history input display control unit, which controls the pattern history input display unit 115 for inputting test data by displaying the test data input in the past in a table format and selecting them.

Although not shown, the function description language input for inputting test data in the function description language and displaying the function simulation result in the function description language as one function section of the input display control section 100. A function description language input display control unit for controlling the display unit is provided.

Further, in the function simulator control section 101 shown in FIG. 38, 130 is a forward step execution control section, and the time forward step by the state value updating section 61 of the functional simulator section 50 for executing the time forward simulation for one unit time. Control execution.

A forward jump execution control unit 131 controls the time forward jump execution by the state value updating unit 61 of the function simulator unit 50 which executes the time forward simulation for a multi-unit time.

Reference numeral 132 denotes a reverse step execution control section, which controls the reverse step execution by the reverse time selecting section 62 of the functional simulator section 50 for executing the time reverse simulation for one unit time.

Reference numeral 133 denotes a backward jump execution control section, which controls the backward backward jump execution by the backward time selecting section 62 of the functional simulator section 50 for executing the time backward simulation in a multi-unit time.

Reference numeral 134 is a pattern setting control unit, which sets the test pattern, memory pattern, etc. input from the input display unit 52 in the state value storage table 60 of the function simulator unit 50.

Reference numeral 135 is a function simulation result fetch control unit which fetches the result of the function simulation by the function simulator unit 50 from the state value storage table 60 of the function simulator unit 50. In the jump execution of the forward jump execution control unit 131 and the backward jump execution control unit 133, the target time is designated.

Next, the function simulation control operation of the function simulator control section 101 of the control section 53 will be described with reference to FIG.

FIG. 40 shows simulation times controlled by the function simulator control section 101. As shown in FIG. 40, when the time forward step is executed under the control of the forward step execution control unit 130 at the current time T0, the current time after the time forward simulation is T1.

When the forward jump execution control section 131 controls the forward jump of 8 unit time at the present time T0, the present time after the forward time simulation is T8.

At the current time T0, if the backward time step is executed under the control of the backward step execution control unit 132, the current time after the backward time simulation is T-1.

At the current time T0, when the backward jump execution control unit 133 controls the time backward jump of 8 unit time, the current time after the backward time simulation is T-8.

As described above, the control unit 53 has the function simulator control unit 10 configured as described above.
By having 1, it becomes possible to execute various functional simulations, input test data at the time of executing the functional simulations, import existing functional simulation results, etc., and improve the verification efficiency of the operating functions of the logic circuit. it can.

Next, the simulation control panel displayed by the simulation control panel display section 110 of the input display section 52 will be described with reference to FIGS. 41 (a) and 41 (b).

FIG. 41 (a) shows the simulation control panel. 41 (a), 370
Is a forward step execution button, and when the forward step execution button 370 is pressed, the time forward simulation is executed for one unit time and the time advances by one unit time.

Reference numeral 371 denotes a reverse step execution button. By pressing the reverse step execution button 371, the time reverse simulation is executed for one unit time and the time is set to 1
It is returned to the past by a unit time.

Reference numeral 372 denotes a jump execution button. By pressing the jump execution button 372, jump execution is performed to control the functional simulation time to a future time point by a multi-unit time or a past time point to a multi-unit time. The control panel is displayed.

FIG. 41 (b) shows the jump execution control panel. In FIG. 41 (b), 373 is
This is a jump execution start button. By inputting the target time and pressing the jump execution start button 373, the time forward jump or the time backward jump is executed. Whether the time forward jump or time backward jump is executed is determined by the input target time. If the target time is in the future, the time forward jump is executed,
The time advance simulation is executed until the target time.
On the other hand, when the target time is in the past, the time backward jump is executed and the time is returned to the target time.

Reference numeral 374 denotes a jump execution stop button. When the jump execution stop button 374 is pressed, jump execution is stopped midway.

It is also possible to easily realize not only the time as the stop condition for jump execution but also the conditional expression and stopping at the time when the conditional expression is satisfied.

As described above, since the control section 53 has the simulation control panel display section 110 for displaying the simulation control panel configured as described above, the function of the simulation control panel displayed on the window of the CRT monitor 2 is improved. It becomes possible to perform simulation execution control, test data input control, and the like, and it is possible to interactively execute functional simulation.

Next, a specific input display operation of the table format pattern input display section 111 of the input display section 52 will be described with reference to FIGS. 42 (a), 42 (b) and 42 (c).

42 (a) and 42 (b) are functional diagrams showing a functional simulation target circuit.
(C) shows the table format pattern input and displayed by the table format pattern input display unit 111. FIG. 42
In (c), “0” is the state value 0 and “1” is the state value 1
“X” indicates that the state value is an indefinite value. It should be noted that it is easy to extend the displayable state value to multiple values.

When inputting the signal value patterns of the external input pins CLK, RST, INDATA on the functional diagram shown in FIG. 42 (a), the external input pins CLK, RST, INDATA are selected in FIG. 42 (c). Then, if a table format pattern shown by a dotted frame is input, the table format pattern is captured as a test pattern when the functional simulation is executed.

Further, the table format pattern input display section 1
The simulation result at the observation point selected at the time of executing the functional simulation is also displayed by 11, and FIG.
When the external output pin OUT on the functional diagram shown in (b) is designated as the observation point, "1" is displayed as the simulation result, as shown in FIG. 42 (c).

In pattern input, signal values for arbitrary times can be set one by one, and the setting can be changed many times.

As the signal value pattern input, 10
It is possible to set not only a base number but also a binary number, an octal number, and a hexadecimal number.

The pattern input is not limited to the external input pin, but is set to an arbitrary signal on the functional diagram by force forcibly setting the state value of the terminal, register, etc. or unforce to release the force. The observation point can be set not only to the external output pin but also to any signal on the functional diagram.

Further, as a method of selecting a signal for setting a pattern input and a signal for setting an observation point, there are a mouse click and a signal name input in another window.

As described above, it is possible to input a table format pattern and display the result of the functional simulation on the window of the CRT monitor. When executing the functional simulation, the parallel operation can be easily performed in the table format instead of the character arrangement. It is possible to know the state value of each circuit model, and improve the efficiency of verifying the operation function of the logic circuit.

Next, a concrete input display operation of the waveform format pattern input display section 112 of the input display section 52 will be described with reference to FIG.
This will be described with reference to 3 (a) and FIG. 43 (b).

FIG. 43A shows the waveform format pattern for one cycle input by the waveform format pattern input display section 112, and FIG. 43B shows the waveform format pattern input display section 11.
2 shows the waveform format pattern displayed.

When the periodic signal of the external input pin CLK on the functional diagram shown in FIG. 42 (a) is set to repeat 0 and 1 in one unit time, the external input pin CLK is set as a target for inputting the waveform format pattern. Select and input the waveform format pattern as shown in FIG. When the functional simulation is executed, the waveform format pattern is captured as a test pattern, and after the simulation is executed, the waveform format pattern input display unit 112 causes the signal of the external input pin CLK to have a periodic waveform as shown in FIG. 43 (b). It is displayed in the format.

It is also possible to set a periodic signal including X in addition to 0 and 1. It is also easy to handle multivalues as the periodic signal.

Further, as a method of selecting an element for setting the pattern input, there are a mouse click, an element name input in another window, and the like.

The periodic waveform can be changed even at a time midway in the functional simulation.

As described above, when the test data for one cycle is input, the test data for the entire simulation time is displayed on the window of the CRT monitor 2, and the test data for one cycle is displayed before the functional simulation is executed. You can easily set test data just by inputting.

Next, the concrete input display operation of the memory pattern input display section 114 of the input display section 52 will be described with reference to FIG.
Will be described with reference to.

FIG. 44 shows the memory pattern input display section 11
4 shows a memory pattern to be input and displayed. In FIG. 44, reference numeral 380 denotes an address panel, which displays memory addresses. Memory addresses can be displayed in decimal format, binary format, octal format, 1
There is a hexadecimal format.

Reference numeral 381 is a memory pattern panel,
Display the memory pattern, and input and change the pattern. The memory pattern display method is 10
There are a decimal format, a binary format, an octal format, a hexadecimal format, and the like. When only the memory patterns of some addresses can be displayed in the memory pattern panel 381, all can be viewed by the scroll function.

As a function of editing a memory pattern, a cursor mode function of setting the cursor to move to the right, left, up, or down after a character is input, and a memory displayed on the memory pattern panel 381. Select the pattern block and copy the selected memory pattern block to a different address as it is, and enter the numerical value incremented from the specified value starting from the smallest address value of the selected memory pattern block. There are a counting function and a changing function for changing the numerical value of the memory pattern with a certain pattern for the selected block of the memory pattern.

As an example of the changing function, the pattern "111" is used.
? ? When changing by ", all the selected memory patterns are all" 1 "from the 3rd bit to the 5th bit.
Therefore, the 1st bit and the 2nd bit remain the numerical values input to the selected memory pattern. For example, if the first bit is "0", the first bit is "0", and if the second bit is "1", the second bit is "1".

As described above, the cursor mode function, the copy function, the count function, and the change function can be used to easily input the memory pattern, and the function simulator section 50 can be used.
Since it is possible to display the pattern of the memory every time the functional simulation is executed, it is possible to easily verify the operational function of the logic circuit having the memory.

Next, the concrete input display operation of the pattern history input display section 115 of the input display section 52 will be described with reference to FIG.
This will be described with reference to FIG.

FIG. 45 shows the pattern history input display section 1
15 shows a pattern used as test data in the past functional simulation, which is displayed and input by 15. Figure 45
In 390, 390 is the time and displays the time when the pattern was input.

Reference numeral 391 is a clock, and if the periodic pattern is input, the character "C" indicating that it is input is displayed. Here, by selecting the letter "C", the signal name for which the periodic pattern is set and the waveform for one period of the periodic pattern set for the signal are displayed. Any method can be used as a method of indicating that it has been input, as long as it can indicate it. For example, the signal name for which the periodic pattern is set may be displayed. Also, a picture showing the periodic pattern may be displayed.

Reference numeral 392 denotes a memory, and if a memory pattern has been input, the character "M" indicating that it has been input is displayed. Here, by selecting the letter "M", the name of the memory element in which the memory pattern is set and the memory pattern set in the memory element are displayed. As a method of indicating that the memory pattern is input, the memory element name for which the memory pattern is set may be displayed. Also, a picture showing the memory may be displayed.

393 displays the signal name for which the test pattern is input and the pattern for each time input to the signal name.

To input the test data displayed by the pattern history input display section 115, the time of the desired test data is selected and the functional simulator section 50 executes the functional simulation. It is automatically transferred from the pattern history input display section 115 to the function simulator control section 101 via the pattern history input display control section 125 and input to the function simulator section 50.

As a selection method, there are a method of clicking the time of desired test data with a mouse, a method of enclosing the time with a mouse and selecting.

Thus, the test data input in the past can be displayed on the window of the CRT monitor 2,
By selecting desired test data from the displayed test data, it is possible to reuse the test data input in the past. Therefore, when re-executing the functional simulation, it is not necessary to manually input the test data from the beginning, and the pattern history input display unit 1
Just select the test data displayed by 15,
It is possible to automatically transfer the test data to the function simulator unit 50 and execute the function simulation.

Even if the functional diagram to be subjected to the functional simulation is changed, the result of the previous functional simulation is saved in the functional simulation result file, and the functional simulation result file is loaded. Can be reused. Therefore, the verification period of the operation function of the logic circuit is shortened, and the verification efficiency can be improved.

Next, a specific input display operation of the functional diagram format pattern input display section 113 of the input display section 52 will be described with reference to FIGS. 46 (a) and 46 (b).

FIG. 46A shows the functional diagram format pattern on the functional diagram input by the functional diagram format pattern input display unit 113, and FIG. 46B shows the functional diagram format pattern input display unit 113. The functional diagram format pattern on a functional diagram is shown.

When inputting test data to the external input pins IN1 and IN2 on the functional diagram shown in FIG. 46 (a), patterns "1" and "0" are input to the signal value display fields of the external input pins IN1 and IN2. To do. At the time of functional simulation execution, the pattern is taken in as test data,
After executing the functional simulation, as shown in FIG. 46B, the external output pin O set as the observation point on the functional diagram.
The UT status value "1" is displayed.

The pattern input is not limited to the external input pin, but is set to an arbitrary signal on the functional diagram by force forcibly setting the state value of the terminal, register, etc., unforce to release the force, etc. The observation point can be set not only to the external output pin but also to any signal on the functional diagram. The state value in the case of force can be identified by changing the color of the character in order to distinguish it from the other state values. As for the transfer condition labels a and b, instead of displaying the state value, the color may be changed according to the state value and a and b may be highlighted.

Further, as a method for selecting a signal for setting a pattern input and a signal for setting an observation point, there are a mouse click, a signal name input in another window, and the like.

As described above, it becomes possible to input the test pattern and display the result of the functional simulation on the functional diagram of the logic circuit to be subjected to the functional simulation. Therefore, at the time of executing the functional simulation, the state value of each circuit model that operates in parallel can be easily known, and the verification efficiency of the operation function of the logic circuit can be improved.

Details of the functional diagram format pattern input display control section 123 of the input display control section 100 of the control section 53 and the functional diagram format pattern input display section 113 of the input display section 52 will be described below with reference to the drawings.

First, the functional diagram format pattern input display control unit 123 and the functional diagram format pattern input display unit 11
The configuration of No. 3 will be described with reference to FIG.

FIG. 47 is a block diagram showing configurations of the functional diagram format pattern input display control section 123 and the functional diagram format pattern input display section 113. In the functional diagram format pattern input display unit 113 shown in FIG.
Is a data path diagram format pattern input display unit, which is controlled by the function diagram format pattern input display control unit 123, and is a data path diagram format representation diagram that represents the operation function of the logic circuit that is the target of the functional simulation in a data path diagram. Each time the functional simulator section 50 performs a functional simulation on the window of the CRT monitor 2 by inputting the above pattern, the value of each signal which is the result of the functional simulation is represented in a data path diagram format on the window of the CRT monitor 2. Display above the figure.

Reference numeral 113b is a state transition diagram format pattern input display section, which is controlled by the function diagram format pattern input display control section 123 and represents the operation function of the logic circuit to be subjected to the functional simulation in the state transition diagram. Each time a pattern on the graphic representation diagram is input and a functional simulation is performed by the functional simulator section 50, the values of the respective signals as the result of the functional simulation are displayed on the state transition diagram format representation diagram on the window of the CRT monitor 2. indicate.

Reference numeral 113c is a logical expression format pattern input / display section, which is controlled by the functional diagram format pattern input / display control section 123, and is a logical expression format expression for expressing the operation function of the logic circuit to be subjected to the functional simulation by a logical expression. Input the pattern on the figure and enter the function simulator 50
Each time a functional simulation is performed by, the value of each signal, which is the result of the functional simulation, is displayed on the logical expression form representation diagram on the window of the CRT monitor 2.

Reference numeral 113d denotes a truth table format pattern input / display section, which is controlled by the functional diagram format pattern input / display control section 123 and represents a truth value representing the operation function of the logic circuit to be subjected to the functional simulation by the truth table. Each time a functional simulation is performed by the functional simulator section 50 by inputting a pattern on the tabular representation diagram,
CR for each signal value that is the result of the functional simulation
It is displayed on the truth table format representation diagram on the window of T monitor 2.

Further, in the functional diagram format pattern input display control section 123 shown in FIG. 47, 123a is a data path diagram format pattern input display control section,
The data path diagram format pattern input display unit 113a that inputs the pattern on the data path diagram format representation diagram and displays the functional simulation result on the data path diagram format representation diagram is controlled.

Reference numeral 123b is a state transition diagram format pattern input display control section, which inputs a pattern on the state transition diagram format representation diagram and displays the functional simulation result on the state transition diagram format representation diagram. The display unit 113b is controlled.

Reference numeral 123c is a logical expression format pattern input display control section, which is a logical expression format pattern input display section 113c for inputting a pattern on the logical expression format expression diagram and displaying a functional simulation result on the logical expression format expression diagram. Control.

Reference numeral 123d is a truth table format pattern input display control unit, which inputs a pattern on the truth table format representation diagram and displays the functional simulation result on the truth value table format representation diagram. Display 1
Control 13d.

Next, a concrete pattern on each figure input and displayed by the state transition diagram format pattern input display section 113b, the logical expression format pattern input display section 113c, and the truth table format pattern input display section 113d is shown. 48
Description will be given with reference to (a), FIG. 48 (b) and FIG. 48 (c). The patterns on the data path diagram format representation diagram that are input and displayed by the data path diagram format pattern input display unit 113a are shown in FIGS. 46 (a) and 46 (b). Since it has already been described, the description is omitted here.

FIG. 48 (a) shows a pattern on the state transition diagram format representation diagram input and displayed by the state transition diagram format pattern input display unit 113b, which is controlled by the state transition diagram format pattern input display control unit 123b. Thus, the state value of each state ST1 to ST4 of the state machine and the state values of the transition conditions a and b are displayed in the signal value display column.

FIG. 48B shows a pattern on the logical expression format pattern representation diagram which is input and displayed by the logical expression format pattern input display section 113c. The state value of each of the elements IN1 and IN2 referred to in the definition of and the state value of the conditions a and b defined are displayed in the signal value display column.

FIG. 48 (c) shows a pattern on the truth table format pattern representation display input and displayed by the truth table format pattern input display section 113d, which is controlled by the truth table format pattern input display control section 123d. Accordingly, the state value of each of the elements reg1 and reg2 referred to in the definition of the condition and the state value of the conditions c and d defined are displayed in the signal value display field.

When displaying a character in the signal value display field, a color corresponding to the signal value, such as distinguishing "X", is displayed in the signal value display field. The state value can be clearly identified by the color distinction.

Further, in addition to displaying characters in the signal value display field, in the state transition diagram format representation diagram of FIG. 48 (a), the current state of the state machine, the pre-transition state during simulation forward execution, and the simulation backward execution You can also highlight the state before the retrograde of in a different color.

Also, in the logical expression format representation diagram of FIG. 48B and the truth table format representation diagram of FIG. 48C, the condition name column is highlighted when the condition becomes “ON”. ,
It is possible to clearly display the state value not only by the characters but also by the color display, such as highlighting with a different color when it becomes “X”.

The pattern input and the observation point can be set to arbitrary signals on the data path diagram format representation diagram, the state transition diagram format representation diagram, the logical formula format representation diagram, and the truth table format representation diagram.

Further, as a method of selecting a signal for setting a pattern input and a signal for setting an observation point, there are a mouse click and a signal name input in another window.

As described above, in the multi-window of the CRT monitor, the test patterns on various functional diagrams such as the data path diagram format representation diagram, the state transition diagram format representation diagram, the logical formula format representation diagram, and the truth table format representation diagram are displayed. It is possible to display the input and the result of the functional simulation, and at the time of executing the functional simulation, the state value of each circuit model operating in parallel can be easily known, and the verification efficiency of the operating function of the logic circuit can be improved.

An example of a functional design support method for verifying the functional design of the operation of the logic circuit using the functional design support device having the functional simulation unit 7 as described above will be described below with reference to the drawings.

First, the overall processing flow of the functional design support method will be described with reference to FIG.

FIG. 49 is a flow chart showing the process flow of the functional design support method. As shown in FIG. 49, step SB1 is a time advance simulation process, and C
The test data displayed on the window of the RT monitor 2 is selected and input by the input device 1, the time advance step or the time advance jump is executed using the test data, and the functional simulation result is displayed on the CRT monitor 2
This is the process of displaying it on the window.

In step SB2, it is determined whether or not the input test data has an error. If the test data does not have an error, the process proceeds to step SB3.

On the other hand, if there is an error in the test data, the process goes to the time backward movement simulation process in step SB5, and in step SB5, the wrong time backward data step or the time backward movement jump is executed to input incorrect test data. The simulation time is returned to the past simulation time, the incorrect test data is corrected in step SB6 to create new test data, the process returns to step SB1, and the new test data is used to advance the time from the past simulation time. Re-run the simulation.

At step SB3, the displayed functional simulation result is compared with the expected value to judge whether or not there is a logical error or a description error in the logical circuit to be subjected to the functional simulation. Is not present, the process proceeds to step 4.

On the other hand, if there is an error in the logic circuit, the process proceeds to step SB7, and in step SB7, the logical error or description error in the logic circuit is corrected. here,
By specifying a past simulation time and displaying the state value at that time, traceback can be easily performed.

At step SB4, it is determined whether or not the functional simulation has been executed over all simulation times, in other words, whether or not the state values at all simulation times for each circuit model forming the logic circuit have been obtained and verified. If there is a simulation time at which the functional simulation has not been executed, the process returns to the time advance simulation process of step SB1 and thereafter, the steps SB1 to SB1 are performed until the functional simulation is executed at all simulation times. S
B6 is repeatedly executed. Then, when the functional simulation at all times is completed, the functional design verification of the operation of the logic circuit is completed.

Details of the time advance simulation process in step SB1 will be described below with reference to FIG. Here, as shown in FIG. 29, the time advance simulation processing in the case of performing the time advance step at the simulation time T1 will be described.

FIG. 50 is a flow chart showing details of the time advance simulation processing in step SB1. As shown in FIG. 50, first, in step SB10, the input display unit 5
2 inputs, for example, the functional diagram format pattern on the functional diagram as test data.

Next, in step SB11, the test data is transferred from the input display section 52 to the function simulator section 50 under the control of the control section 53.

Then, in step SB12, FIG.
As shown in (a), the forward step execution button 370 on the simulation control panel displayed by the input display section 52 is pressed.

As a result, in step SB13, the function simulator section 50 executes the simulation of the operation function of the logic circuit for a predetermined unit time using the test data.

When the execution of this simulation is completed, in step SB14, the function simulator section 50 adds the simulation result to the state value storage table 60 as the state value at the simulation time T2 of the logic circuit, as shown in FIG. .

At step SB15, the control unit 53
Is a state value storage table 60 of the function simulator section 50.
The simulation result as a state value at the simulation time T2 of the logic circuit is fetched from and transferred to the input display unit 52.

At step SB16, the input display section 52 displays
As shown in FIGS. 46 and 48, the simulation result is displayed on the functional diagram. As shown in FIGS. 42 and 43, the simulation result can be displayed in a table format or a waveform format. Further, when the logic circuit has a memory, a memory pattern as a simulation result can be displayed as shown in FIG. 44. Further, as shown in FIG. 45, the memory pattern is input in step SB10. You can also display the test data in tabular form.

The time forward simulation process of the time forward jump is step SB12 in FIG. 41 (a).
The jump execution button 124 of the simulation control panel shown in FIG.
In the jump execution control panel shown in (b), it is started by designating a desired simulation time and pressing the jump execution start button 125, and by repeatedly executing steps SB13 to SB16, all of the desired simulation time is reached. The state value at the simulation time is calculated and the process ends.

When the test data is set in the pattern history input display section, the test data is automatically set and the time advance simulation is executed.

As described above, according to the time advance simulation process, the functional simulation can be executed for a limited time, the test data can be input each time, and the simulation result can be displayed each time. For this reason, it becomes possible to verify the operation function in the middle stage, and it is possible to detect an error in the test data early.

Further, the state value at each simulation time of the logic circuit can be set in the state value storage table 60 of the function simulator section 50 by repeatedly executing the time advance simulation process.

Details of the time backward movement simulation process in step SB5 will be described below with reference to FIG. Here, as shown in FIG. 29, in the state value storage table 60 of the function simulator unit 50, the state values at the simulation times T1 to T4 of the logic circuit are preset, and at the simulation time T4, the past simulation time T2 is set. The time-reverse traveling simulation processing when the time-reverse traveling jump is performed will be described.

FIG. 51 is a flow chart showing details of the time backward movement simulation process of step SB5. As shown in FIG. 51, first, in step SB20, as shown in FIG.
As shown in, the jump execution button 3 of the simulation control panel displayed by the input display unit 52
Press 72. As a result, as shown in FIG. 41 (b),
The jump execution control panel is displayed.

At step SB21, the past simulation time T2 is designated as the target time on the jump execution control panel and the jump execution start button 373 is pressed.

As a result, in step SB22, as shown in FIG.
As shown in FIG. 9, in the function simulator unit 50, the simulation time of the state value storage table 60 is returned to the past simulation time T2.

At step SB23, the control unit 53
Is a state value storage table 60 of the function simulator section 50.
Then, the state value at the past simulation time T2 of the logic circuit is fetched as a simulation result and transferred to the input display unit 52.

At step SB24, the input display section 52 displays
As shown in FIGS. 46 and 48, the simulation result is displayed on the functional diagram. As shown in FIGS. 42 and 43, the simulation result can be displayed in a table format or a waveform format. Further, when the logic circuit includes a memory, a memory pattern as a simulation result can be displayed as shown in FIG.

The time backward movement simulation process of the time backward movement step is step SB20 in FIG.
It is started by pressing the backward step execution button 371 of the simulation control panel shown in, and in step SB22, the simulation time of the state value storage table 60 of the function simulator section 50 is returned to the immediately preceding past simulation time, and in step SB23, The state value of the logic circuit at the immediately preceding past simulation time is transferred from the function simulator unit 50 to the input display unit 52 as a simulation result, and step SB
At 24, the simulation result is displayed on the functional diagram and the process ends.

As described above, according to the time backward simulation processing, the simulation time can be returned to the past. Therefore, even if the entered test data is incorrect or you want to change the entered test data,
There is no need to execute the time advance simulation process again from time 0.

Further, since the state value at the past simulation time can be confirmed, even if there is an error in the logic circuit or the test data, traceback can be easily performed in order to find the cause. it can.

Another example of the configuration of the function simulation section of the functional design support apparatus according to the first embodiment will be described below with reference to FIG.

FIG. 52 is a block diagram showing the overall structure of the functional simulation section 7A. Here, the functional simulation unit 7A is the functional simulation unit 7 shown in FIG. 26 further provided with a test vector generation unit, and the same components as those shown in FIG. Omit it.

In FIG. 52, reference numeral 54 is a test vector generation unit which receives the functional diagram information and the functional simulation result information 51 and generates the test vector 11 which describes the contents of the test data. The test vector 11 can perform a functional simulation by inputting into the batch processing type language-based functional simulator 10.

The test vector 11 can be used not only as a functional simulator but also as an input to a logic simulator.

It is also easy to use the test vector 11 generated not only in the batch processing simulator but also in the interactive simulator.

As described above, since the functional simulation unit further includes the test vector generation unit 54, the language-based base is obtained from the result information obtained by interactively functionally simulating the test data input to interactively debug the logic circuit. Since the test vector of the function simulator 10 can be generated, it becomes possible to interactively create and modify test data while simultaneously debugging the logic circuit and verifying the operation function of the logic circuit.

(Second Embodiment) A functional design support device according to a second embodiment of the present invention will be described below with reference to the drawings.

FIG. 53 is a block diagram showing the overall structure of a functional design support device according to the second embodiment. here,
The same components as those of the functional design support apparatus of the first embodiment shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

In FIG. 53, the processing section 3A of the functional design support apparatus of the second embodiment is similar to the functional design support apparatus of the first embodiment shown in FIG. An editor unit 5, a function diagram check unit 6, a function simulation unit 7, and a function description language conversion unit 8 are provided, and a design constraint information input unit 14, a design constraint information check unit 15, and a design constraint description language conversion unit 16 are further provided. I have it.

The design constraint information input section 14 inputs timing constraint information, delay constraint information, design constraint information such as fan-out capacity, fan-in capacity, etc. on the functional diagram indicated by the functional diagram information.

The design constraint information check unit 15 verifies whether or not there is a contradiction in the design constraint information input by the design constraint information input unit 14.

The functional simulation unit 7 is verified by the functional diagram checking unit 6 for the presence / absence of a contradiction, and is corrected by the functional diagram editor unit 5 to eliminate the contradiction. Furthermore, the design constraint information checking unit 15 discriminates the conflict of the design constraint information. The functional diagram information relating to the functional diagram that has been verified by the presence / absence and has been corrected by the functional diagram editor unit 5 to eliminate the contradiction of the design constraint information is read from the functional diagram information storage device 4, and the delay simulation is executed for this functional diagram. By doing so, the function and timing of the logic circuit are verified.

The design constraint description language conversion unit 16 analyzes the design constraint information input by the design constraint information input unit 14 on the functional diagram indicated by the functional diagram information, and generates the design constraint description language.

A design constraint description language 17 is generated by the design constraint description language conversion unit 16.

The language-based function simulator 10 includes a function description language 9, a design constraint description language 17, and a test vector 11.
Using and as inputs, high-speed functional simulation is performed on the functional description language.

The logic synthesizing unit 12 receives the function description language 9 and the design constraint description language 17 as input, and netlist information 13
To generate.

FIG. 54A shows the design constraint information input unit 14.
In the functional diagram displayed on the screen of the CRT monitor 2 by the functional diagram editor unit 5, the design constraint information input unit 14 inputs a periodic waveform and displays the periodic waveform. It is an example of setting to the clock external input pin of the logic circuit.

In FIG. 54 (a), reference numeral 400 denotes a waveform for one cycle which is set by the design constraint information input unit 14 to the clock external input pin of the logic circuit.

When a logic circuit has a plurality of clock external input pins, it is possible to set a periodic waveform for each of the clock external input pins.

FIG. 54 (b) shows a first specific example of the operation of the design constraint description language conversion unit 16, and the design constraint description language conversion unit 16 uses the design constraint in the functional diagram of FIG. 54 (a). In this example, the information input unit 14 generates the design constraint description language 17 corresponding to the information of the periodic waveform set in the clock external input pin of the logic circuit.

In FIG. 54 (b), the first line shows the design constraint for setting the information of the periodic waveform set in the clock external input pin of the logic circuit by the design constraint information input unit 14 in the logic synthesis unit 12. It is a description language.

The second line is the logic synthesizing unit 14 so as to satisfy the register setup constraint and the hold time constraint.
Is a design constraint description language for instructing to.

It is also possible to input and specify information such as rising skew and falling skew in the periodic waveform.

FIG. 55A shows the design constraint information input unit 14
In the functional diagram displayed on the screen of the CRT monitor 2 by the functional diagram editor unit 5, the design constraint information input unit 14 inputs the fan-out capacity and the fan-in capacity. In this example, the fan-out capacitance is set to the external input pin and the fan-in capacitance is set to the external output pin.

In FIG. 55 (a), reference numeral 410 is the fan-out capacity set to the external input pin by the design constraint information input unit 14.

Reference numeral 411 is a fan-in capacity set to the external output pin by the design constraint information input unit 14.

A blank in the reset external input pin and the clock external input pin indicates that no capacitance is designated.

FIG. 55 (b) shows a second specific example of the operation of the design constraint description language conversion unit 16. The design constraint description language conversion unit 16 uses the design constraint in the functional diagram of FIG. 55 (a). In this example, the information input unit 14 generates the design constraint description language 17 corresponding to the fan-out capacity information set in the external input pin of the logic circuit and the fan-in capacity information set in the external output pin.

In the first and second lines of FIG. 55B, the information on the fan-out capacity set to the external input pin of the logic circuit by the design constraint information input unit 14 is set to the logic synthesis unit 12. Is a design constraint description language for.

The third and fourth lines are a design constraint description language for setting the fan-in capacity information set to the external output pin of the logic circuit by the design constraint information input unit 14 in the logic synthesis unit 12. is there.

FIG. 56A shows the design constraint information input unit 14
In the functional diagram displayed on the screen of the CRT monitor 2 by the functional diagram editor unit 5, the design constraint information input unit 14 inputs the delay value and displays the delay value. This is an example of setting a terminal, which is a component having no state value storage capability, a register, which is a component having storage capability, and an external pin.

In FIG. 56A, reference numeral 420 is a delay value set to the external input pin by the design constraint information input unit 14.

Reference numeral 421 is a delay value set to the external output pin by the design constraint information input unit 14.

Reference numeral 422 is a delay value set in the terminal by the design constraint information input unit 14.

Reference numeral 423 is a delay value set in the register by the design constraint information input unit 14. A blank delay value indicates that no delay value is specified.

In the function simulation section 7, the design constraint information input section 14 is CR by the function diagram editor section 5.
The delay simulation is executed based on the delay value set on the functional diagram displayed on the screen of the T monitor 2. This delay simulation is a more accurate simulation than the 0 delay simulation.

As the delay value, not only the standard delay value but also the rising delay value, the falling delay value, etc. can be used.

Further, as a component for setting the delay value, it is possible to extend so as to set the component other than the external input pin, the external output pin, the terminal and the register.

FIG. 56 (b) shows a third specific example of the operation of the design constraint description language conversion unit 16, and the design constraint description language conversion unit 16 uses the design constraint in the functional diagram of FIG. 56 (b). This is an example in which the design constraint description language 17 is generated from the information of the delay value set in the terminal, the register, and the external pin by the information input unit 14.

In FIG. 56 (b), the first row shows a design constraint for setting information on the total delay value obtained by calculating the total delay value from the external input pin IN1 to the external output pin OUT1 in the logic synthesis unit 12. It is a description language.

The second line is a design constraint description language for setting information on the total delay value obtained by calculating the total delay value from the external input pin IN2 to the external output pin OUT1 in the logic synthesis unit 12.

The third line is a design constraint description language for setting the information of the total delay value obtained by calculating the total delay value from the external input pin IN2 to the external output pin OUT2 in the logic synthesis unit 12.

The fourth line is a design constraint description language for setting the information of the total delay value obtained by calculating the total delay value from the external input pin IN3 to the external output pin OUT1 in the logic synthesis unit 12.

The fifth line is a design constraint description language for setting information on the total delay value obtained by calculating the total delay value from the external input pin IN3 to the external output pin OUT2 in the logic synthesis unit 12.

In the present embodiment, the design constraint description language for setting the delay value obtained by simply adding all the delay values set in the parts on the path from the external input pin to the external output pin is taken as an example. However, it is easy to support other various delay calculation methods.

FIG. 57 is a flow chart showing a functional design support method using the functional design support apparatus of the second embodiment.

In FIG. 57, SC1 is a functional diagram creating process for creating a functional diagram using figures, tables, characters and the like.

SC2 is a functional diagram error checking process for inputting the functional diagram created in the functional diagram creating process SC1 and verifying whether or not there is a contradiction in this functional diagram.

SC3 is a judging process for judging whether or not there is a contradiction in the functional diagram. Here, if there is no contradiction in the functional diagram, the process moves to SC4, while if there is a contradiction, SC10
Then, in SC10, the functional diagram is corrected using the figure, table, characters, etc. (functional diagram correction process), and the process returns to the functional diagram error check process SC2.

SC4 inputs timing constraint information, delay constraint information, design constraint information such as fan-out capacity, fan-in capacity, etc., and outputs this design constraint information on the functional diagram created by the functional diagram creation process SC1. It is a process of inputting design constraint information set to.

SC5 is a design constraint information error check process for verifying whether or not there is an error in the design constraint information input in the design constraint information input process SC4.

SC6 is a judging process for judging whether or not there is an error in the design constraint information. Here, if there is no error in the design constraint information, the process proceeds to SC7, while if there is an error, the process proceeds to SC11, where the design constraint information is corrected (design constraint information correction process), and the design constraint information error check process is performed. Return to SC5.

SC7 performs functional verification and timing verification of the logic circuit on the functional diagram from the information of the functional diagram created by the functional diagram creation process SC1 and the design constraint information input by the design constraint information input process SC4. This is the function verification process to be performed.

SC8 is a judgment process for judging whether or not there is an error in the operation of the logic circuit. Here, if the operation of the logic circuit is correct, the process proceeds to SC9, if the test pattern has an error, the process proceeds to SC12, the test pattern is corrected in SC12 (test pattern correction process), and the corrected function verification process SC7 is performed. If there is an error in the design constraint information, the process proceeds to the design constraint information correction process SC11 to correct the design constraint information and returns to the design constraint information error check process after correction SC5 to find a logical error in the functional diagram. In order to correct the operation of the functional diagram, the functional diagram modification process S
Move to C10 and correct function diagram error check process SC2
If the operation of the logic circuit is correct, the process proceeds to SC9.

SC9 uses the function diagram and design constraint information to
This is a language conversion process for generating a function description language and a design constraint description language.

[0453]

As described above, according to the functional design support device of the invention of claim 1, the following effects can be obtained.

(1) Since the function description language is not used, the designer of the logic circuit does not need to learn the function description language.

(2) Since the function description language is not used, design assets can be accumulated and used.

(3) The functional design of the logic circuit is performed by using graphic elements such as figures, tables, and characters, so that it is easy to see.

(4) The design period of the logic circuit is shortened.

(5) Standardization of logic circuit design techniques can be achieved.

According to the functional design support apparatus of the invention of claim 2, the following effects can be obtained.

(1) The functional design can be spread and expanded by the state transition diagram, the data path diagram, the truth table, and the logical expression table.

(2) Since the control circuit of the logic circuit is described by the state transition diagram, the data path unit is described by the data path diagram, and the combination circuit unit is described by the truth table or the logical expression table, the logic The operation of the circuit can be efficiently described according to its function.

(3) On the multi-window of the display device,
Since it is possible to describe multiple functional diagrams of the state transition diagram, data path diagram, truth table, and logical expression table at the same time, it is necessary to divide the description into multiple windows even for a logic circuit with a large circuit scale. This makes the design more efficient, and also makes the designed circuit easier to see.

According to the functional design support apparatus of the third aspect of the invention, in the functional design using the functional diagram information, the connection, definition and reference status of the functional diagram can be easily confirmed, and mistakes at the initial stage can be easily checked. can do.

According to the functional design support apparatus of the invention of claim 4, in the functional design using the functional diagram information, from the functional diagram information, a functional description language suitable for logical synthesis means, or a language-based functional description language, is used. By creating a functional description language suitable for a functional simulator and suitable for functional simulation, a circuit that guarantees the same operation in logic synthesis and functional simulation can be obtained.

According to the functional design support apparatus of the fifth aspect of the present invention, in the functional design using the functional diagram information, the functional description language suitable for the logic composition suitable for the circuit configuration desired after the logic composition is realized from the functional diagram information. By creating, a logic circuit having a desired circuit configuration can be obtained after logic synthesis.

According to the functional design support apparatus of the invention of claim 6, in the functional design using the functional diagram information, the control unit of the circuit is changed to the state transition diagram functional description language suitable for the state transition diagram oriented logic synthesizing means, Data path part of the circuit to the data path diagram functional description language suitable for data path oriented logic synthesis means,
An optimal logic circuit can be obtained after logic synthesis by converting the random logic of the circuit into a combinational circuit function description language suitable for random logic-oriented logic synthesis means.

According to the functional design support apparatus of the seventh aspect of the present invention, in the functional design using the functional diagram information, the facility for designing the functional description language suitable for the circuit synthesis which is desired to be realized after the logical synthesis is obtained from the functional diagram information. It can be created for each facility, and after logic synthesis, a logic circuit having a desired circuit configuration for each facility can be obtained.

According to the functional design support apparatus of the eighth aspect, the functional simulation can be executed for a limited time, the test data can be input each time, and the simulation result can be displayed each time. In addition, it becomes possible to verify the operation function in the middle stage, and it is possible to detect an error in the test data at an early stage.

According to the functional design support apparatus of the ninth aspect, since the simulation time can be set back to the past, it is possible to execute the functional simulation again. Even if you want to change the test data you entered,
There is no need to restart the functional simulation from time 0. Therefore, the verification period of the operation function of the logic circuit can be shortened and the verification efficiency can be improved.

According to the functional design support apparatus of the tenth aspect of the present invention, for example, in the functional description language of the functional simulation target circuit displayed in the multi-window of the display device, the test data is input and the functional simulation result is displayed. Therefore, it is possible to easily verify the operation function of the circuit in the function description language.

According to the functional design support apparatus of the eleventh aspect of the present invention, for example, pattern input and functional simulation result display are performed on the functional diagram of the functional simulation target circuit displayed in the multi-window of the display device. Since it becomes possible to verify the operation function of the logic circuits operating in parallel, it is possible to improve the verification efficiency of the operation function of the logic circuit. Further, at the time of debugging, the cause of the error can be spatially pursued on the functional diagram, so that the debugging efficiency can be improved.

According to the functional design support apparatus of the twelfth to fifteenth aspects, for example, the data path diagram, the state transition diagram, and the logical expression representation diagram of the functional simulation target circuit displayed in the multi-window of the display device. Since it is possible to input patterns and display the result of functional simulation on the above or on the truth table format representation diagram, it becomes easier to verify the operational function of the logic circuits operating in parallel. The verification efficiency of can be improved. Further, at the time of debugging, the cause of the error can be spatially pursued on each figure, so that the debugging efficiency can be improved.

According to the functional design support apparatus of the sixteenth aspect, for example, it is possible to perform execution control of functional simulation and input control of test data on the simulation control panel displayed in the multi-window of the display device. Therefore, the functional simulation can be interactively performed, so that the verification efficiency of the operation function of the logic circuit can be improved.

According to the functional design support apparatus of the seventeenth aspect of the present invention, in the functional simulation processing, not only the time forward function simulation but also the time backward function simulation can be quickly returned from the middle of the processing to the past time. Therefore, the verification efficiency of the operation function of the logic circuit can be improved.

According to the functional design support apparatus of the eighteenth aspect of the present invention, in a memory element such as a register or a RAM that operates in synchronization with a rising or falling edge of a clock signal, the clock signal and the input signal are at the same time. When changing, even if there is a time difference between the event processing for the change of the clock signal and the event processing for the change of the input signal, the same functional simulation result can be obtained. Therefore, it is possible to guarantee the same operation by functional simulation.

According to the functional design support apparatus of the nineteenth aspect of the present invention, an input signal having a plurality of bit widths represented by four values is a coded input signal composed of 0 drive word and one drive word represented by a binary value. It is possible to process the logical signal represented by four values as a binary signal and collectively process a plurality of digits. Therefore, it is not necessary to obtain the operation result for each bit, and there is an effect that the simulation of the logical operation between the logic signals of a plurality of bit widths represented by four values can be accelerated.

According to the functional design support apparatus of the twentieth aspect, the ZX conversion for converting the coded bit corresponding to the logic signal Z in the coded input signal into the coded bit corresponding to the logic signal X is facilitated. Can be realized.

According to the functional design support apparatus of the twenty-first aspect of the present invention, the function simulation support apparatus for the language-based functional simulator is obtained from the result of the functional simulation that is interactively functionally simulated by the test data input to interactively debug the logic circuit. Since a test pattern can be generated, it is possible to debug the logic circuit and verify the operation function of the logic circuit, and at the same time, interactively create and modify test data, and interactively create test vectors for the language-based functional simulator. It can be created and modified. Therefore, it is possible to automatically generate a highly reliable test vector and eliminate the need to create a new test vector for a language-based functional simulator, which can shorten the period for design verification of logic circuits and improve verification efficiency. Can be made.

According to the functional design support apparatus of the twenty-second aspect of the invention, the control means is divided into an input display control section for controlling the input display means and a function simulator control section for controlling the function simulator means. When the function of the input display means is changed or the function is added, only the input display control section needs to be changed, and the function simulator control section can be easily changed. Conversely, when changing the function of the function simulator means, adding a function, or replacing the function simulator means with another function simulator means, it is sufficient to change the function simulator control section and change the input display control section. Can be easily dealt with. Therefore, it is possible to easily meet the demands and desires of the user of the apparatus, and it is possible to construct an efficient operation function verification environment.

According to the functional design support apparatus of the twenty-third and twenty-fourth aspects of the present invention, it is possible to appropriately select and execute from various functional simulations, and to execute a test pattern, a periodic pattern or Input test data such as memory pattern,
Since it is possible to take out the existing functional simulation result, it is possible to improve the verification efficiency of the operation function of the logic circuit.

According to the functional design support apparatus of the twenty-fifth aspect of the present invention, for example, it is possible to input a table format pattern and display a functional simulation result in a window of a display device, and thus display only characters. Since it is possible to easily verify the operation function of the logic circuit, it is possible to improve the efficiency of verifying the operation function of the logic circuit.

According to the functional design support apparatus of the twenty-sixth aspect of the invention, for example, it is possible to input a waveform format pattern and display a functional simulation result in a window of a display device, so that only characters are displayed. Since it is possible to easily verify the operation function of the logic circuit, it is possible to improve the efficiency of verifying the operation function of the logic circuit.

According to the functional design support apparatus of the twenty-seventh aspect, for example, the memory pattern can be easily input by the cursor mode function, the copy function, the count function, and the change function, and each time the functional simulation is executed, Since it is possible to display the memory pattern, it is possible to easily verify the operation function of the logic circuit having the memory, so that the verification period of the operation function of the logic circuit can be shortened and the verification efficiency can be improved. it can.

According to the functional design support apparatus of the twenty-eighth aspect of the present invention, for example, by displaying or selecting the test data input in the past in the window of the display device, the test data input in the past is re-displayed. Since it can be used, functional simulation can be re-executed without manually inputting test data. Further, even when the logic circuit is changed, the test data can be reused by saving the functional simulation result of the previous functional simulation in a file and loading the functional simulation result. . Therefore, the verification period of the operation function of the logic circuit can be shortened and the verification efficiency can be improved.

According to the functional design support method of the invention of claim 29, the functional simulation can be executed for a limited time, the test data can be input each time, and the simulation result can be displayed each time. Because it is possible, it becomes possible to verify the operation function in the middle stage,
Errors in test data can be detected early.

Further, according to the functional design support method of the invention of claims 31 and 32, since it is possible to confirm the state value at the past simulation time, for example, there is an error in the logic circuit or the test data. Even if
Traceback can be easily performed to pursue the cause. Therefore, the debugging efficiency can be improved.

According to the functional design support method of the thirty-fourth aspect of the present invention, since the state value at each simulation time of the logic circuit can be obtained and stored by repeatedly executing the functional simulation, the simulation time can be stored in the past. It can be easily returned. As a result, it is not necessary to restart the functional simulation from time 0 even when the input test data has an error or when the input test data is desired to be changed. Therefore, the verification period of the operation function of the logic circuit can be shortened and the verification efficiency can be improved.

According to the functional design support method of claim 30, 33, and 35, for example, on the functional diagram of the functional simulation target circuit displayed in the multi-window of the display device, the input of the pattern and the display of the functional simulation result are performed. It becomes possible to do it. Therefore, the state value of each circuit model that operates in parallel can be easily known, and the operation function verification of the logic circuits that operate in parallel can be easily performed, so that the verification efficiency of the operation function of the logic circuit can be improved.
Further, at the time of debugging, the cause of the error can be spatially pursued on the functional diagram, so that the debugging efficiency can be improved.

According to the functional design support device of the invention of claim 36 and the functional design support method of the invention of claim 40, the following effects can be obtained.

(1) Since it is possible to clearly understand how the design constraint is set for the logic circuit on the functional diagram, the design efficiency is improved.

(2) Since the functional description language and the design constraint description language can be automatically generated from the functional diagram, the designer can obtain the netlist information reflecting the design constraint without using the design constraint description language. it can. Therefore, a circuit having desired performance can be logically synthesized in a short time, and the design period of the logic circuit can be shortened.

(3) It is possible to perform delay simulation and perform timing verification on the functional diagram, and it is possible to realize more accurate functional simulation on the functional diagram.

According to the functional design support apparatus of the thirty-seventh aspect of the present invention, it is possible to set constraints such as the setup time and the hold time of the register of the logic circuit in the logic synthesizing means as a design constraint, and the desired logic circuit. Therefore, a circuit closer to the above can be obtained at a higher level in the design process.

According to the functional design support apparatus of the thirty-eighth aspect of the present invention, the fan-out capacity for the external input pin of the logic circuit and the fan-in capacity for the external output pin can be set in the logic synthesizing means as design constraints. Therefore, a circuit closer to the desired logic circuit can be obtained at a higher level in the design process. .

According to the functional design support apparatus of the thirty-ninth aspect of the invention, the delay value is set in the component forming the logic circuit,
This delay value can be set in the logic synthesis means as a design constraint, and the function simulation means can perform delay simulation on the functional diagram. As a result, a circuit closer to the desired logic circuit can be obtained, and more detailed simulation can be performed.

As described above, according to the present invention, all the operations of the logic circuit can be input using figures, tables, characters, etc. without using any functional description language. It is possible to realize a functional design support device having a user-friendly interface that can perform functional verification by using it and can generate a functional description language from these figures, tables, characters, and the like.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a functional design support device according to a first exemplary embodiment of the present invention.

FIG. 2 is a flowchart showing a functional design support method using the functional design support device.

FIG. 3 is a block diagram showing an example of a configuration of a functional diagram editor unit according to the first embodiment.

FIG. 4 is a diagram showing a specific example of a state transition diagram described by a state transition diagram editor unit according to the first embodiment.

FIG. 5 is a diagram showing a specific example of a data path diagram described by a data path editor unit according to the first embodiment.

FIG. 6 is a diagram showing a specific example of a truth value table described by a truth value table editor unit according to the first embodiment.

FIG. 7 is a diagram showing a specific example of a logical expression table described by the logical expression editor unit according to the first embodiment.

FIG. 8 is a block diagram illustrating an example of a configuration of a functional diagram check unit according to the first embodiment.

9A is a diagram showing an example of a state transition diagram window, FIGS. 9B and 9C are diagrams showing an example of a data path diagram window, and FIG. 9D is an example of a truth table window. FIG.

FIG. 10 is a block diagram showing an example of a configuration of a check unit in the functional diagram check unit.

FIG. 11 is a diagram showing a specific example of check result information 21.

FIG. 12 is a block diagram showing an example of a configuration of a function description language conversion unit according to the first embodiment.

FIG. 13 is a block diagram showing an example of a configuration of a logic synthesis function description language conversion unit in the function description language conversion unit.

FIG. 14A is a diagram showing an example of a state transition diagram converted by a state transition diagram function description language conversion unit according to the first embodiment, and FIG. 14B is a state transition diagram of FIG. It is a figure which shows the state transition diagram function description language obtained by converting.

FIG. 15A is a diagram showing an example of a data path diagram converted by a data description diagram function description language conversion unit according to the first embodiment, and FIG. 15B is a data path diagram of FIG. It is a figure which shows the data path diagram function description language obtained by converting.

FIG. 16A is a diagram showing an example of a truth table converted by a truth table function description language conversion unit according to the first embodiment, and FIG. 16B is a truth table of FIG. It is a figure which shows the truth table function description language obtained by conversion.

FIG. 17A is a diagram showing an example of a logical expression table converted by a logical expression function description language conversion unit according to the first embodiment, and FIG. 17B is a conversion of the logical expression table of FIG. It is a figure which shows the logical expression function description language obtained by doing.

FIG. 18 is a block diagram showing an example of a configuration of a data path diagram function description language conversion unit according to the first embodiment.

19 is a diagram showing an example of a data path diagram converted by the data description diagram function description language conversion unit of FIG. 18;

FIG. 20A is a diagram showing a selector-structured logic synthesis function description language with a priority order obtained by converting the data path diagram of FIG. 19 by the data path diagram function description language conversion unit of FIG. 18; FIG. 9B is a circuit diagram showing a circuit obtained by logically synthesizing the selector-configured logic synthesizing function description language of FIG.

FIG. 21A is a diagram showing a function description language for selector configuration logic synthesis without priority, which is obtained by converting the data path diagram of FIG. 19 by the data path diagram function description language conversion unit of FIG. FIG. 6B is a circuit diagram showing a circuit obtained by logically synthesizing the function description language for selector-configured logic synthesis in FIG.

FIG. 22 is a block diagram showing another example of the configuration of the data path diagram function description language conversion unit according to the first embodiment.

23 is a diagram showing an example of a data path diagram converted by a data path diagram function description language conversion unit in FIG. 22.

24A is a diagram showing a functional configuration language for selector-configured logic synthesis with priority, which is obtained by converting the register RegA in the data path diagram of FIG. 23, and FIG.
3 is a diagram showing a function description language for tri-state configuration logic synthesis without priority obtained by converting a register RegB in the data path diagram of FIG.

FIG. 25 shows a circuit obtained by logically synthesizing the selector-configured logic synthesis function description language with priority shown in FIG. 24A and the tri-state configuration logic synthesis function description language without priority shown in FIG. 24B. It is a circuit diagram shown.

FIG. 26 is a block diagram showing an example of a configuration of a functional simulation section according to the first example.

FIG. 27 is a block diagram showing a configuration of a function simulator unit according to the first embodiment.

FIG. 28 is a diagram showing a state value storage table of the function simulator unit.

FIG. 29 is a diagram showing changes in state values due to a functional simulation operation of the functional simulator section.

FIG. 30A is a diagram showing a logic circuit that is a target of time advance simulation by the state value updating unit of the function simulator unit, and FIG. 30B is a timing diagram showing input data and simulation result of the time advance simulation. It is a figure.

FIG. 31 is a block diagram showing a configuration of an event processing unit of the function simulator unit.

FIG. 32 is a block diagram showing a configuration of an evaluation unit of the function simulator unit.

FIG. 33 is a diagram showing an input / output correspondence relationship when the encoding unit according to the first embodiment performs encoding.

FIG. 34 is a diagram illustrating a specific example of encoding a logical signal.

FIG. 35 is a block diagram showing a configuration of a ZX conversion unit of the evaluation unit.

FIG. 36 is a schematic diagram showing a specific example of the operation of the evaluation unit.

FIG. 37 is a diagram showing a specific example of the operation of the ZX conversion unit.

FIG. 38 is a block diagram showing a configuration of a control unit and an input display unit according to the first example.

FIG. 39 is a diagram showing a table displayed by the table format pattern input display unit according to the first example.

FIG. 40 is a diagram showing a change in simulation time due to a functional simulation control operation by the functional simulator control unit according to the first example.

FIG. 41 (a) is a diagram showing a simulation control panel displayed by the simulation control panel display unit according to the first embodiment, and FIG. 41 (b) is displayed by pressing a jump execution button of this simulation control panel. It is a figure which shows the jump execution control panel.

42 (a) and 42 (b) are data path diagrams showing a logic circuit to be subjected to functional simulation, and FIG.
FIG. 6 is a diagram showing a table format pattern input and displayed by the table format pattern input display unit according to the first embodiment.

43A is a waveform diagram showing a waveform format pattern input by the waveform format pattern input display section according to the first embodiment, and FIG. 43B is a waveform format displayed by this waveform format pattern input display section. It is a wave form diagram which shows a pattern.

FIG. 44 is a diagram showing a memory pattern input and displayed by the memory pattern input display unit according to the first example.

FIG. 45 is a diagram showing test data used in the past functional simulation displayed and input by the pattern history input display section according to the first example.

FIG. 46A is a diagram showing a functional diagram format pattern input by the functional diagram format pattern input display unit according to the first embodiment, and FIG. 46B is a diagram showing this functional diagram format pattern input display unit; It is a figure which shows a function diagram format pattern.

FIG. 47 is a block diagram showing configurations of a functional diagram format pattern input display control unit and a functional diagram format pattern input display unit according to the first example.

48A is a diagram showing a pattern input and displayed by the state transition diagram format pattern input / display unit according to the first embodiment, and FIG. 48B is a logical expression format pattern according to the first embodiment; It is a figure which shows the pattern which an input display part inputs and displays, and (c) is a figure which shows the pattern which the truth table format pattern input display part which concerns on a 1st Example inputs and displays.

FIG. 49 is a flowchart showing a functional design support method using a functional design support device including the functional simulation unit.

50 is a flowchart showing the details of the time advance simulation process in the functional design support method of FIG. 49.

51 is a flowchart showing the details of the time backward simulation processing in the functional design support method of FIG. 49.

FIG. 52 is a block diagram showing another example of the configuration of the functional simulation section according to the first example.

FIG. 53 is a block diagram showing an overall configuration of a functional design support device according to a second example of the present invention.

54A is a diagram showing a periodic waveform set on the functional diagram by the design constraint information input unit according to the second embodiment, and FIG. 54B is a design constraint description according to the second embodiment. It is a figure which shows the design constraint description language corresponding to the periodic waveform of (a) obtained by the language conversion part.

55A is a diagram showing fan-out capacity and fan-in capacity set on the functional diagram by the design constraint information input unit, and FIG. 55B is obtained by the design constraint description language conversion unit; It is a figure which shows the design constraint description language corresponding to the fan-out capacity and fan-in capacity of (a).

FIG. 56 (a) is a diagram showing a delay value set on the functional diagram by the design constraint information input unit, and FIG. 56 (b) is a delay of (a) obtained by the design constraint description language conversion unit. It is a figure which shows the design constraint description language corresponding to a value.

FIG. 57 is a flowchart showing a functional design support method using the functional design support apparatus according to the second embodiment.

FIG. 58 is a block diagram showing a configuration of a conventional logic design support device.

[Explanation of symbols]

1 Input device 2 CRT monitor 2a State transition diagram window 2b Data path diagram window 2c Truth table window 2d Logical expression window 3,3A Processing unit 4 Functional diagram information storage device 4a State transition diagram information 4b Data path diagram information 4c Truth table Information 4d Logical expression information 5 Functional diagram editor section 5a State transition diagram editor section 5b Data path editor section 5c Combinational logic editor section 5d Truth table editor section 5e Logical expression editor section 6 Functional diagram check section 7, 7A Functional simulation section 8 Function Description language conversion unit 9 Function description language 10, 10A, 10B Language-based function simulator 11 Test vector 12, 12A, 12B Logic synthesis unit 12a State transition diagram-oriented logic synthesis unit 12b Data path-oriented logic synthesis unit 12c Random logic-oriented logic synthesis unit 13 Netlist information 14 Design constraint information input unit 15 Design constraint information check unit 16 Design constraint description language conversion unit 17 Design constraint description language 20 Check unit 20a Name error check unit 20b Name undetermined check unit 20c Name duplication check unit 20d Component parts Unconnected check unit 20e Bit width error check unit 20f Condition label setting error check unit 21 Check result information 22 Check result screen display unit 23 Check result error report file creation unit 24 Check result error report file 30 Logic synthesis function description language conversion unit 31 Function description language conversion unit for language-based function simulator 32, 32A, 32B Function description language for logic synthesis 33, 33A, 33B Function description language for language-based function simulator 40 State transition diagram Function description language Conversion unit 41, 41A Data path diagram Functional description language conversion unit 41a No priority order selector configuration logic synthesis function description language conversion unit 41b Priority level selector configuration logic synthesis function description language conversion unit 41c No priority tri-state configuration logic synthesis Function description language conversion unit 41d Tristate configuration logic synthesis function description language conversion unit 42 Truth table function description language conversion unit 43 Logical expression function description language conversion unit 44 State transition diagram Function description language 45 Data path diagram function Description language 45a Function language for selector configuration logic synthesis without priority order 45b Function description language for selector configuration logic synthesis with priority order 45c Function description language for tri-state configuration logic synthesis without priority order 45d Tristate configuration logic synthesis function with priority order Description language 46 Truth table functional description language 47 Logical function description language 48 Desired circuit configuration information 49 Circuit model type discriminator 50 Functional simulator section 51 Functional simulation result information 52 Input display section 53 Control section 54 Test vector generation section 60 State value storage table 61 State value update section 62 Backward movement Time selection unit 63 Event list 64 Event processing unit 65 Evaluation unit 66 Circuit information 70 Event extraction processing unit 71 Event type determination processing unit 72 Normal event processing unit 73 Clock event processing unit 74 Register input data event processing unit 80 Arithmetic operation evaluation unit 81 Logical operation evaluation unit 82 ZX conversion unit 83 Output signal evaluation unit 84 Encoding unit 85 Decoding unit 90 Logical sum evaluation unit 91 Bit inversion unit 92 ZX conversion mask processing unit 100 Input display control unit 101 Functional simulator co Control section 110 Simulation control panel display section 111 Table format pattern input display section 112 Waveform format pattern input display section 113 Functional diagram Format pattern input display section 113a Data path diagram Format pattern input display section 113b State transition diagram Format pattern input display section 113c Logic Expression format pattern input display section 113d Truth table format pattern input display section 114 Memory pattern input display section 115 Pattern history input display section 120 Simulation control panel display control section 121 Table format pattern input display control section 122 Waveform format pattern input display control section 123 Functional diagram format pattern input display control section 123a Data path diagram format pattern input display control section 123b State transition Format pattern input display control section 123c Logical expression format pattern input display control section 123d Truth table Format pattern input display control section 124 Memory pattern input display control section 125 Pattern history input display control section 130 Forward step execution control section 131 Forward jump execution control Part 132 Reverse step execution control part 133 Reverse jump execution control part 134 Pattern setting control part 135 Functional simulation result acquisition control part

Claims (40)

[Claims] 1. A functional design support device for supporting functional design of a logic circuit, comprising: a display device for displaying graphic elements such as figures, tables and characters; and a function for expressing the operation function of the logic circuit by the graphic element. A storage device for storing functional diagram information about the figure, a function for describing the functional diagram on the screen of the display device using a chart element, and a function for storing the functional diagram information for the described functional diagram in the storage device. A functional diagram editor means having a function of reading the functional diagram information from the storage device, and functional diagram information relating to the functional diagram described by the functional diagram editor means from the storage device to determine whether there is a contradiction in the functional diagram. A functional diagram checking unit to be verified, and functional diagram information relating to the functional diagram whose presence / absence is verified by the functional diagram checking unit are read from the storage device;
Functional simulation means for performing functional verification on the functional diagram, and function for reading functional diagram information on the functional diagram functionally verified by the functional simulation means from the storage device to generate a functional description language from the functional diagram. A functional design support apparatus comprising: a description language conversion means; and a logic synthesis means for inputting a function description language generated by the function description language conversion means and generating netlist information. 2. The display device has a multi-window composed of first, second, third and fourth windows, and the functional diagram editor means includes a logical window on the first window of the display device. State transition diagram editor means for describing the control part of the circuit in the form of a state transition diagram, and data path part of the logic circuit on the second window of the display device, arrangement of functional elements and connection relation between the functional elements. Data path editor means described in the form of a data path diagram, and truth table editor means for describing the combinational circuit portion of the logic circuit in the truth table format on the third window of the display device. On the fourth window of the display device, a logical expression editor that describes, in the form of a logical expression table, a combined circuit that is difficult to be expressed by a truth table in the combined circuit portion of the logical circuit. Functional design support apparatus according to claim 1, characterized in that and a coater unit. 3. The function diagram checking means reads the function diagram information from the storage means, determines whether there is a contradiction in the function diagram indicated by the function diagram information based on a check rule, and a check result. Check means having a function of creating information, check result screen displaying means for displaying check result information on the screen of the display device, and check result error report file creating means for creating a check result error report file from the check result information The functional design support apparatus according to claim 1, further comprising: 4. A language-based function simulator for inputting the function description language generated by the function description language conversion means and performing a function simulation on the function description language, wherein the function description language conversion means is functional diagram information. To a language-based function simulator function description language suitable for the language-based function simulator, and a function description language conversion means for the language-based function simulator; Logic synthesis function description language conversion means for converting into a logic synthesis function description language suitable for the logic synthesis means, which guarantees the same result as the function simulation result on the language-based function simulator function description language by the function simulator. The machine according to claim 1, characterized in that Noh design support device. 5. The logic synthesis function description language conversion means implements the function diagram information as a selector without priority after logic synthesis of conditional transfer in a data path diagram indicated by the function diagram information. A priority-less selector configuration logic synthesis functional description language conversion means for converting to a priority-less selector configuration logic synthesis function description language, and the same function diagram information in a data path diagram indicated by the function diagram information A priority-configured selector configuration suitable for the logic synthesizing means, which realizes condition transfer as a selector with priority after logic synthesis, and a priority-configured selector configuration logical-synthesis functional description language conversion means; , The same function diagram information has no priority after logical synthesis of the condition transfer in the data path diagram indicated by the function diagram information. And a non-priority tri-state configuration logic synthesis functional description language conversion means for converting into a non-priority tri-state configuration logic synthesis functional description language, which is suitable for the logic synthesis means. Priority conversion for realizing a conditional transfer in the data path diagram indicated by the function diagram information as a tristate with priority order after logic synthesis, converting to a selector configuration logic synthesis function description language with priority order suitable for the logic synthesis means 5. The functional design support apparatus according to claim 4, further comprising a function description language conversion unit for ordering tristate configuration logic synthesis. 6. The logic synthesizing means includes a state transition diagram-oriented logic synthesizing means, a data path-oriented logic synthesizing means, and a random logic-oriented logic synthesizing means, wherein the logic synthesizing function description language converting means comprises: State transition diagram function description language conversion means for converting information about the state transition diagram in the function diagram information into a state transition diagram function description language suitable for the state transition diagram oriented logic synthesis means, and data in the function diagram information Data path diagram function description language conversion means for converting the information about the path diagram into a data path diagram function description language suitable for the data path oriented logic synthesis means, and information about the truth table in the function diagram information as the random logic The truth table function description language converting means for converting the truth table function description language suitable for the direction logic synthesizing means, and the information on the logical expression table in the function diagram information Functional design support apparatus according to claim 4, characterized in that it has a logical expression hardware description language conversion means for converting the logical expression hardware description language suitable for the logical direction logic synthesis means. 7. The logic synthesizing function description language converting means, after function synthesizing condition data transfer for each facility, data path diagram information for each facility such as a register or terminal on the data path diagram among the function diagram information. A priority-less selector configuration suitable for the logic synthesizing means, which is realized as a selector without priority, and is converted into a logic-description functional description language without priority selector, a logic-description functional description language conversion means, and data for each facility. Prioritized selector configuration logic for converting the path diagram information into a priority-assigned selector configuration logic synthesis function suitable for the logic synthesis means that realizes condition transfer for each facility as a selector with logic priority after logic synthesis Synthesizing function description language conversion means, and data path diagram information for each facility, A priority-less tristate configuration logic synthesis function for converting each condition transfer as a tristate without priority after logic synthesis, which is suitable for the logic synthesis means, into a function description language for tristate configuration logic synthesis Description language conversion means and data path diagram information for each facility are realized as a tri-state with priority order after condition synthesis for each facility is logically synthesized. A function description language conversion unit for tri-state configuration logic synthesis with priority conversion for converting into a function description language, and reading function diagram information from the storage device, and a facility on a data path diagram indicated by the function diagram information For each time, considering the circuit model configuration desired after logic synthesis, Functional derivation language conversion means for logical synthesis, the selector configuration with priority, logic descriptive language conversion means for logic synthesis, tristate configuration without priority, functional descriptive language conversion means for logic synthesis, or tristate configuration with priority The functional design support apparatus according to claim 4, wherein the functional description language conversion means for logic synthesis is driven. 8. The functional simulation means simulates the operating function of the logic circuit for a predetermined simulation time t based on the state value at the simulation time T, thereby simulating the simulation time T.
Function simulator means for executing a time forward step function simulation for obtaining a state value at + t, and input for inputting test data used when the function simulator means is executed and displaying a function simulation result obtained by the execution of the function simulator means. Display means and control means for controlling the transfer of the test data from the input display means to the functional simulator means and for controlling the transfer of the functional simulation result from the functional simulator means to the input display means. The functional design support apparatus according to claim 1, wherein: 9. The function simulator means is a simulation time T−n × t (where n is an integer of 1 or more).
9. The functional design support device according to claim 8, further comprising a function of executing a backward time functional simulation for obtaining a state value in. 10. The function description language, wherein the input display means inputs the test data in a function description language that describes an operation function of a logic circuit in a text base and displays the result of the function simulation in the function description language. 10. The functional design support according to claim 8 or 9, further comprising input display means, and the control means includes function description language input display control means for controlling the function description language input display means. apparatus. 11. The input / display means inputs, as the test data, a functional diagram format pattern on a functional diagram that expresses an operation function of a logic circuit by a diagram element such as a figure, a table, or a character, and outputs the functional simulation result. It has a functional diagram format pattern input display means for displaying on the functional diagram, and the control means has a functional diagram format pattern input display control means for controlling the functional diagram format pattern input display means. The functional design support device according to claim 8 or 9. 12. The function diagram format pattern input / display means inputs a data path diagram format pattern on a data path diagram format representation diagram that represents an operation function of a logic circuit as a data path diagram, and outputs the function. The data path diagram format pattern input display means for displaying the simulation result on the data path diagram format representation diagram, the functional diagram format pattern input display control means,
12. The functional design support apparatus according to claim 11, further comprising data path diagram format pattern input display control means for controlling the data path diagram format pattern input display means. 13. The function diagram format pattern input display means inputs a state transition diagram format pattern on a state transition diagram format representation diagram that represents an operation function of a logic circuit in a state transition diagram as the test data, and outputs the function. There is a state transition diagram format pattern input display means for displaying a simulation result on the state transition diagram format representation diagram, the functional diagram format pattern input display control means,
The functional design support apparatus according to claim 11, further comprising state transition diagram format pattern input display control means for controlling the state transition diagram format pattern input display means. 14. The functional diagram format pattern input / display means inputs a logical equation format pattern on a logical equation format representation diagram expressing the operation function of a logic circuit by a logical equation as the test data, and outputs the functional simulation result. A logical expression format pattern input display means for displaying on the logical expression format representation diagram, the functional diagram format pattern input display control means,
12. The functional design support apparatus according to claim 11, further comprising logical expression format pattern input display control means for controlling the logical expression format pattern input display means. 15. The function diagram format pattern input / display means inputs a truth table format pattern on a truth table format representation diagram expressing the operation function of a logic circuit in a truth table as the test data, and the function. It has a truth table format pattern input display means for displaying a simulation result on the truth table format representation diagram, the functional diagram format pattern input display control means,
12. The functional design support apparatus according to claim 11, further comprising truth value table format pattern input display control means for controlling the truth value table format pattern input display means. 16. The input display means has a simulation control panel display means for displaying a simulation control panel for performing execution control of functional simulation of the function simulator means and input control of the test data, and the control means comprises: 10. The functional design support device according to claim 8 or 9, further comprising simulation control panel display control means for controlling the simulation control panel display means. 17. The function simulator means has a state value storage table for holding a history of state value changes at all simulation times for each circuit model forming a logic circuit. Functional design support device described in. 18. The function simulator means updates the state value by selecting an operation from an event list composed of a list of events storing state value change information and an event from the event list and selecting a process according to the type of the event. And an element for which a new state value change may occur by updating the state value of the event processing means, and when the new state value change occurs, the change information is stored in the event. Then, the event processing means extracts the event from the event list, and the event type for judging the type of the event extracted by the event extraction processing means. Judgment processing means, normal event processing means for updating the state value, clock signal 10. The functional design according to claim 8, further comprising clock event processing means for updating the state value of the register and register input data event processing means for updating the state value of the input data signal of the register. Support device. 19. The input display means inputs an input signal having an n-bit width (n ≧ 2) in which each bit is represented by a logic signal of any one of logic signals 0, 1, X and Z, Each bit of the input signal is an encoded bit composed of 0 drive bit indicating whether the bit can take a logical value 0 and 1 drive bit indicating whether the bit can take a logical value 1 Coding means for generating a coded input signal by coding, a 0 drive word consisting of n 0 drive bits and a 1 drive word consisting of n 1 drive bits; and n 0's. 0 drive word consisting of drive bits and n
A coded output signal composed of 1 drive word consisting of 1 drive bit is input, and coded with the m-th (1 ≦ m ≦ n) 0 drive bit of the 0 drive word of the coded output signal. M of 1 drive word of output signal
The set with the 1st drive bit is logical signals 0, 1, X
And Z, and decoding means for generating an output signal having an n-bit width by restoring the representation by the logical signal of any one of Z and Z, the functional simulator means receiving the encoded input signal, ZX conversion means for generating a converted coded input signal by converting coded bits corresponding to the logical signal Z out of n coded bits of the coded input signal to coded bits corresponding to the logical signal X. A 0 drive word and a 1 drive word corresponding to an operation result of a logical operation to be a functional simulation based on the 0 drive word and the 1 drive word of the conversion encoded input signal 10. The function setting device according to claim 8 or 9, further comprising output signal evaluation means for generating the encoded output signal by determining Support device. 20. The ZX conversion means receives an encoded input signal from the encoding means, and outputs 0 drive words of the encoded input signal and 1 of the encoded input signal.
A logical sum evaluation means for calculating a logical sum with the drive word and outputting the calculation result as an intermediate result; and inputting the intermediate result, calculating the logical NOT of the intermediate result, and using the calculated result as a ZX conversion mask. Bit inversion means for outputting, the encoded input signal and the ZX conversion mask are input,
The logical sum of the 0 drive word of the encoded input signal and the ZX conversion mask is calculated, and the calculation result is output as the 0 drive word of the converted encoded input signal, and the 1 drive word of the encoded input signal and the 20. ZX conversion mask processing means for calculating a logical sum with a ZX conversion mask and outputting the calculation result as one drive word of the same conversion encoded input signal. Functional design support device. 21. The functional design support according to claim 8, further comprising a test vector generation means for generating a test vector describing the contents of the test data based on the result of the functional simulation. apparatus. 22. The control means is divided into a function simulator control section for controlling the function simulator means and an input display control section for controlling the input display means. Functional design support device described in. 23. The function simulator means simulates the operation function of the logic circuit for a simulation time m × t (where m is an integer of 2 or more) based on the state value at the simulation time T, thereby simulating the simulation time T + m ×. The control means further has a function of executing a time forward jump function simulation for obtaining a state value at t, and the control means controls the time forward step function simulation by executing the time forward jump function simulation. Forward jump execution control means for controlling execution, pattern setting control means for setting the test data in the functional simulator means, and the functional simulation result from the functional simulator means Functional design support apparatus according to claim 8, characterized in that it has a non-functional simulation result capture controls means. 24. The function simulator means simulates the operation function of the logic circuit for a simulation time m × t (where m is an integer of 2 or more) based on the state value at the simulation time T, thereby simulating the simulation time T + m ×. Further, the function simulator means has a function of executing a time forward jump function simulation for obtaining a state value at t, and the time backward movement functional simulation of the function simulator means is a time backward step functional simulation for obtaining a state value at a simulation time T-t.
A time backward jump function simulation for obtaining a state value at a simulation time T−L × t (where L is an integer of 2 or more), and the control means controls the execution of the time forward step functional simulation. Execution control means, forward jump execution control means for controlling execution of the time forward jump function simulation, reverse step execution control means for controlling execution of the time backward step functional simulation,
Reverse jump execution control means for controlling the execution of the time backward jump functional simulation, pattern setting control means for setting the test data in the functional simulator means, and importing the functional simulation result from the functional simulator means The functional design support apparatus according to claim 9, further comprising a control unit. 25. The input display means includes table format pattern input display means for inputting a table format pattern as the test data and displaying the functional simulation result in a table format, and the control means comprises the table. 9. A table format pattern input display control means for controlling the format pattern input display means is provided.
Alternatively, the functional design support device according to item 9. 26. The input display means includes a waveform format pattern input display means for inputting a waveform format pattern as the test data and displaying the functional simulation result in a waveform format, and the control means comprises the waveform 10. The functional design support apparatus according to claim 8, further comprising a waveform format pattern input display control means for controlling the format pattern input display means. 27. The input display means inputs a memory pattern of a memory of a logic circuit as the test data,
It has a memory pattern input display means for displaying a memory pattern as a result of the functional simulation, and the control means has a memory pattern input display control means for controlling the memory pattern input display means. The functional design support device according to claim 8. 28. The input display unit displays past test data used in past executions of the function simulator unit in a tabular form, and displays test data selected from the past test data as new data. 10. The pattern history input display means for inputting as test data is provided, and the control means has a pattern history input display control means for controlling the pattern history input display means. The described functional design support device. 29. A functional design support method for supporting functional design of a logic circuit, comprising: a test data input process for inputting test data; and a logic circuit operation for a predetermined simulation time based on the input test data. A functional design support method comprising: a time advance function simulation process for simulating a function; and a function simulation result display process for displaying a function simulation result obtained by executing the time advance function simulation process. 30. The test data in the test data input process is a functional diagram format pattern on a functional diagram that expresses an operation function of a logic circuit by a diagram element such as a figure, a table or a character, and the functional simulation result display 30. The functional design support method according to claim 29, wherein the processing displays the functional simulation result on the functional diagram. 31. A functional design support method for supporting functional design of a logic circuit, wherein state values at all simulation times up to the current simulation time of the logic circuit are stored in advance, and simulation times are past simulation times. Time backward functional simulation processing for obtaining the state value of the logic circuit at the past simulation time as a functional simulation result by returning to time, and functional simulation displaying the functional simulation result obtained by executing the time backward functional simulation processing. A method for supporting functional design, comprising: result display processing. 32. The time backward functional simulation process is characterized in that the state value at the immediately preceding past simulation time of the logic circuit is obtained as the functional simulation result by returning the simulation time to the immediately preceding past simulation time. Claim 31
Functional design support method described in. 33. The functional simulation result display processing displays the functional simulation result on a functional diagram expressing the operation function of the logic circuit by a diagram element such as a figure, a table or a character. Functional design support method described in. 34. A functional design support method for supporting functional design of a logic circuit, wherein a state value storage table capable of holding state values at all simulation times of the logic circuit is provided in advance, and test data is stored. A test data input process for inputting the test data, a test data setting process for setting the input test data in the state value storage table as a state value at the simulation time T of the logic circuit, and a state value at the simulation time T of the logic circuit. A state value reading process for reading the state value from the state value storage table held, and a time advance function simulation process for simulating the operation function of the logic circuit for a predetermined simulation time t based on the read state value, To execute the time advance function simulation process The time advance function simulation result writing process of writing the time advance function simulation result obtained as described above into the state value storage table as the state value at the simulation time T + t of the logic circuit, and the simulation time of the logic circuit written in the state value storage table The time advancing function simulation result display process for displaying the time advancing function simulation result as a state value at T + t, and the simulation time T + t is set as a new simulation time T after the time advancing function simulation result displaying process is executed. By repeatedly executing the value reading process, the time advance function simulation process, the time advance function simulation result writing process, and the time advance function simulation result display process.
The process of setting the state values at all simulation times up to the simulation time T0 of the logic circuit in the state value storage table, and the current simulation time of the state value storage table from the simulation time T0 to the simulation time T0-nxt ( However, by changing the value of n to an integer of 1 or more), the time backward function simulation processing for obtaining the state value at the simulation time T0-n × t of the logic circuit held in the state value storage table as the time backward function simulation result A time-reverse function simulation result display process for displaying the time-reverse function simulation result obtained by executing the time-reverse function simulation process. 35. The test data in the test data input process is a functional diagram format pattern on a functional diagram that expresses an operation function of a logic circuit by a chart element such as a figure, a table or a character, and the time advance function simulation. The result display process displays the time forward function simulation result on the functional diagram, and the time backward function simulation result display process displays the time backward function simulation result on the functional diagram. Item 34. The functional design support method according to Item 34. 36. A function of inputting design constraint information from the outside, a function of reading functional diagram information relating to the functional diagram described by the functional diagram editor means from the storage device, and setting of design constraint information on the functional diagram. A design constraint information inputting unit having a function to perform, and function diagram information relating to a function diagram in which the design constraint information is set by the design constraint information inputting unit is read from the storage device, and the presence or absence of a contradiction in the design constraint information is verified Design constraint information check means and function diagram information relating to the function diagram for which design constraint information is set by the design constraint information input means is read from the storage device, the design constraint information is analyzed on the function diagram, and the design constraint description language is read. Design constraint description language conversion means for generating a function description language, the function description language generated by the function description language conversion means, and the design The system further comprises a language-based functional simulator for inputting the design constraint description language generated by the constraint description language conversion unit and performing a functional simulation on the functional description language, wherein the functional simulation unit is designed by the design constraint information input unit. The functional diagram information relating to the functional diagram in which the constraint information is set is read from the storage device, and the timing verification is performed by performing the delay simulation on the functional diagram based on the design constraint information. The functional design support according to claim 1, wherein the function description language generated by the conversion unit and the design constraint description language generated by the design constraint description language conversion unit are input to generate netlist information. apparatus. 37. The design constraint information input means has a function of inputting a periodic waveform to a clock input pin of a logic circuit and a function of setting a periodic waveform to a clock input pin on the functional diagram, Design constraint description language conversion means, for the periodic waveform set on the functional diagram by the design constraint information input means,
37. The functional design support apparatus according to claim 36, which generates a design constraint description language for setting timing constraint information such as register setup time and hold time in the logic synthesizing means. 38. The design constraint information input means inputs a fan-out capacitance to an external input pin of a logic circuit and a fan-in capacitance to an external output pin of the logic circuit, and an external input pin on the functional diagram. It has a function of setting a fan-out capacity and a function of setting a fan-in capacity with respect to an external output pin on the functional diagram. The design constraint description language conversion means uses the design constraint information input means on the functional diagram. 4. A design constraint description language for setting the information of fan-out capacity and fan-in capacity set in the above in the logic synthesizing means is generated.
6. The functional design support device described in 6. 39. The design constraint information input means has a function of inputting a delay value for a terminal that is a component that does not have a state value storage capability, a register that has a storage capability, and an external pin in a logic circuit, It has a function to set the delay value to the terminal on the function diagram, a function to set the delay value to the register on the function diagram, and a function to set the delay value to the external pin on the function diagram. The functional simulation means performs the delay simulation based on the delay values set in the terminals, registers and external pins on the functional diagram by the design constraint information input means, and the design constraint description language conversion means sets the design constraint information. Generating a design constraint description language for setting delay information based on the delay value set on the functional diagram by the input means in the logic synthesis means Functional design support apparatus according to claim 36, wherein the door. 40. A functional design support method for supporting functional design of a logic circuit, comprising: a functional diagram creation process for creating a functional diagram using diagram elements such as figures, tables, characters; Diagram error checking process for verifying the function diagram, function diagram correcting process for correcting the function diagram using the chart elements, and design constraint information input process for inputting design constraint information and setting the design constraint information on the function diagram. And a design constraint information error check process for verifying whether or not there is an error in the design constraint information, a design constraint information correction process for correcting the design constraint information on the functional diagram, and a logic from the functional diagram and the design constraint information. A function verification process for performing circuit function verification and timing verification on a function diagram, and a language conversion process for generating a function description language and a design constraint description language from the function diagram and design constraint information. Functional design support method, characterized in that are e.