JPH07221688A - Received electric field detection circuit - Google Patents

Abstract

PURPOSE:To easily perform a correction for the loss or gain from a received input defining point up to a received electric field detection means even if they are deviated from those at the time of an adjustment. CONSTITUTION:The loss of a signal transmission line 8 exists from a received input defining point 100 to the input terminal of a reception part 1. By the reception part 1, a level adjustment circuit 2, an analog/digital detection circuit 3 and a ROM 5, the digital signal S 16 of the value corresponding to the signal intensity (received electric field intensity) of a reception signal S 10 in the received input stipulated point 100 when no change exists in loss is generated. From a dip switch 7, the loss or gain correction value of the line 8 is inputted. This correction signal S 18 becomes the address signal of a ROM 6 and generates the digital signal S 17 corresponding to the correction value. An adder 4 adds a digital signal S 14 and the digital signal S 17 and the correction of the received electric field intensity in the stipulated point 100 is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a received electric field detection circuit for detecting the signal strength (also called received signal strength) of a received signal in a radio frequency band, and particularly to mobile communication such as a car telephone system which receives received signals of a plurality of channels. The present invention relates to a reception electric field detection circuit suitable for use in a base station.

[0002]

2. Description of the Related Art In a conventional mobile communication base station such as an automobile telephone system, generally, a receiving signal sent from a plurality of mobile devices (channels) is received by each corresponding receiver.
The received signal strength of this received signal is measured by a built-in received electric field detection circuit, and channel connection control of the system is performed according to the received signal strength. In the base station, the received signals of all the channels received by the antenna are introduced into a signal distributor provided on the rack and further distributed to each receiver. In the base station, it is necessary to accurately compare the received signal strengths of the receivers in order to control the channel connection, and an appropriate point such as the input end of the signal distributor or the output end of the antenna is received and input. The reception signal strength at this reception input specification point is used as a standard for the reception signal strength (also the reception electric field strength) of the receiver.

Here, the signal distributor and the receiver are generally connected to each other via a signal transmission line for each channel. The loss of this signal transmission line depends on the length and channel (frequency) of this signal transmission line. Also, the distribution loss of the signal distributor often differs for each output terminal. Therefore, when the reception input regulation point is the input end of the signal distributor, the reception signal at each input end of the receiver is the same even if the reception signal strength at this input end is the same for each channel. The strengths often differ from each other. Therefore, in the reception electric field detection circuit of each receiver, it is necessary to correct the measured (detected) received signal strength for each receiver and set the comparison target under the same condition.

In the conventional received electric field detection circuit of this type, the difference in received signal strength generated between the respective input terminals of the receiver is corrected by a fixed value (for example, Japanese Patent Laid-Open No. 4-342).
321: Received electric field detection circuit of wireless communication device, and JP-A-4-266223: Wireless receiver).

[0005]

In the above-mentioned conventional received electric field detection circuit, the signal strength correction amount for each receiver is fixed at the value at the time of initial adjustment. Therefore, each receiver is mounted on the rack during operation. Even if the amount to be corrected for accurate measurement of the received signal strength changes due to changes in the position, changes in the electric field strength detection circuit over time, etc., this correction amount cannot be easily changed. .

[0006]

The received electric field strength detection circuit according to the present invention comprises a received electric field strength detecting means for generating a first digital signal having a value corresponding to the signal strength of a received signal received at an input end, and the receiving electric field strength detecting means. Second showing the correction value of the signal strength of the signal
Digital signal generating means for generating a digital signal, adder means for generating a third digital signal by adding the first digital signal and the second digital signal, and the third digital signal generating means.
First memory means for producing a fourth digital signal of a value corresponding to the digital signal of.

In the received electric field detection circuit, the received signal is a signal received from a reception input regulation point via a signal transmission line, and the received electric field detecting means receives the received electric field corresponding to the signal strength of the received signal. A receiver that produces a detection voltage,
A plurality of digital signal generating means, comprising: a level adjusting circuit for adjusting the level of the received electric field detection voltage; and an analog-digital converter for generating the first digital signal from the level-adjusted received electric field detection voltage. A correction value selection switch for selectively outputting a fifth digital signal corresponding to any one of the values, and a second memory circuit for generating the second digital signal having a value corresponding to the fifth digital signal. And the value of the fourth digital signal is a value obtained by fixedly correcting the value of the first digital signal as the signal strength of the received signal at the reception input regulation point.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a received electric field detection circuit according to an embodiment of the present invention.

The received signal S10 in the radio frequency band is received from the output terminal of the antenna (not shown) of the mobile communication base station via the coaxial line, and the reception input regulation point 1 is the input terminal of the signal distributor.
00 is supplied. The reception signal S10 passes through one output end of the signal distributor, further passes through the coaxial line, and is supplied to the reception unit (RX) 1 as a reception signal S11. Here, the signal distributor and the coaxial line are collectively referred to as a signal transmission line 8. The signal transmission line 8 may include an amplifier. The reception input regulation point 100 may be the output end of the antenna. In this case, the signal transmission line 8 also includes a coaxial line between the antenna and the signal distributor.

The receiving section 1 generates a received electric field detection voltage S12 having a level corresponding to the signal strength of the received signal S11 (received signal strength). In addition, the reception signal S11
You may have the demodulation part of. Received electric field detection voltage S12
Is subjected to level adjustment (including output adjustment and offset adjustment) by the level adjustment circuit (ADJ) 2 and becomes the level adjustment signal S13. This level adjustment is performed to correct the gain of the receiving unit 1 to a standard value and to adjust the DC potential of the received electric field detection voltage S12 to the proper input offset value of the analog / digital conversion circuit (A / D) 3. is there. This level adjustment is also performed in order to absorb variations in gain and offset between the plurality of receiving units (1) used for other channels. Analog-digital conversion circuit 3
Converts the level adjustment signal S13 into a digital signal S14.

On the other hand, the DIP switch (SW) 7 has a correction signal S which is a digital signal corresponding to a correction value described later.
Yields 18. The correction signal S18 is an address signal for the ROM 6. A table corresponding to the correction signal S18 is prepared in advance in the ROM 6, and when the correction signal S18 is input, a digital signal S17 having a value corresponding to the correction signal S18 is generated.

The adder (ADD) 4 has a digital signal S1.
4 and the digital signal S17 are added to obtain the digital signal S1.
Yields 5. This digital signal S15 is used as an address signal for the ROM 5. ROM5 is digital signal S1
A digital signal S16 corresponding to a value of 5 is produced. Here, the digital signal S from the analog / digital converter 3
The value of 14 corresponds to the signal strength of the received signal S11 at the input end of the receiving unit 1, whereas the value of the digital signal S16 generated from the ROM 5 is the value when the value of the digital signal S17 is zero. It corresponds to the signal strength of the received signal S10 at the input regulation point 100. That is, ROM5
The table stores the values obtained by fixedly correcting the loss or gain due to the signal transmission line 8 from the digital signal S13.

It is obvious that once the above-mentioned table of the ROM 5 (correction value of loss or gain of the signal transmission line 8) is set, it cannot be easily changed. DIP switch 7
Is a correction signal S18 corresponding to one of a plurality of settable correction values when the loss of the signal transmission line 8 changes.
Is generated, the value of the digital signal S15 which is the address signal of the ROM 5 is changed, and the loss correction value of the signal transmission path 8 is substantially changed. Therefore, the ROM 5 can generate the digital signal S16 that accurately represents the reception electric field strength of the reception signal S10 at the reception input regulation point 100. Since it is extremely easy to change the correction value by operating the DIP switch 7 described above, the correction value can be used for correction of changes in the received electric field detection voltage S12 due to changes over time of the receiving unit 1, changes in temperature conditions, and the like.

FIG. 2 is a diagram showing the relationship between the input digital value (digital signal S15) and the output digital value (digital signal S16) in the ROM 5 used in this embodiment, and FIG. 3 is the DIP switch 7 of this embodiment. FIG. 5 is a diagram showing a correction value given to, a setting state of the DIP switch 7 corresponding to the correction value, and a correction signal S18.

The operation of this embodiment will be described in more detail with reference to FIGS. 1, 2 and 3.

As shown in FIG. 2, the ROM 5 stores the input digital value (digital signal S15) and the reception input regulation point 10.
Data corresponding to the received signal strength (received electric field strength) at 0, that is, the output digital value (digital signal S16) is stored. In the initial adjustment of the electric field strength detection circuit, the level adjustment circuit 2 adjusts the magnitude and offset of the received electric field detection voltage S12 so that the digital signal S17 is not added by the adder 4 so as to match the data of FIG. Make adjustments. This level adjustment is performed assuming that the signal transmission line 8 has a certain gain or loss. That is,
When the loss of the signal transmission line 8 is 4 dB, the value of the digital signal S16 is the signal of the reception signal S10 at the reception input regulation point 100 when the reception signal S11 having the signal strength of −104 dBm is input to the input end of the reception unit 1. Strength-100 dB
m.

Now, the DIP switch 7 operates when the gain of the signal transmission line 8 is changed from the initial adjustment state.
This is a circuit for setting a correction value for correcting this change value. As shown in FIG. 3, the switch 7 outputs a 3-bit correction signal S18 that sets a correction value from +1.5 dB to −1.5 dB at 0.5 dB intervals. That is, +0.
If 5 dB correction is required, set switch 7 to "001".
If a correction value of -0.5 dB is required, switch 7
Is set to "111" and the switch 7 is set to "000" when correction is unnecessary.

Here, the signal strength of the received signal S10 is -1.
Since it is 10 dBm or more and it is necessary to detect this in 0.5 dB steps, the number of output bits of the analog-digital converter 3 is 10 bits. Therefore, the adder 4 and the ROM 5 also perform signal processing with 10 bits. Although only 3 bits are required to set the correction value of the DIP switch 7, it is necessary to match the number of bits of the correction signal S18 with the number of bits of the adder 4. The ROM 6 is the adder 4 of the switch 7.
It is provided to adjust the number of bits and interface with and.

That is, the ROM 6 converts the correction value (correction signal S18) indicated by 3 bits into the correction value (digital signal S17) of 10 bits. The adder 4 generates a digital signal S15 by adding the digital signal S14 having the information of the received signal strength at the input end of the receiving section 1 and the digital signal S17 having the information of the correction value. As a result, R
The OM5 is a digital signal S1 having a value corresponding to an accurate reception signal strength (reception electric field strength) at the reception input regulation point 100.
Will result in 6.

Next, a specific application of the electric field strength detection circuit according to this embodiment will be described.

When this electric field strength detection circuit is mounted on the rack of the above-mentioned mobile communication base station, the gain or loss from the reception input regulation point 100 to the input end of the receiving section 1 during operation is equal to the value set at the time of adjustment. Do not necessarily match. In addition, when a plurality of electric field intensity detection circuits are mounted, the values vary depending on the mounting position. For example, + 4d
If the loss estimated as B is actually +3.5 dB, the signal strength at the reception input regulation point 100 is -100.
Despite being dBm, if the detected signal strength is not corrected, it becomes -99.5 dB. In this way, when the received electric field strength is detected in the initial adjusted state as it is, the received electric field strength is detected in which the error amount changed from the initial state is shifted as it is.

Therefore, in the present embodiment, the dip switch 7 is set so that the received electric field strength is inversely shifted by the amount of the above-mentioned shifted error. In the above example, the digital signal S
Since the value of 16 is increased by 0.5 dB, the dip switch 7 is set to "111", and the adder 4 adds the received signal strength by 0.5 dB. By setting the switch 7 as described above, the reception electric field detection circuit of the present embodiment can detect the electric field strength at the reception input regulation point 100 without error.

The electric field strength detection circuit of this embodiment uses the adder 4, the ROM 5, the ROM 6 and the dip switch 7 which are the individual constituent elements, and uses the analog-digital conversion circuit 3
Although the digital signal S14 from the above is added to the above-mentioned correction value and the reception electric field strength at the reception input regulation point 100 is detected, the above-mentioned digital signal processing can also be performed by a computer circuit including a microprocessor and a ROM. Of course.

[0025]

As described above, according to the present invention, the first digital signal which is the information of the received electric field strength and the second digital signal which is used as the correction value of the received electric field strength are added to each other to obtain the third digital signal. A signal is generated, and a fourth digital signal having a value corresponding to this third digital signal is generated from the first memory means, so that the loss or gain from the reception input regulation point to the reception electric field detection means is adjusted. Even if there is an error in the value, the correction can be easily performed, and the reception electric field strength at the reception input regulation point can always be detected accurately.

[Brief description of drawings]

FIG. 1 is a block diagram of a received electric field detection circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between an input digital value (digital signal S15) and an output digital value (digital signal S16) in a ROM 5 used in this embodiment.

FIG. 3 is a diagram showing a correction value given to the DIP switch 7 used in this embodiment, a setting state of the DIP switch 7 corresponding to the correction value, and a correction signal S18.

[Explanation of symbols]

 1 receiver (RX) 2 level adjustment circuit (ADJ) 3 analog / digital circuit (A / D) 4 adder (ADD) 2, 6 ROM 7 dip switch (SW) 8 signal transmission line 100 reception input regulation point

Claims (2)

[Claims] 1. A reception electric field strength detecting means for generating a first digital signal having a value corresponding to the signal strength of a reception signal received at an input end, and a second showing a correction value of the signal strength of the reception signal.
Digital signal generating means for generating a digital signal, adder means for generating a third digital signal by adding the first digital signal and the second digital signal, and the third digital signal generating means.
A first memory means for generating a fourth digital signal having a value corresponding to the digital signal of. 2. The reception signal is a signal received from a reception input regulation point via a signal transmission line, and the reception electric field detection means generates a reception electric field detection voltage corresponding to a signal strength of the reception signal. A digital signal generator, a level adjusting circuit that adjusts the level of the received electric field detection voltage, and an analog-digital converter that generates the first digital signal from the level-adjusted received electric field detection voltage. Is a correction value selection switch for selectively outputting a fifth digital signal corresponding to any one of a plurality of values, and a second value generating a second digital signal having a value corresponding to the fifth digital signal. A memory circuit, the value of the fourth digital signal fixedly complements the value of the first digital signal as the signal strength of the received signal at the reception input regulation point. The received electric field detection circuit according to claim 1, which is a corrected value.