JPH07221211A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH07221211A JPH07221211A JP3305494A JP3305494A JPH07221211A JP H07221211 A JPH07221211 A JP H07221211A JP 3305494 A JP3305494 A JP 3305494A JP 3305494 A JP3305494 A JP 3305494A JP H07221211 A JPH07221211 A JP H07221211A
- Authority
- JP
- Japan
- Prior art keywords
- package
- ceramic
- lid
- chips
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、半導体装置の実装密
度を向上させることを目的とする。半導体装置の単位体
積当たりの機能を向上させるためには、パタ−ンル−ル
を小さくし素子チップ内での回路の高集積化をはかると
いう方法と、チップの収納密度を向上させるというふた
つの方法がある。本発明は後者の改良に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention aims to improve the packaging density of semiconductor devices. In order to improve the function per unit volume of a semiconductor device, there are two methods of reducing the pattern rule to achieve high integration of the circuit in the element chip and improving the packing density of the chip. There is. The present invention relates to the latter improvement.
【０００２】[0002]
【従来の技術】半導体素子はパッケ−ジに収容されるこ
とが多い。パッケ−ジは樹脂モ−ルドパッケ−ジ、セラ
ミックパッケ−ジ、サ−デイップパッケ−ジなどがあ
る。樹脂モ−ルドはチップやリ−ドフレ−ムを型に入
れ、樹脂を流し込み硬化させるものである。安価であり
最も普通に利用されている。しかし放熱性が悪い。気密
性にも劣る。セラミックパッケ−ジは、アルミナの薄板
を積層して中央部に矩形状の空間を形成したものであ
り、ここには電極配線パタ−ンが印刷してある。配線パ
タ−ンの端にはピンが多数接続してある。中央部のメタ
ライズ層に、半導体チップをダイボンドし、チップの電
極パッドと、配線パタ−ンとをワイヤボンデイングによ
り接続する。このあとセラミックの蓋をして内部を密封
する。2. Description of the Related Art Semiconductor devices are often housed in packages. As the package, there are a resin mold package, a ceramic package, and a dip package. The resin mold is one in which chips and lead frames are put in a mold and the resin is poured and cured. It is cheap and the most commonly used. However, the heat dissipation is poor. It is also inferior in airtightness. The ceramic package is formed by laminating thin alumina plates to form a rectangular space in the center, and an electrode wiring pattern is printed on the space. A large number of pins are connected to the ends of the wiring pattern. A semiconductor chip is die-bonded to the central metallization layer, and the electrode pads of the chip and the wiring pattern are connected by wire bonding. After this, a ceramic lid is placed and the inside is sealed.
【０００３】セラミックパッケ−ジは高価であるが、ア
ルミナを使うので熱伝導度が高く放熱性が良い。また気
密性にも優れている。高速で動作し大量の熱を発生する
素子や、集積度が高くて熱発生密度の高い素子等のパッ
ケ−ジとして最適である。Although a ceramic package is expensive, since it uses alumina, it has high thermal conductivity and good heat dissipation. It also has excellent airtightness. It is optimal as a package for devices that operate at high speed and generate a large amount of heat, or devices that have a high degree of integration and high heat generation density.
【０００４】従来は、一つのパッケ−ジにはただ一つの
半導体チップが収納されていた。セラミックパッケ−ジ
の中央部のキャビテイは矩形状で、素子の形状寸法と適
合するように作られる。パッケ−ジのキャビテイには１
枚のチップしか取り付けることができない。Conventionally, only one semiconductor chip was stored in one package. The central cavity of the ceramic package is rectangular in shape and is made to fit the geometry of the device. 1 for package cavities
Only one chip can be attached.
【０００５】[0005]
【発明が解決しようとする課題】１枚より多くの半導体
チップを同じパッケ−ジに収納すると、より高密度実装
できるはずである。しかし単にキャビテイを広げて、広
いキャビテイにふたつのチップを並べて取り付けたとし
てもそれは実装密度を上げることにはならない。パッケ
−ジの面積、容積が増えるだけで意味はない。パッケ−
ジの面積を増やすことなく、半導体チップの実装密度を
向上させることが本発明の目的である。If more than one semiconductor chip is housed in the same package, higher density packaging should be possible. However, simply expanding the cavities and installing two chips side by side in the wide cavities does not increase the packaging density. There is no point in increasing the area and volume of the package. Package
It is an object of the present invention to improve the packaging density of semiconductor chips without increasing the area of the semiconductor chip.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体装置は、
セラミックパッケ−ジの蓋の裏面にも半導体チップを取
り付けるようにしている。キャビテイの底にも一つの素
子チップが付いており、蓋の裏面にもチップが付いてい
るので、ふたつのチップが一つのパッケ−ジに収納され
る。蓋の裏面にはチップを取り付けるためのメタライズ
面や、配線が印刷してあり、蓋に一つの半導体チップを
ダイボンドし、電極パッドと配線をワイヤボンドして接
続しておく。パッケ−ジのキャビテイの底にも同様にも
うひとつの素子チップをダイボンドし、配線パタ−ンと
ワイヤボンドしておく。ピンは初めからパッケ−ジに付
いているから、これでキャビテイ底の半導体チップとピ
ンの接続が取れている。蓋に取り付けている半導体チッ
プと、ピンの接続は、蓋を閉じると同時に、ピンと蓋配
線パタ−ンの接続がなされるようにする。ピンがパッケ
−ジの面に直角に伸びる場合は、一部のピンが蓋の取り
付け面まで伸びていて、蓋の配線にハンダ付けされるよ
うにする。The semiconductor device of the present invention comprises:
A semiconductor chip is also attached to the back surface of the lid of the ceramic package. Since one element chip is attached to the bottom of the cavity and another chip is attached to the back side of the lid, two chips can be stored in one package. A metallized surface for mounting chips and wiring are printed on the back surface of the lid, and one semiconductor chip is die-bonded to the lid, and electrode pads and wiring are wire-bonded to each other. Similarly, another element chip is also die-bonded to the bottom of the package cavity and wire-bonded to the wiring pattern. Since the pin is attached to the package from the beginning, the pin can be connected to the semiconductor chip on the bottom of the cavity. The semiconductor chip attached to the lid and the pin are connected so that the pin and the lid wiring pattern are connected at the same time when the lid is closed. If the pins extend at right angles to the surface of the package, then some of the pins should extend to the lid mounting surface and be soldered to the lid wiring.
【０００７】[0007]
【作用】同じセラミックパッケ−ジのキャビテイの天井
と床にあたる部分にふたつの半導体チップが互いに対向
して取り付けられる。パッケ−ジの面積を増やすことな
く、ふたつのチップを同じパッケ−ジに収納することが
できる。これにより、パッケ−ジに対するチップの実装
密度を２倍近くに高揚させることができる。In the same ceramic package, two semiconductor chips are mounted on the ceiling and floor of the cavity facing each other. Two chips can be stored in the same package without increasing the area of the package. As a result, the packaging density of the chips with respect to the package can be increased almost twice.
【０００８】セラミック蓋を、パッケ−ジ本体に接着す
ると同時に、ピンと蓋取り付けチップの電気的接続がな
される。蓋取り付けチップのパッケ−ジに対する取り付
けが難しいということはない。蓋とチップの接着、電極
パッドと配線のワイヤボンデイングは予めなされている
ので、蓋の取り付けは従来の蓋の取り付け作業とほとん
ど変わらない。At the same time that the ceramic lid is bonded to the package body, the pins and the lid mounting chip are electrically connected. It is not difficult to attach the lid mounting tip to the package. Since the bonding of the lid and the chip and the wire bonding of the electrode pad and the wiring have been performed in advance, the lid attachment is almost the same as the conventional lid attachment work.
【０００９】放熱量が増えるので、パッケ−ジ内がより
高温になる可能性がある。しかし、セラミックパッケ−
ジは放熱性に余裕をもっていることが多いので、それほ
ど高温にはならない。放熱性を高める必要があれば、蓋
にヒ−トシンクを取り付ければ良い。もしもふたつのチ
ップの間が電気的に接続されるべきものならば、両者の
距離が短縮されるので、誘導分Ｌが減少し、ノイズに対
して強くなる。Since the amount of heat radiation increases, the temperature inside the package may become higher. However, the ceramic package
Ji often has enough heat dissipation, so it doesn't get very hot. If it is necessary to improve heat dissipation, a heat sink may be attached to the lid. If the two chips are to be electrically connected to each other, the distance between the two chips is shortened, so that the inductive component L is reduced, and the chip becomes stronger against noise.
【００１０】[0010]
【実施例】図１によって本発明の実施例を説明する。セ
ラミック板が何枚か積層されたセラミックパッケ−ジが
ある。板の枚数は任意である。ここではパッケ−ジ本体
を構成するセラミック板は３枚である。第１セラミック
板１、第２セラミック板２、第３セラミック板３、第４
セラミック板４とよりなっている。第１セラミック板１
は盲板である。この上には、チップをダイボンドするた
めのメタライズ層が印刷あるいは蒸着されている。第２
セラミック板２は、中央に開口部があり、この開口部は
チップより大きい。上面にはメタライズ配線が印刷、蒸
着されている。これはチップの電極とピンを接続するも
のである。放射状になった配線パタ−ンである。Embodiment An embodiment of the present invention will be described with reference to FIG. There is a ceramic package in which several ceramic plates are laminated. The number of plates is arbitrary. Here, the number of ceramic plates constituting the package body is three. First ceramic plate 1, second ceramic plate 2, third ceramic plate 3, fourth
It consists of a ceramic plate 4. First ceramic plate 1
Is a blind plate. A metallization layer for die-bonding the chip is printed or vapor-deposited on this. Second
The ceramic plate 2 has an opening at the center, and this opening is larger than the chip. Metallized wiring is printed and vapor-deposited on the upper surface. This connects the electrodes and pins of the chip. This is a radial wiring pattern.
【００１１】第３セラミック板３はより広い開口部を有
する。第２セラミック板２の上の配線パタ−ンの内側縁
が一部露出する必要があるので開口部が広くなってい
る。第４セラミック板４は外側がより狭くなっている。
これら第１〜第４セラミック板１〜４の積層体がパッケ
−ジの本体７の主要部を形成する。The third ceramic plate 3 has a wider opening. Since the inner edge of the wiring pattern on the second ceramic plate 2 needs to be partially exposed, the opening is wide. The fourth ceramic plate 4 is narrower on the outside.
The laminated body of these first to fourth ceramic plates 1 to 4 forms the main part of the main body 7 of the package.
【００１２】蓋は第５セラミック板５と第６セラミック
板６とよりなる。第６セラミック板６は盲板である。こ
の下面にはチップを取り付けるためのメタライズ層が形
成される。第５セラミック板５は、チップより大きい開
口がある。第５セラミック板５の下面には配線パタ−ン
が印刷、蒸着されている。つまり蓋の第５セラミック板
５は、本体の第２セラミック板２と同じような機能を持
つ。The lid is composed of a fifth ceramic plate 5 and a sixth ceramic plate 6. The sixth ceramic plate 6 is a blind plate. A metallization layer for mounting the chip is formed on the lower surface. The fifth ceramic plate 5 has an opening larger than the chip. A wiring pattern is printed and vapor-deposited on the lower surface of the fifth ceramic plate 5. That is, the fifth ceramic plate 5 of the lid has the same function as the second ceramic plate 2 of the main body.
【００１３】本体７の第１セラミック板１の上に第１の
半導体チップ１１がダイボンドされる。蓋８の第６セラ
ミック板６の裏面つまりキャビテイの天井に当たる部分
に第２の半導体チップ１２がダイボンドされる。第２セ
ラミック板２のメタライズ配線１３の端と、第１チップ
１１の電極パッドが、それぞれワイヤボンデイング１４
されている。多数のピン１５、１６、１７が本体のセラ
ミック板１、２、３を貫いて設けられる。ピンは４辺に
あるいは２辺に設けられる。ここでは縦型のピンを例示
しているが、横型のピンであっても良い。The first semiconductor chip 11 is die-bonded on the first ceramic plate 1 of the main body 7. The second semiconductor chip 12 is die-bonded to the back surface of the sixth ceramic plate 6 of the lid 8, that is, the portion corresponding to the ceiling of the cavity. The end of the metallized wiring 13 of the second ceramic plate 2 and the electrode pad of the first chip 11 are connected to the wire bonding 14 respectively.
Has been done. A large number of pins 15, 16, 17 are provided through the ceramic plates 1, 2, 3 of the body. The pins are provided on four sides or two sides. Although a vertical pin is illustrated here, a horizontal pin may be used.
【００１４】ピンのうちの一部は、第１チップに接続さ
れ、他の一部は第２チップ１２に接続されるべきもので
ある。ピン１５、ピン１６は第２セラミック板２の上面
のメタライズ配線パタ−ンの終端部のいずれかに接続さ
れている。これらはパッケ−ジを製作した時に既に接続
されているのである。ピンの内残りのピン１７は第３、
第４セラミック板３、４をも貫いて本体枠の上面にまで
到達している。ここでピンの頭が露出している。蓋８の
第６セラミック板６に固着した第２チップ１２の電極パ
ッドと、第５セラミック板５の下面のメタライズ配線１
８とはワイヤボンデイング１９により接続される。蓋８
を、本体７の上面に接着した時に、ピン１７の頭と、メ
タライズ配線１８とが電気的に接続される。これにより
第２チップ１２とピン１７が、結合されたことになる。
このように本体と蓋に、別々にチップをダイボンドし、
ワイヤボンデイングしておいてから、蓋を本体に接着す
るので、蓋の接着により実装が完成する。Some of the pins are to be connected to the first chip and some are to be connected to the second chip 12. The pins 15 and 16 are connected to either of the end portions of the metallized wiring pattern on the upper surface of the second ceramic plate 2. These are already connected when the package is manufactured. The remaining pin 17 of the pins is the third,
It penetrates through the fourth ceramic plates 3 and 4 and reaches the upper surface of the main body frame. The head of the pin is exposed here. The electrode pad of the second chip 12 fixed to the sixth ceramic plate 6 of the lid 8 and the metallized wiring 1 on the lower surface of the fifth ceramic plate 5
8 is connected by wire bonding 19. Lid 8
When is bonded to the upper surface of the main body 7, the head of the pin 17 and the metallized wiring 18 are electrically connected. As a result, the second chip 12 and the pin 17 are connected.
In this way, the die is die-bonded to the main body and the lid separately,
Since the lid is adhered to the main body after wire bonding, the mounting is completed by adhering the lid.
【００１５】セラミック板３、４は、上下のチップ１
１、１２のワイヤボンデイングのワイヤが接触しないよ
うに適当な厚みが必要となる。チップ１１、１２が上下
で対向するので、ピンに接続する他に、ピンを介さず、
ビアホ−ルによって、上下のメタライズ配線の一部を接
続するようにもできる。これは外部に取り出す必要のな
い端子の場合に可能となる接続である。またふたつのチ
ップをダイボンドしたメタライズ層はグランド面とする
ことができる。するとキャビテイ２０の上下にグランド
面があることになるから、外部からのノイズを遮断でき
る。The ceramic plates 3 and 4 are composed of upper and lower chips 1.
Appropriate thickness is required so that the wires of wire bonding Nos. 1 and 12 do not come into contact with each other. Since the chips 11 and 12 face each other in the vertical direction, in addition to connecting to the pin,
A part of the upper and lower metallized wirings can be connected by the via hole. This is a connection that is possible when the terminal does not need to be taken out. Further, the metallized layer obtained by die-bonding two chips can be used as a ground surface. Then, since the ground surfaces are provided above and below the cavity 20, noise from the outside can be blocked.
【００１６】縦型のピンではなく、水平のピンとする場
合は、本体のメタライズ配線とピン（リ−ドフレ−ム）
の接続は第３セラミック板の外周部を狭くし、この外側
へメタライズ配線の一部を露出させる。ここにリ−ドフ
レ−ムをろう付けする。蓋のメタライズ配線との接続
は、ビアホ−ルにより行なうことができる。第３セラミ
ック板３と第４セラミック板４にビアホ−ルを設けて、
蓋メタライズ配線１８と、本体メタライズ配線１３の一
部を接続し、本体メタライズ配線の一部を利用して外部
のピンに接続する。When the horizontal pins are used instead of the vertical pins, the metallized wiring and the pins (lead frame) of the main body are used.
In this connection, the outer peripheral portion of the third ceramic plate is narrowed and a part of the metallized wiring is exposed to the outside. The lead frame is brazed here. The via hole can be used to connect the lid to the metallized wiring. A via hole is provided on the third ceramic plate 3 and the fourth ceramic plate 4,
The lid metallized wiring 18 and a part of the main body metallized wiring 13 are connected, and a part of the main body metallized wiring is used to connect to an external pin.
【００１７】[0017]
【発明の効果】本発明は、セラミックパッケ−ジのキャ
ビテイの天井と床の部分に、チップを取り付けるので、
同一の面積のパッケ−ジであるのに２枚のチップを収容
することができる。半導体チップの実装密度が高くな
る。天井が高くなり体積は増えるが、電気部品の実装で
問題になるのは面積の不足であって、高さの増加はあま
り問題でない。結局、パッケ−ジに対してほぼ２倍の実
装密度を実現できるようになる。高密度実装を要求され
るシステム商品に本発明を利用すると極めて効果的であ
る。According to the present invention, since the chips are attached to the ceiling and floor of the cavity of the ceramic package,
Two chips can be accommodated even though the packages have the same area. The packaging density of semiconductor chips is increased. Although the ceiling rises and the volume increases, the problem in mounting electrical components is the lack of area, and the increase in height does not pose a problem. As a result, it is possible to realize a packaging density almost double that of the package. It is extremely effective to apply the present invention to a system product that requires high-density mounting.
【図１】本発明の実施例に係る半導体装置の断面図。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.
１ 第１セラミック板 ２ 第２セラミック板 ３ 第３セラミック板 ４ 第４セラミック板 ５ 第５セラミック板 ６ 第６セラミック板 ７ パッケ−ジ本体 ８ 蓋 １１ 第１半導体チップ １２ 第２半導体チップ １３ メタライズ配線 １４ ワイヤボンデイング １５ ピン １６ ピン １７ ピン １８ メタライズ配線 １９ ワイヤボンデイング 1 1st ceramic board 2 2nd ceramic board 3 3rd ceramic board 4 4th ceramic board 5 5th ceramic board 6 6th ceramic board 7 Package body 8 Lid 11 1st semiconductor chip 12 2nd semiconductor chip 13 Metallized wiring 14 Wire Bonding 15 Pins 16 Pins 17 Pins 18 Metallized Wiring 19 Wire Bonding
Claims (1)
体チップを収容するキャビテイを形成したセラミックパ
ッケ−ジ本体と、セラミック板を積層してなり中央に半
導体チップを収容する部分を持つ蓋とよりなるセラミッ
クパッケ−ジの、キャビテイの底面と、蓋の裏面とに、
それぞれ半導体チップを取り付けたことを特徴とする半
導体装置。1. A ceramic package body formed by laminating ceramic plates and having a cavity formed in the center thereof for accommodating semiconductor chips, and a lid having a portion accommodating semiconductor chips in the center formed by laminating ceramic plates. On the bottom of the cavity and the back of the lid of the ceramic package
A semiconductor device having a semiconductor chip attached thereto.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3305494A JPH07221211A (en) | 1994-02-03 | 1994-02-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3305494A JPH07221211A (en) | 1994-02-03 | 1994-02-03 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07221211A true JPH07221211A (en) | 1995-08-18 |
Family
ID=12376057
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3305494A Pending JPH07221211A (en) | 1994-02-03 | 1994-02-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07221211A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000079845A1 (en) * | 1999-06-17 | 2000-12-28 | Telefonaktiebolaget Lm Ericsson (Publ) | An arrangement for mounting chips in multilayer printed circuit boards |
| JP2001267842A (en) * | 2000-03-15 | 2001-09-28 | Mitsubishi Electric Corp | Microwave module |
| EP1069639A3 (en) * | 1999-06-29 | 2002-05-22 | Mitsubishi Denki Kabushiki Kaisha | Radio-frequency circuit module |
-
1994
- 1994-02-03 JP JP3305494A patent/JPH07221211A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000079845A1 (en) * | 1999-06-17 | 2000-12-28 | Telefonaktiebolaget Lm Ericsson (Publ) | An arrangement for mounting chips in multilayer printed circuit boards |
| US6333856B1 (en) | 1999-06-17 | 2001-12-25 | Telefonaktiebolaget Lm Ericsson (Publ) | Arrangement for mounting chips in multilayer printed circuit boards |
| EP1069639A3 (en) * | 1999-06-29 | 2002-05-22 | Mitsubishi Denki Kabushiki Kaisha | Radio-frequency circuit module |
| EP1484815A1 (en) * | 1999-06-29 | 2004-12-08 | Mitsubishi Denki Kabushiki Kaisha | Radio-frequency circuit module |
| JP2001267842A (en) * | 2000-03-15 | 2001-09-28 | Mitsubishi Electric Corp | Microwave module |
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