JPH07219808A - Emulator and its tracking method - Google Patents

Abstract

PURPOSE:To acquire the accurate executing result of tracing of an emulator. CONSTITUTION:In a tracing state of an emulator 1, the program counter value- executed actually by a microprocessor 2 is designated as one of trace acquiring conditions. At the same time, the counter value is stored in a trace memory 7 based on the trace acquiring conditions and in a state related to the data stored in the memory 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emulator tracing method and an emulator technique, and more particularly to a technique effectively applied to an emulator tracing technique having a microprocessor with a prefetch function.

[0002]

2. Description of the Related Art Emulators are sometimes used in the development of microprocessor application equipment. The emulator has a target microprocessor or a microprocessor with the same function as it. By controlling the user system while executing and stopping the user program by this microprocessor, it is possible to debug the hardware and software in the microprocessor application device. To do.

Generally, an emulator has a trace function for acquiring information on the address bus, data bus, and various information of the microprocessor during execution of real-time emulation, and the contents thereof are in bus cycle units or instruction units by disassembly. It can be displayed with. Here, the trace acquisition condition can be specified by the state of the acquisition information. Regarding this, for example, Hitachi Ltd. H8
/ 530 ASEmodel-II User's Manual P49 to P54.

Meanwhile, as the degree of integration of elements constituting a microprocessor has been improved, various functions such as a prefetch function have been incorporated in a semiconductor chip. This prefetch function is a function of pre-storing the data that the microprocessor will execute next in a predetermined memory.

In such a conventional technique, the coincidence determination of the trace acquisition condition of the emulator has been performed by comparing with the designated content in bus cycle units. Then, by comparing the address with the trace condition, the data cycle, refresh cycle and DMA (Di
The data was stored in the trace memory in the prefetch cycle other than the rect Memory Access) cycle.

[0006]

However, the inventor of the present invention has found that the conventional trace technique for an emulator having a microprocessor with a prefetch function has the following problems.

First, since the prefetched instruction may not be actually executed, erroneous data that has not been actually executed may be stored in the trace memory, and disassemble display cannot be performed. was there.
This will be described with reference to FIGS. 6 and 7.

FIG. 6 shows the instruction execution sequence of a conventional emulator. Here, it is assumed that the microprocessor sequentially executes the instructions at the addresses 101, 102, 110, 111, 112 on the memory in the order of execution of the arrows in FIG.

That is, it is assumed that the instructions at the addresses 103 to 109 are not executed. It should be noted that the addresses 103 and 104 of the instructions that are not executed are shaded to make the drawing easier to see.

Here, in the conventional bus trace, the prefetch cycle other than the data cycle, refresh cycle, and DMA cycle is traced by comparing the address with the trace acquisition condition. In this case, as shown in FIG. In addition, the instructions of the addresses 103 and 104 which are not actually executed are also stored in the trace memory 30.

Secondly, when the trace acquisition condition is set within a predetermined range by addressing, for example, the execution result is partially stored in the trace memory 30 as shown by the instructions at addresses 101, 104 and 111 in FIG. Although it will be written, the position of the signal indicating the instruction execution state for the last part may be erroneously stored at each break,
There was a problem that disassemble display could not be performed.

The signal indicating the instruction implementation state is erroneously stored for the following reason, for example. That is, the signal output from the microprocessor indicating the instruction execution state is generated slightly later than the prefetch cycle, and the position fetched in the trace memory 30 deviates from the position originally stored. Is.

The present invention has been made in view of the above problems, and an object thereof is to provide a technique capable of accurately acquiring an execution result in tracing of an emulator.

The above and other objects and novel features of the present invention will be apparent from the description of the specification and the accompanying drawings.

[0015]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

That is, the emulator tracing method of the present invention is a tracing method of an emulator, in which an electronic device to be emulated is pseudo-operated by a microprocessor provided in the emulator main body to debug the electronic device to be emulated. There
The program counter value actually executed by the microprocessor is specified as one of the trace acquisition conditions, and is also stored in the trace memory in association with the data stored in the trace memory according to the trace acquisition conditions. There is a step of doing.

The emulator tracing method of the present invention is a tracing method of an emulator, in which an electronic device to be emulated is pseudo-operated by a microprocessor provided in the emulator main body to debug the electronic device to be emulated. The microprocessor has a prefetch step of previously acquiring data to be executed at the time of its operation, the state of the bus signal at the time of prefetch output from the microprocessor and the state of the operation signal inside the emulator main body. And a step of generating the program counter value based on, and comparing the program counter value with the program counter value in the emulator.

Further, the emulator tracing method of the present invention generates a program counter value based on the instruction execution state of the microprocessor, specifies the value as one of the trace acquisition conditions, and stores it in the trace memory. A program counter generation circuit section having a function of storing in a trace memory in a state of being associated with data is provided.

[0019]

According to the present invention described above, by setting the program counter value, which means the actual execution, as the trace acquisition condition, only the actually executed data can be stored in the trace memory.

In addition, for example, when data such as an instruction to be acquired in the trace memory is specified in an address range, that is, when data such as an instruction is partially extracted, the aggregate of each data in the trace memory is The position of the signal indicating the last data execution state at the break can be accurately known by referring to the program counter value corresponding to the data.

[0021]

FIG. 1 is a block diagram of an emulator which is an embodiment of the present invention, FIG. 2 is a block diagram showing in detail a trace memory section in the emulator of FIG. 1, and FIG. 5 is a timing chart of the bus cycle timing and the generation timing of the program counter in FIG. 4, FIG. 4 is an explanatory diagram for explaining the instruction execution sequence of the emulator of the present embodiment, and FIG. 5 is a description of the instruction storage state in the trace memory. FIG.

As shown in FIG. 1, the emulator of this embodiment is an emulator 1 used, for example, in developing a microprocessor application device.

Emulation microprocessor (Microprocessor Unit, hereinafter abbreviated as MPU) 2
Has a function equivalent to that of a microprocessor possessed by an electronic device to be emulated, and can transmit an instruction execution state signal used for an emulator to a program counter generation circuit PC described later through a wiring L _1. There is.

The MPU 2 is electrically connected to the emulation control unit 4, the memory 5, the break detection circuit 6, the program counter generation circuit PC, the trace memory 7 and the emulation memory 8 via the emulation bus 3, and further the user interface unit. 9 and the user interface socket 10 are connected to the microprocessor unit and the DRAM on the user system (electronic device to be emulated).

The emulation control section 4 is a circuit section for controlling the emulation operation. Memory 5
Is a memory in which data used during emulation operation control is stored. The break detection circuit 6 is a circuit unit for detecting a user program execution stop condition. The trace memory 7 is a memory for acquiring the emulation execution result based on a trace acquisition condition described later. The emulation memory 8 is a memory that can be used by being assigned to any address of the user system.

The host CPU 11 is a component for controlling the entire emulator 1, and includes a system memory 13 and an I / O interface unit 1 via a system bus 12.
4 is electrically connected. A CRT 15 for man-machine interface and a floppy disk device 16 are connected to the I / O interface section 14.

Further, the host CPU 11 can access the emulation control unit 4, the memory 5, the break detection circuit 6, the program counter generation circuit PC, the trace memory 7 and the emulation memory 8 via the system bus 12 and the like. Has become.

In such an emulator 1, the MP
U2 executes the user program on the user system or the emulation memory 8 when executing the emulation.

The emulation memory 8 is accessed by constantly monitoring the address bus of the emulation bus 3. That is, when the emulation memory allocation address is reached during monitoring of the address bus, the operation of the user interface unit 9 is stopped and the chip select signal or the write enable signal of the emulation memory 8 is output. There is. The detection of the write-prohibited and access-prohibited areas is similarly performed by monitoring the address bus.

The program counter generation circuit PC has an instruction execution status signal from the above MPU 2, for example, MPU 2
Is a circuit for generating a program counter value at any time based on the state of the bus signal at the time of prefetching output and the state of the operation signal inside the emulator main body,
The break detection circuit 6 and the trace memory 7 are electrically connected through the program counter bus 17.

The value of the program counter generated here is specified as one of the trace acquisition conditions, and traced in a state of being related to the data such as the instruction stored in the trace memory 7 according to the trace acquisition conditions. It is stored in the memory 7.

That is, in the present embodiment, only the data such as the actually executed instruction can be stored in the trace memory 7 by setting the program counter value meaning the actual execution as the trace acquisition condition. It is possible. Therefore, in the trace of the emulator 1, the execution result of the instruction can be accurately acquired.

Further, in the present embodiment, the program counter value is stored in the trace memory 7 in a state of being associated with the data such as the instruction stored in the trace memory 7, so that it is obtained in the trace memory 7, for example. Even when the data such as the instruction to be specified is specified in the address range, that is, when the data such as the instruction is partially extracted, the last data execution state at the break of each data aggregate in the trace memory 7 is determined. The position of the indicated signal can be accurately known by referring to the program counter value corresponding to the data.

Next, the trace memory 7 will be described in detail with reference to FIG.

The trace memory 7 is a trace memory unit 7
a, a trace condition setting register 7b, an input address selection multiplexer 7c, and a condition match comparison circuit 7d.
And a trace memory access control circuit 7e.

The trace memory section 7a is a storage section for storing data such as instructions. Trace memory unit 7a
A is an address terminal, CS is a chip selector terminal, WE
Is a write enable terminal, Din is an input terminal, and Dout is an output terminal.

The emulation bus 3 is electrically connected to the input terminal Din. The system bus 12 is electrically connected to the output terminal Dout. An access control circuit 7e is electrically connected to the address terminal A, the chip selector terminal CS and the write enable terminal WE.

The condition setting register 7b includes a host CPU.
The trace mode value and the trace target address value are set in accordance with the signal transmitted from 11 through the system bus 12. As the condition setting, condition settings other than the address such as the interrupt request terminal state can be set, but the description is omitted here for simplification of description.

There are a bus trace and a program counter trace in the trace mode.
The output of the input address selecting multiplexer 7e is switched.

That is, when the bus trace is designated, the address bus 18 on the emulation bus 3 is selected, and when the program counter trace is designated, the program counter bus 17 is selected. The meaning of the set address is also switched between the access address and the program counter.

The condition setting register 7b is also electrically connected to the input address selecting multiplexer 7c.
The program counter generation circuit PC is electrically connected to the input of the input address selection multiplexer 7c through the program counter bus 17 described above. The other input of the input address selection multiplexer 7c is electrically connected to the emulation bus 3 through the address bus 18.

Further, the output of the condition setting register 7b and the output of the input address selecting multiplexer 7c are electrically connected to the input of the condition coincidence comparing circuit 7d.
That is, the condition coincidence comparison circuit 7d, the program counter value generated by the program counter generation circuit PC,
The value set in the condition setting register 7b is compared.

The output of the condition matching comparison circuit 7d is electrically connected to the input of the access control circuit 7e. The access control circuit 7e controls an address signal, a chip selector signal, and a write enable signal when writing to the trace memory unit 7a during emulation and when the host CPU 11 reads the contents in the trace memory unit 7a. Is. The access control circuit 7e is also electrically connected to the system bus 12 and is controlled according to a signal transmitted from the system bus 12 side.

Next, FIG. 3 shows the program counter generation timing during instruction execution of the MPU 2, FIG. 4 shows the contents of the instruction at that time, and FIG. 5 shows the contents stored in the trace memory 7 at that time.

Now, the MPU 2 follows the addresses 101, 102, 11 on the memory 5 according to the execution order of the arrows in FIG.
It is assumed that the instructions 0, 111, and 112 are executed in order.
That is, the instructions at the addresses 103 to 109 are not executed. The address 10 of the instruction that is not executed
3, 3 and 104 are hatched to make the drawings easier to see.

In the bus cycle at this time, as shown in FIG. 3, addresses 101, 102, 103, 10
In addition to prefetching 4, 110 and 112 instructions,
Data cycle, refresh cycle and DMA cycle are executed.

In this embodiment, since the program counter value is designated as one of the trace acquisition conditions, as shown in FIG. 102, 110, 11
Only the instructions of 1 and 112 are stored, and the instructions of the addresses 103 to 109 that are not actually executed are not stored. That is, the execution result can be accurately acquired.

Although not shown in FIG. 5, the instruction addresses 101, 102, 110 and 11 are stored in the trace memory 7.
The program counter value is also stored in the state where 1 and 112 are related. Therefore, although not described with reference to FIGS. 3 to 5, even when an instruction is partially extracted by designating a predetermined address range, the last portion in the aggregate of each instruction in the trace memory 7 is extracted. The position of the signal indicating the instruction execution state can be accurately known by referring to the program counter value corresponding to the instruction.

As described above, according to this embodiment, the following effects can be obtained.

(1). By setting the program counter value, which means the actual execution, as the trace acquisition condition, it becomes possible to store only the data such as the actually executed instruction in the trace memory 7. Therefore, in the trace of the emulator 1, the execution result of the instruction can be accurately acquired. Therefore, disassemble display can be performed and the debug efficiency of the emulator 1 can be improved.

(2). By storing the program counter value in the trace memory 7 in a state of being associated with the data such as the instruction stored in the trace memory 7, for example, the instruction acquired in the trace memory 7 Even when the data is specified in the address range, that is, when the data such as the instruction is partially extracted, the trace memory 7
It is possible to accurately know the position of the signal indicating the last data execution state at the break of each data aggregate in the above by referring to the program counter value corresponding to the data. Therefore, disassemble display can be performed and the debug efficiency of the emulator 1 can be improved.

The invention made by the present inventor has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, the trace acquisition condition may be specified by combining the program counter value and another condition, for example, a predetermined data value used by the user. Further, a predetermined data value on the user side may be added to the trace information.

In the above description, the case where the invention made by the present inventor is mainly applied to the emulator of the microprocessor application device which is the background field of application has been described, but the present invention is not limited to this and can be variously applied. It is also possible to apply, for example, to an analyzer which analyzes other logic circuits.

[0055]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

According to the above-described present invention, by setting the program counter value, which means the actual execution, as the trace acquisition condition, only the actually executed data can be stored in the trace memory. It is possible to accurately acquire the execution result of the instruction in the trace of.

Also, for example, when data such as an instruction to be acquired in the trace memory is specified in an address range, that is, when data such as an instruction is extracted in a partial portion, a set of data in the trace memory is collected. The position of the signal indicating the last data execution state at the break can be accurately known by referring to the program counter value corresponding to the data.

Therefore, disassemble display can be performed, and the debugging efficiency of the emulator can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an emulator that is an embodiment of the present invention.

FIG. 2 is a block diagram showing in detail a trace memory in the emulator of FIG.

FIG. 3 is a timing chart of bus cycle timing and program counter generation timing during instruction execution of the emulator of this embodiment.

FIG. 4 is an explanatory diagram for explaining an instruction execution order of the emulator of this embodiment.

FIG. 5 is an explanatory diagram for explaining a storage state of instructions in a trace memory.

FIG. 6 is an explanatory diagram for explaining an instruction execution order of an emulator according to a conventional technique.

FIG. 7 is an explanatory diagram for explaining a storage state of instructions in a trace memory according to a conventional technique.

FIG. 8 is an explanatory diagram for explaining a storage state of instructions in a trace memory according to a conventional technique.

[Explanation of symbols]

 1 emulator 2 microprocessor 3 emulation bus 4 emulation control unit 5 memory 6 break detection circuit 7 trace memory 7a trace memory unit 7b trace condition setting register 7c input address selection multiplexer 7d condition match comparison circuit 7e trace memory access control circuit 8 emulation memory 9 User Interface Section 10 User Interface Socket 11 Host CPU 12 System Bus 13 System Memory 14 I / O Interface Section 15 CRT 16 Floppy Disk Unit 17 Program Counter Bus 18 Address Bus PC Program Counter Generation Circuit 30 Trace Memory

Claims (5)

[Claims] 1. A tracing method of an emulator, wherein an emulation target electronic device is pseudo-operated by a microprocessor provided in an emulator main body to debug the emulation target electronic device. Specifying the executed program counter value as one of the trace acquisition conditions and storing it in the trace memory in association with the data stored in the trace memory according to the trace acquisition condition. Characteristic emulator tracing method. 2. When the microprocessor operates,
2. The emulator tracing method according to claim 1, further comprising a prefetch step of previously acquiring data to be executed. 3. The emulator trace method according to claim 2, wherein the program counter value is generated based on a state of a bus signal output from the microprocessor at the time of prefetch and a state of an operation signal inside the emulator main body. And a step of comparing whether or not the program counter value matches the program counter value in the emulator, the tracing method of the emulator. 4. An emulator that emulates an electronic device to be emulated by a microprocessor provided in an emulator main body to debug the electronic device to be emulated, based on an instruction execution state of the microprocessor. To generate a program counter value, specify the value as one of trace acquisition conditions, and store the program counter value in the trace memory in a state associated with the data stored in the trace memory. An emulator having a circuit section. 5. The emulator according to claim 4, wherein the microprocessor has a prefetch function for previously acquiring data to be executed next.