JPH07211898A - Semiconductor device and its manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor device in which the strength of the gate oxide film in I/O sections is insured and its manufacturing method. CONSTITUTION:A semiconductor device includes p-type diffused source/drain regions 11, diffused region 9 of lower impurity concentration than the region 11, n-type diffused source/drain regions 12, and diffused regions 10 of lower impurity concentration than the region 12. A self-aligned silicide layer of TiSi2 is formed on part of the diffused region of lower impurity concentration or the diffused source/drain region. In this device, the strength of the gate oxide is insured even if an abnormal voltage is applied to the diffused source/drain region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low voltage operation, high reliability semiconductor device and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, the structure of a semiconductor device is shown in FIG.
Those shown in are generally used. That is, both the P-type diffusion layer 11 and the N-type diffusion layer 12 are salicide regions. In addition, as a manufacturing method thereof, a polysilicon gate 5 is provided on the semiconductor substrate 1 via a gate oxide film 7.
HTO sidewall 8 is formed, impurities are injected,
The P-type diffusion layer 11 and the N-type diffusion layer 12 are formed. Then depositing a Ti on the entire surface of the substrate, heat-treated in an N ₂ atmosphere (e.g. RT
A) is performed to form TiSi ₂ 13, and the source and drain diffusion layers are made salicide regions.

[0003]

However, in the above semiconductor device structure, when such a semiconductor device is used in the I / O section, a voltage higher than the operating voltage of the internal logic is I / O.
When applied to the source / drain diffusion layers of the O-part semiconductor device, there arises a problem that the gate oxide film resistance cannot be maintained.

In view of the above problems, the present invention provides a structure of a semiconductor device which can maintain the gate oxide film resistance of the I / O section semiconductor device,
And its manufacturing method.

[0005]

In order to solve the above problems, the structure of a semiconductor device according to the present invention has a diffusion layer having a lower concentration than the source / drain diffusion layer between the source / drain diffusion layer and the gate. And the low-concentration diffusion layer,
Unlike the source and drain diffusion layers, it is characterized in that it is a non-salicide region.

[0006]

The present invention has the above-described structure, so that even if a voltage higher than the operating voltage is applied to the source / drain diffusion layer, the voltage is reduced by the low-concentration diffusion layer existing between the source / drain diffusion layer and the gate. It can be offset to maintain the resistance of the gate oxide film.

[0007]

Embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to Embodiment 1 of the present invention. In FIG. 1A, the N well 2 (P, 5.0E12) is formed on the semiconductor substrate 1.
/ cm ^2, 80keV) and P-well ^{3 (B, 5.0E12 / cm 2} , 10keV) is formed, N-channel stopper ^{6 (B, 5.0E13 / cm 2} , 8keV)
After the implantation, a 500 nm silicon oxide film 4 is formed, 10 nm gate oxidation is performed, and a polysilicon gate 5 is provided at a desired position.

Then, in FIG. 1B, the source and drain
P-type low-concentration diffusion layer 9 as a diffusion layer having a lower concentration than
(B, 5.0E13 / cm², 5keV), N type low concentration diffusion layer 10 (P, 5.0
E13 / cm ², 20 keV) and 150 nm HTO is deposited on the entire surface.
And etch back the HTO sidewall 8 and
A gate oxide film 7 is formed.

Subsequently, in FIG. 1C, a P-type diffusion layer 11 (B, 5.0E15 / cm ² , 5 keV) and an N-type diffusion layer 12 are formed as source and drain diffusion layers through a photo process and an implantation process. (P,
5.0E15 / cm ² , 20keV) is formed.

Next, in FIG. 1D, the salicide process is started. 50 nm Ti except the low concentration diffusion layers 9 and 10
And heat treatment (600 ° C., 800 ° C.) in an N ₂ atmosphere to form TiSi ₂ 13 at the positions of the diffusion layers 11 and 12, and a salicide region is provided only in the source and drain diffusion layers.
With this semiconductor device structure, even if a voltage higher than the operating voltage is applied to the source and drain diffusion layers, the low-concentration diffusion layers 9 and 10 are provided, so that the voltage is offset and the resistance of the gate oxide film 7 is improved. Is secured.

Furthermore, in the above salicide process, when Ti is deposited on the source / drain diffusion layers 11 and 12 except for a part thereof, only a part of the source / drain diffusion layer becomes a salicide region (FIG. 1e). ). With this semiconductor device structure, even if a voltage higher than the operating voltage is applied to the source and drain diffusion layers, not only the gate oxide film but also the LO
It is also possible to secure the resistance at the edge of the COS oxide film.

In the salicide process shown in FIG.
The case where Ti is deposited on the portion excluding the low-concentration diffusion layer 10 is shown. In this case, the P-type low concentration diffusion layer 9 and the P-type diffusion layer 1
1 is the salicide area. However, TiSi ₂ 13 and P
The type diffusion layer 11 has an ohmic characteristic, and the TiSi ₂ 13 and the P type low concentration diffusion layer 9 have a non-ohmic characteristic. Therefore, even if a voltage equal to or higher than the operating voltage is applied to the P-type source / drain diffusion layer 11, the TiSi ₂ 13 remains in the P-type low-concentration diffusion layer 9
Since it is non-ohmic at the above, the voltage is offset and the resistance of the gate oxide film can be secured.

(Embodiment 2) FIG. 4 is a sectional view showing the steps in manufacturing a semiconductor device according to Embodiment 2 of the present invention. In FIG. 3 (a), the N well 2 (P, 5.0E12 / cm) is formed on the semiconductor substrate 1.
² , 80keV) and P well 3 (B, 5.0E12 / cm ² , 10keV) are formed, and N channel stopper 6 is injected (B, 5.0E13 / cm ² , 8keV).
V) After that, a 500 nm silicon oxide film 4 is formed, 10 nm gate oxidation is performed, and a polysilicon gate 5 whose periphery is covered with an oxide film 5 is formed.
Is provided at a desired position. Then, a 20 nm silicon nitride film 14 is deposited on the entire surface, a pattern of the photoresist 15 is formed, and then the silicon nitride film in the low concentration diffusion layer injection portion is removed by a dry etching method.

In FIG. 3B, the P type low concentration diffusion layer 9 (B, 5.0
E13 / cm ² , 5keV), N type low concentration diffusion layer 10 (P, 5.0E13 / c
After the formation of m ² (20 keV), the photoresist 15 is removed and further oxidized to form a silicon oxide film 16 on the 40 nm low-concentration diffusion layer. Then, in FIG. 3C, the silicon nitride film 14
Is removed.

Next, in FIG. 3D, when the silicon oxide film in the portion where the source and drain diffusion layers are implanted is removed, the silicon oxide film 16 on the low concentration diffusion layer is also etched at the same time, but about 10 nm remains. . Then, the photoresist 15
Pattern is formed, and source and drain diffusion layers are implanted. When the photoresist 15 is removed after the implantation, the P-type diffusion layer 11 (B, 5.0E15 / cm ² , 5 keV) and the N-type diffusion layer 12 (P, 5.0
E15 / cm ² , 20 keV) is formed, and the silicon oxide film 16 exists only on the low concentration diffusion layer (FIG. 3e). In this state, in FIG. 3F, 50 nm Ti is deposited on the entire surface, and RTA is performed at 625 ° C. for 60 seconds in an N ₂ atmosphere. After removing titanium nitride, RTA is performed at 800 ° C. for 60 seconds in a N ₂ atmosphere, and then TiSi ₂
13 is formed. Since the low concentration diffusion layer is covered with the silicon oxide film, TiSi ₂ is not formed. Thus, the salicide region can be formed only in the gate 5, the source / drain diffusion layers 11 and 12.

(Embodiment 3) FIG. 3 is a sectional view showing the steps in manufacturing a semiconductor device according to Embodiment 3 of the present invention. In FIG. 3 (a), the N well 2 (P, 5.0E12 / cm) is formed on the semiconductor substrate 1.
² , 80keV) and P well 3 (B, 5.0E12 / cm ² , 10keV) are formed, and N channel stopper 6 is injected (B, 5.0E13 / cm ² , 8keV).
V) After that, a 500 nm silicon oxide film 4 is formed, 10 nm gate oxidation is performed, and a polysilicon gate 5 is provided at a desired position.
The gate oxide film 7 is also formed. Then, a 20 nm silicon nitride film 14 is deposited directly on the semiconductor substrate, a pattern of the photoresist 15 is formed, and then the silicon nitride film in the low concentration diffusion layer injection portion is removed by a dry etching method.

In FIG. 3B, the P type low concentration diffusion layer 9 (B, 5.0
E13 / cm ² , 5keV), N type low concentration diffusion layer 10 (P, 5.0E13 / c
After the formation of m ² (20 keV), the photoresist 15 is removed and further oxidized to form a silicon oxide film 16 on the 5 nm low-concentration diffusion layer.

Then, in FIG. 3C, the silicon nitride film 1 is formed.
4 is removed, the pattern of the photoresist 15 is formed,
Source and drain diffusion layers are implanted. Compared with the manufacturing method shown in the second embodiment, the step of etching the silicon oxide film before implanting the source / drain diffusion layer can be omitted, and the film thickness of the silicon oxide film 16 on the low concentration diffusion layer can be controlled to be thin.

In FIG. 3 (d), the photoresist 15 after implantation is injected.
, The P-type diffusion layer 11 (B, 5.0E15 / cm ² , 5ke
V) and the N type diffusion layer 12 (P, 5.0E15 / cm ² , 20 keV) are formed, and the silicon oxide film 16 exists only on the low concentration diffusion layer.

In this state, as shown in FIG. 3 (e), 50 nm Ti is deposited on the entire surface, and RTA is performed at 625 ° C. for 60 seconds in an N ₂ atmosphere.
After removing the titanium nitride, continue in an N ₂ atmosphere at 800 ° C for 6
RTA for 0 sec is performed to form TiSi ₂ 13. Since the low concentration diffusion layer is covered with the silicon oxide film, TiSi ₂ is not formed. In this way, the salicide region can be formed only in the source and drain diffusion layers.

[0022]

As described above, according to the present invention, the source,
By forming a low-concentration diffusion layer between the drain diffusion layer and the gate, it is possible to secure the resistance of the gate oxide film even if the source or drain diffusion layer is applied with an operating voltage or higher. The practical effect is great.

[Brief description of drawings]

FIG. 1 is a sectional view of a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 3 is a sectional view of a semiconductor device manufacturing process in a second embodiment of the present invention.

FIG. 4 is a sectional view of a semiconductor device manufacturing process in a third embodiment of the present invention.

FIG. 5 is a sectional view of a semiconductor device according to a conventional method.

[Explanation of symbols]

1 semiconductor substrate 2 N well 3 P well 4 silicon oxide film 5 polysilicon gate 6 N channel stopper 7 gate oxide film 8 HTO sidewall 9 P type low concentration diffusion layer 10 N type low concentration diffusion layer 11 P type diffusion layer 12 N Type diffusion layer 13 TiSi ₂ 14 Silicon nitride film 15 Photoresist 16 Low concentration diffusion layer Silicon oxide film

Claims (11)

[Claims] 1. A diffusion layer having a lower concentration than that of a source / drain diffusion layer and two types of diffusion layers of a source / drain diffusion layer are formed, and a portion of the low concentration diffusion layer or the source / drain diffusion layer is salicided. A semiconductor device having a region. 2. A non-salicide region on the low-concentration diffusion layer,
The semiconductor device according to claim 1, wherein a salicide region is formed on the source and drain diffusion layers. 3. The semiconductor device according to claim 2, further comprising a low-concentration diffusion layer having a width of 0.5 μm or more from the side surface edge of the gate to both or one direction of the source and drain diffusion layers. 4. A diffusion layer of a lower concentration than the source / drain diffusion layer and two types of diffusion layers of a source / drain diffusion layer, wherein the low concentration diffusion layer is a non-salicide region, a source,
2. The semiconductor device according to claim 1, wherein only a part of the drain diffusion layer is used as a salicide region. 5. The salicide region existing only on a part of the source / drain diffusion layer is formed at a position separated by 0.5 μm or more from the side edge of the gate and the edge of the LOCOS oxide film. Semiconductor device. 6. A salicide region is formed over the entire area of two types of P-type diffusion layers, that is, a P-type diffusion layer having a lower concentration than the P-type source and drain diffusion layers and a P-type source and drain diffusion layer. 2. The semiconductor device according to 2 or 4. 7. A step of providing a gate on a semiconductor substrate via a silicon oxide film, a step of forming a pattern of a silicon nitride film on the silicon oxide film, and a diffusion layer having a lower concentration than the source / drain diffusion layers. And a step of oxidizing the silicon oxide film to thicken just above the low-concentration diffusion layer, removing the silicon nitride film, and then removing the entire surface of the silicon oxide film except the low-concentration diffusion layer. A method for manufacturing a semiconductor device, comprising: a step of forming a source / drain diffusion layer; and a step of salicidation to use only the source / drain diffusion layer as a salicide region. 8. A step of providing a gate on a semiconductor substrate with a silicon oxide film interposed therebetween, a step of removing a silicon oxide film other than the gate oxide film directly below the gate, and a step of depositing a silicon nitride film on the entire surface of the semiconductor substrate. A step of forming a pattern of a silicon nitride film on the semiconductor substrate, a step of forming a diffusion layer having a lower concentration than the source / drain diffusion layer, and an oxidation process to form a silicon oxide film only on the low concentration diffusion layer. A method of manufacturing a semiconductor device comprising: a step of forming a silicon nitride film, a step of forming a source / drain diffusion layer, and a step of salicidation to use only the source / drain diffusion layer as a salicide region. 9. A diffusion layer having a concentration lower than that of the source / drain diffusion layer and two types of diffusion layers of a source / drain diffusion layer. I /
A semiconductor device characterized by being used for an O part. 10. A diffusion layer having a lower concentration than the source and drain diffusion layers and two types of diffusion layers, a source and a drain diffusion layer, and a non-salicide region, a source and a drain diffusion layer on the low concentration diffusion layer. A semiconductor device characterized in that a semiconductor element having only a portion as a salicide region is used for an I / O portion. 11. A semiconductor device having a salicide region on two types of P-type diffusion layers, that is, a P-type diffusion layer having a lower concentration than the P-type source and drain diffusion layers and a P-type source and drain diffusion layer. 9. The method according to claim 9 or 10, characterized in that
The semiconductor device described.