JPH07202097A - Semiconductor device and lead frame - Google Patents
Semiconductor device and lead frameInfo
- Publication number
- JPH07202097A JPH07202097A JP6001046A JP104694A JPH07202097A JP H07202097 A JPH07202097 A JP H07202097A JP 6001046 A JP6001046 A JP 6001046A JP 104694 A JP104694 A JP 104694A JP H07202097 A JPH07202097 A JP H07202097A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- pellet
- semiconductor
- semiconductor device
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4905—Shape
- H01L2224/49051—Connectors having different shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置のリード構成
技術、特に、大電流形にあって抵抗成分による電圧降下
を低減するために用いて効果のある技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device lead configuration technique, and more particularly to a technique effective in reducing a voltage drop due to a resistance component in a large current type.
【０００２】[0002]
【従来の技術】整流用などのダイオードやパワートラン
ジスタのように大電流を扱う半導体装置においては、特
開昭６１−１０２７４５号公報に示すように、３本のリ
ード電極を平行かつ一定間隔に配設し、その中央のリー
ド電極に放熱板を兼ねるペレット搭載部が一体加工され
ており、このペレット搭載部上に搭載されたペレット
（半導体素子）とリード電極間をボンディングワイヤで
接続し、ペレット周辺を樹脂材により封止する構造がと
られている。2. Description of the Related Art In a semiconductor device for handling a large current such as a diode or a power transistor for rectification, three lead electrodes are arranged in parallel and at regular intervals as shown in JP-A-61-2102745. The pellet mounting part that also functions as a heat sink is integrally processed on the center lead electrode. The pellet (semiconductor element) mounted on this pellet mounting part and the lead electrode are connected by a bonding wire, and the pellet periphery The structure is such that the resin is sealed with a resin material.
【０００３】ところで、本発明者は、大電流を扱う半導
体装置におけるボンディングワイヤの抵抗成分による電
圧降下について検討した。By the way, the present inventor has examined the voltage drop due to the resistance component of the bonding wire in the semiconductor device handling a large current.
【０００４】以下は、本発明者によって検討された技術
であり、その概要は次の通りである。図６は本発明者に
よって考え出された半導体装置の樹脂封止前の状態を示
す平面図であり、ここでは半導体装置としてダイオード
を例にしている。The following is a technique studied by the present inventor, and the outline thereof is as follows. FIG. 6 is a plan view showing a state of a semiconductor device before resin encapsulation conceived by the present inventor, and a diode is taken as an example of the semiconductor device here.
【０００５】図６に示すように、リードフレームを形成
するリード電極１１，１２，１３は平行かつ同一平面上
に配設され、両側のリード電極１１，１３の上端（ペレ
ット側）はＬ字形に曲げ加工が施されている。また、リ
ード電極１１の上端には板状のペレット搭載部１４が一
体加工により設けられており、このペレット搭載部１４
の中央部（主面）にロウ材１６を介してペレット１５が
搭載されている。As shown in FIG. 6, the lead electrodes 11, 12 and 13 forming the lead frame are arranged in parallel and on the same plane, and the upper ends (pellet side) of the lead electrodes 11 and 13 on both sides are L-shaped. Bending is applied. A plate-shaped pellet mounting portion 14 is integrally formed on the upper end of the lead electrode 11.
The pellets 15 are mounted on the central portion (main surface) of the through the brazing material 16.
【０００６】ペレット１５の両面には電極が形成されて
おり、下面電極にはロウ材１６を介してペレット搭載部
１４に接続され、表面電極とリード電極１１，１３の各
々との間にはボンディングワイヤ１７ａ，１７ｂが接続
されている。ボンディングワイヤ１７ａ，１７ｂは超音
波ボンダを用いる場合、アルミ線が用いられる。このア
ルミ線は、通過電流に応じた直径のものを選定する。Electrodes are formed on both sides of the pellet 15, and the lower surface electrode is connected to the pellet mounting portion 14 via a brazing material 16 and the surface electrode and the lead electrodes 11 and 13 are bonded to each other. The wires 17a and 17b are connected. Aluminum wires are used for the bonding wires 17a and 17b when an ultrasonic bonder is used. This aluminum wire should have a diameter corresponding to the passing current.
【０００７】図６の半導体装置の等価回路を示したのが
図７であり、１個のダイオード１８から３本のリード線
が引き出される構造になっている。このダイオード１８
が図６のペレット１５に相当し、このペレット１５の表
面がアノード、下面がカソードになっている。したがっ
て、リード電極１２はアノードに接続されている。ま
た、リード電極１１，１３はボンディングワイヤ１７
ａ，１７ｂを介して共通接続されており、ペレット１５
のカソードに接続されている。この接続が終了した後に
樹脂材によるパッケージングが行われる。FIG. 7 shows an equivalent circuit of the semiconductor device shown in FIG. 6, which has a structure in which three lead wires are led out from one diode 18. This diode 18
Corresponds to the pellet 15 in FIG. 6, the surface of the pellet 15 is the anode, and the lower surface is the cathode. Therefore, the lead electrode 12 is connected to the anode. In addition, the lead electrodes 11 and 13 are the bonding wires 17
a and 17b are commonly connected, and the pellet 15
Connected to the cathode. After this connection is completed, packaging with a resin material is performed.
【０００８】近年、半導体ペレットの特性改善が進展
し、素子の低損失化が図られてきた結果、半導体装置の
組立構成要素の内、特にボンディングワイヤによる抵抗
成分による電力損失（電圧降下）が問題になっている。
この抵抗成分を低減するためにはワイヤ径を大きくすれ
ばよいが、市販品を充当しようとすると、５００μｍ径
が最大であり、６０Ａ程度を通電するには１本では足り
ない。そこで、前記特開昭６１−１０２７４５号公報に
示すように、１つの経路に複数本のボンディングワイヤ
を用いて配線し、電流経路の拡大を図ることが考えられ
る。In recent years, as the characteristics of semiconductor pellets have been improved and the loss of the element has been reduced, the power loss (voltage drop) due to the resistance component due to the bonding wire is a problem among the assembly components of the semiconductor device. It has become.
In order to reduce this resistance component, the wire diameter may be increased, but when a commercially available product is used, the diameter of 500 μm is the maximum, and one wire is not enough to energize about 60 A. Therefore, as disclosed in Japanese Patent Laid-Open No. 61-102745, it is conceivable to use a plurality of bonding wires for one path to expand the current path.
【０００９】[0009]
【発明が解決しようとする課題】ところが、前記の如く
ボンディングワイヤにアルミ線を用いた半導体装置で
は、そのワイヤ接続のための装置にワイヤボンディンダ
を用いている。しかし、そのボンディングに方向性があ
り、治具でリードの上下を押圧しながら行う必要がある
ほか、取り出し用リード端子部分の形状の問題から、ワ
イヤボンディングに使用できる面積が制約されるため、
複数本（特に、３本以上）のボンディングワイヤを並列
接続することができず、抵抗成分を低減できないという
問題のあることを本発明者は見い出した。However, in the semiconductor device using the aluminum wire for the bonding wire as described above, the wire bonder is used for the device for connecting the wire. However, the bonding is directional, and it is necessary to perform it while pressing the top and bottom of the lead with a jig.Because of the problem of the shape of the lead terminal for extraction, the area that can be used for wire bonding is restricted.
The present inventor has found that there is a problem in that a plurality of (in particular, three or more) bonding wires cannot be connected in parallel and the resistance component cannot be reduced.
【００１０】そこで、本発明の目的は、大電流を扱う半
導体素子に接続されるボンディングワイヤ部での抵抗成
分を低減することのできる技術を提供することにある。Therefore, an object of the present invention is to provide a technique capable of reducing a resistance component in a bonding wire portion connected to a semiconductor element handling a large current.
【００１１】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面から明らかにな
るであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【００１２】[0012]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下の通りである。すなわち、平行に配設された複数の
リード電極を有するリードフレームの主面に少なくとも
１つの半導体ペレットが搭載され、この半導体ペレット
の表面電極とペレット搭載部に連結されないリード電極
との間をボンディングワイヤで接続する半導体装置であ
って、前記表面電極にボンディングワイヤで接続される
リード電極の少なくとも１本を前記ペレット搭載部に平
行するように延伸させ、このリード電極に対し最短距離
で複数のボンディングワイヤを並列接続するようにして
いる。Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows. That is, at least one semiconductor pellet is mounted on the main surface of a lead frame having a plurality of lead electrodes arranged in parallel, and a bonding wire is provided between the surface electrode of this semiconductor pellet and the lead electrode not connected to the pellet mounting portion. In the semiconductor device, the lead electrodes connected to the surface electrodes by bonding wires are extended so as to be parallel to the pellet mounting portion, and a plurality of bonding wires are arranged at the shortest distance to the lead electrodes. Are connected in parallel.
【００１３】[0013]
【作用】上記した手段によれば、半導体ペレットの表面
電極にボンディングワイヤで接続されるリード電極の少
なくとも１本を前記表面電極に対し最短距離でワイヤ接
続が可能な位置まで延伸させた構成により、半導体ペレ
ットの表面電極にワイヤボンダを用いてボンディングワ
イヤを接続する場合のスペース的な制約及び方向性の問
題が無くなり、複数本のボンディングワイヤを半導体ペ
レットの表面電極に並列接続できるようになる。これに
より、直列抵抗成分が低減され、電力損失の低減が可能
になる。According to the above means, at least one of the lead electrodes connected to the surface electrode of the semiconductor pellet by the bonding wire is extended to the position where the wire connection can be made to the surface electrode at the shortest distance. When connecting the bonding wires to the surface electrodes of the semiconductor pellets by using a wire bonder, there are no problems in space and directionality, and a plurality of bonding wires can be connected in parallel to the surface electrodes of the semiconductor pellets. Thereby, the series resistance component is reduced, and the power loss can be reduced.
【００１４】[0014]
【実施例】以下、本発明の実施例について、図面を参照
しながら説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１５】図１は本発明における半導体装置の一実施
例を示す平面図である。また、図２は本発明におけるリ
ードフレームを示す平面図である。なお、以下において
は、図７に示したように、半導体ペレットが１個のダイ
オードから成る場合を例に説明している。FIG. 1 is a plan view showing an embodiment of a semiconductor device according to the present invention. 2 is a plan view showing the lead frame of the present invention. In the following description, the case where the semiconductor pellet is composed of one diode as shown in FIG. 7 is described as an example.
【００１６】図２に示すように、リードフレームは平行
かつ等間隔に配設された３本のリード電極１，２，３
と、リード電極２の上端に一体に形成されたペレット搭
載部４を主体に構成されている。なお、組み立ての完了
まで各部が散逸しないように、各リード端子間には全体
の形状姿態及び位置を保持するためのダムバー６ａが設
けられている。As shown in FIG. 2, the lead frame has three lead electrodes 1, 2, 3 arranged in parallel and at equal intervals.
And the pellet mounting portion 4 integrally formed on the upper end of the lead electrode 2 is configured. A dam bar 6a is provided between the lead terminals to maintain the overall shape and position of the lead terminals so that the respective parts do not scatter until the assembly is completed.
【００１７】また、実際には、半導体装置の複数個分の
リードフレームを同時に作成するために枠部６ｂが設け
られており、個々のフレームを相互に連結している。パ
ッケージングが終了した後、ダムバー６ａ及び枠部６ｂ
は、リード電極及びペレット搭載部４から切り離され
る。Further, in practice, a frame portion 6b is provided for simultaneously forming a plurality of lead frames of the semiconductor device, and the individual frames are connected to each other. After the packaging is completed, the dam bar 6a and the frame portion 6b
Are separated from the lead electrode and the pellet mounting portion 4.
【００１８】リード電極２の上端にはペレット搭載部よ
り延長されており、板状で且つ凸形の輪郭形状を成した
ペレット搭載部４（その表面には、酸化防止のためのニ
ッケルメッキ等が施されている）が一体加工により設け
られている。リード電極１，３は同一長さであるが、共
にリード電極２の全長より長く設定され、ペレット搭載
部４上に搭載された半導体ペレット５の横側にまで延伸
している。このため、ペレット搭載部４のリード側の幅
をリード電極１，２の内側の距離相当に狭めている。な
お、ペレット搭載部４の半導体ペレット５の搭載部に隣
接させて取付穴４ａが設けられているが、これは仕様に
よっては設けない場合もある。The upper end of the lead electrode 2 is extended from the pellet mounting portion, and has a plate-like and convex contour shape. The pellet mounting portion 4 has a nickel plating or the like for preventing oxidation. It is provided) by integral processing. Although the lead electrodes 1 and 3 have the same length, both are set to be longer than the entire length of the lead electrode 2 and extend to the lateral side of the semiconductor pellet 5 mounted on the pellet mounting portion 4. Therefore, the width of the pellet mounting portion 4 on the lead side is narrowed to a distance corresponding to the inside of the lead electrodes 1 and 2. Although the mounting hole 4a is provided adjacent to the mounting portion of the semiconductor pellet 5 of the pellet mounting portion 4, this may not be provided depending on the specifications.
【００１９】半導体ペレット５は、はんだを用いたロウ
材７によってペレット搭載部４の所定の位置に実装さ
れ、機械的な固定と同時にリード電極２に対する電気的
な接続が行われる。半導体ペレット５の表面には、その
全面に１枚の電極が形成されており、この電極とリード
電極１，２の各々との間にアルミ線によるボンディング
ワイヤ８，９の各々が超音波ワイヤボンダを用いて接続
される。The semiconductor pellet 5 is mounted at a predetermined position of the pellet mounting portion 4 by a brazing material 7 using solder, and is mechanically fixed and simultaneously electrically connected to the lead electrode 2. One electrode is formed on the entire surface of the semiconductor pellet 5, and each of the bonding wires 8 and 9 made of aluminum wire forms an ultrasonic wire bonder between the electrode and each of the lead electrodes 1 and 2. Be connected using.
【００２０】この場合、ボンディングワイヤ８，９の各
々は、リード電極側の接続部の面積が広いため、ワイヤ
ボンダにとって作業上の制約が無くなり、複数本のリー
ド電極の並列接続が可能になる。この結果、図１に示す
ように、リード電極１，２の各々に対し、複数本（本実
施例では３本）を１グループにした並列接続が可能にな
り、ワイヤ径を太くした場合と同等の効果が得られるよ
うになる。また、リード電極１，２を半導体ペレット５
の側方部にまで延ばしたことにより、ボンディングワイ
ヤ８，９を最短長さにすることができ、抵抗分を最小に
することができる。In this case, since each of the bonding wires 8 and 9 has a large area of a connecting portion on the side of the lead electrode, the wire bonder does not have a restriction on work and a plurality of lead electrodes can be connected in parallel. As a result, as shown in FIG. 1, a plurality of (three in this embodiment) one group can be connected in parallel to each of the lead electrodes 1 and 2, which is equivalent to a case where the wire diameter is increased. The effect of can be obtained. Further, the lead electrodes 1 and 2 are connected to the semiconductor pellet 5
Since the bonding wires 8 and 9 are extended to the lateral portions, the bonding wires 8 and 9 can have the shortest length, and the resistance component can be minimized.
【００２１】すなわち、導体の電気抵抗Ｒは、Ｒ＝ρ×
ｌ／Ｓ（但し、ρは抵抗率、ｌは長さ、Ｓは断面積）で
表されるため、１つの経路のボンディングワイヤをｎ本
にすることにより、抵抗値を１／ｎに低減することがで
きる。この結果、大電流を取り扱っても電力損失を小さ
くすることが可能になる。That is, the electric resistance R of the conductor is R = ρ ×
Since it is represented by 1 / S (where ρ is the resistivity, l is the length, and S is the cross-sectional area), the resistance value is reduced to 1 / n by using n bonding wires in one path. be able to. As a result, it is possible to reduce power loss even when handling a large current.
【００２２】例えば、図６の構成において、６０Ａの電
流を取り扱うダイオードをペレット搭載部１４にロウ材
１６で固着し、これとリード電極１１または１３の間
を、抵抗率が2.６×１０-6Ω・ｃｍで、直径0.５ｍｍの
アルミ線を用いて６ｍｍの長さで接続した場合、このボ
ンディングワイヤにおける抵抗成分は約0.８ｍΩとな
り、６０Ａ通電時には４８ｍＶの電圧降下がボンディン
グワイヤに生じ、これが半導体素子の電気的特性を劣化
させる原因になる。For example, in the structure shown in FIG. 6, a diode for handling a current of 60 A is fixed to the pellet mounting portion 14 with a brazing material 16, and the resistance between this and the lead electrode 11 or 13 is 2.6 × 10 −. When connecting with a length of 6 mm using an aluminum wire with a diameter of 6 Ω · cm and a diameter of 0.5 mm, the resistance component in this bonding wire is approximately 0.8 mΩ, and a voltage drop of 48 mV occurs in the bonding wire when a current of 60 A is applied. This causes deterioration of the electrical characteristics of the semiconductor element.
【００２３】これに対し、本発明によれば、ワイヤボン
ダに制約を及ぼすことなく複数本のボンディングワイヤ
を並列に張ることができるため、ボンディングワイヤの
抵抗成分を低減することができる。例えば、本発明者ら
が扱う製品においては、ボンディングワイヤにおける電
圧降下を0.４Ｖに目標をおいているが、図６の構成にお
ける４８ｍＶに対し、本発明によれば、0.３８〜0.３９
Ｖに低減でき、目標を達成することができた。On the other hand, according to the present invention, since a plurality of bonding wires can be stretched in parallel without restricting the wire bonder, the resistance component of the bonding wires can be reduced. For example, in the products handled by the present inventors, the voltage drop in the bonding wire is set to 0.4 V, but according to the present invention, the voltage drop in the bonding wire is 0.38 to 0.3 V. 39
It was possible to reduce it to V and achieve the target.
【００２４】以上説明したように、本発明の半導体装置
によれば、１つの経路に複数本を並列にしたワイヤボン
ディングが可能になり、ボンディングワイヤに起因する
直列抵抗成分を低減することができ、半導体素子自体の
低損失化に対応した半導体装置を提供することができ
る。As described above, according to the semiconductor device of the present invention, it is possible to wire-bond a plurality of wires in parallel in one path, and it is possible to reduce the series resistance component due to the bonding wires. It is possible to provide a semiconductor device corresponding to the reduction in loss of the semiconductor element itself.
【００２５】なお、上記実施例においては、ダイオード
が１個の場合について説明したが、図３に示すように、
ダイオードが２個の場合についても本発明を適用するこ
とができる。この場合、ダイオード１０ａ，１０ｂは両
波整流回路に対応すべく、ダイオード１０ａ，１０ｂが
対向接続され、その中点がリード電極２に接続される。
また、ダイオード１０ａのアノードはリード電極１に接
続され、ダイオード１０ｂのアノードはリード電極３に
接続される。In the above embodiment, the case where there is one diode has been described, but as shown in FIG.
The present invention can be applied to the case where there are two diodes. In this case, the diodes 10a and 10b are connected oppositely to each other so that the diodes 10a and 10b correspond to the double-wave rectification circuit, and the middle point thereof is connected to the lead electrode 2.
The anode of the diode 10 a is connected to the lead electrode 1, and the anode of the diode 10 b is connected to the lead electrode 3.
【００２６】また、構造的には、半導体ペレット５の上
面（表面）の電極が図１の中心部から左右に２分割さ
れ、各々にボンディングワイヤ８，９が接続される。な
お、ダイオード１０ａ，１０ｂはアノード同士を対向接
続する構成であってもよい。Structurally, the electrode on the upper surface (front surface) of the semiconductor pellet 5 is divided into two parts from the center of FIG. 1 to the left and right, and the bonding wires 8 and 9 are connected to each. The diodes 10a and 10b may have a structure in which the anodes of the diodes are opposed to each other.
【００２７】以上、本発明者によってなされた発明を実
施例に基づき具体的に説明したが、本発明は前記実施例
に限定されるものではなく、その要旨を逸脱しない範囲
で種々変更可能であることは言うまでもない。Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.
【００２８】例えば、上記実施例では、アルミ線による
ボンディングワイヤを用いたが、これに限定されるもの
ではなく、銅線等を用いてもよい。For example, in the above embodiment, the bonding wire made of aluminum wire was used, but it is not limited to this, and copper wire or the like may be used.
【００２９】また、半導体ペレットを固着する際の向き
等は、上記実施例に限定されるものではなく、任意にす
ることができる。The direction and the like for fixing the semiconductor pellets are not limited to those in the above embodiment, but may be arbitrary.
【００３０】更に、ペレット搭載部４の面積に制約が無
い場合には、図４に示すように、各リード電極をＳ字形
にしても前記実施例と同一の効果を得ることができる。
この場合、ボンディングワイヤ８，９が図１の実施例に
比べて長くなるので、抵抗分が大きくなる場合には本数
を増やすことになる。Further, when the area of the pellet mounting portion 4 is not limited, the same effect as that of the above embodiment can be obtained even if each lead electrode is S-shaped as shown in FIG.
In this case, since the bonding wires 8 and 9 are longer than those in the embodiment of FIG. 1, the number of wires is increased when the resistance is large.
【００３１】また、上記実施例においては、リード電極
１，３の両方を延伸させたが、半導体ペレット５が１つ
の電極面を有する場合には、図５に示すように、いずれ
か一方のリード電極のみを延伸させ、他方は図６のまま
であってもよい。この構成は、トランジスタの様に電流
の少ないベース電極を有したものに適している。例え
ば、リード電極１３をベース、リード電極１をエミッ
タ、リード電極１２をコレクタに各々用いることで、電
流容量の問題が解決する。Further, in the above embodiment, both the lead electrodes 1 and 3 were extended, but when the semiconductor pellet 5 has one electrode surface, as shown in FIG. Only the electrodes may be stretched and the other may remain as in FIG. This structure is suitable for a transistor having a base electrode with a small current, such as a transistor. For example, by using the lead electrode 13 as a base, the lead electrode 1 as an emitter, and the lead electrode 12 as a collector, the problem of current capacity is solved.
【００３２】また、以上の説明では、主として本発明者
によってなされた発明をその利用分野であるダイオード
に適用した場合について説明したが、これに限定される
ものではなく、例えば、ＬＳＩ等、他の半導体装置に対
しても本発明を適用することができる。Further, in the above description, the case where the invention made by the present inventor is mainly applied to the diode, which is the field of use of the invention, has been described, but the invention is not limited to this and, for example, an LSI, etc. The present invention can be applied to a semiconductor device.
【００３３】[0033]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば以下
のとおりである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
【００３４】すなわち、平行に配設された複数のリード
電極を有するリードフレームの主面に少なくとも１つの
半導体ペレットが搭載され、この半導体ペレットの表面
電極とペレット搭載部に連結されないリード電極との間
をボンディングワイヤで接続する半導体装置であって、
前記表面電極にボンディングワイヤで接続されるリード
電極の少なくとも１本を前記ペレット搭載部に平行する
ように延伸させ、このリード電極に対し最短距離で複数
のボンディングワイヤを並列接続するようにしたので、
直列抵抗成分が低減され、電力損失の低減が可能にな
る。That is, at least one semiconductor pellet is mounted on the main surface of a lead frame having a plurality of lead electrodes arranged in parallel, and the surface electrode of this semiconductor pellet and the lead electrode not connected to the pellet mounting portion are mounted. A semiconductor device in which bonding wires are connected to each other,
At least one of the lead electrodes connected to the surface electrode by a bonding wire is extended in parallel with the pellet mounting portion, and a plurality of bonding wires are connected in parallel to the lead electrode at the shortest distance.
The series resistance component is reduced, and the power loss can be reduced.
【００３５】低損失である半導体素子自身の特性を、犠
牲にすることのないパッケージングが実現でき、半導体
素子全体の損失低減が可能となる。The packaging can be realized without sacrificing the characteristics of the semiconductor element itself, which has a low loss, and the loss of the entire semiconductor element can be reduced.
【図１】本発明における半導体装置の一実施例を示す平
面図である。FIG. 1 is a plan view showing an embodiment of a semiconductor device according to the present invention.
【図２】本発明におけるリードフレームの一実施例を示
す平面図である。FIG. 2 is a plan view showing an embodiment of a lead frame according to the present invention.
【図３】本発明の他の回路例を示す等価回路図である。FIG. 3 is an equivalent circuit diagram showing another circuit example of the present invention.
【図４】図１の実施例の変形例を示す平面図である。FIG. 4 is a plan view showing a modified example of the embodiment of FIG.
【図５】図１の実施例の他の変形例を示す平面図であ
る。FIG. 5 is a plan view showing another modified example of the embodiment of FIG.
【図６】本発明者によって考え出された半導体装置の樹
脂封止前の状態を示す平面図である。FIG. 6 is a plan view showing a state before resin encapsulation of a semiconductor device devised by the present inventor.
【図７】図６の半導体装置の等価回路を示す回路図であ
る。FIG. 7 is a circuit diagram showing an equivalent circuit of the semiconductor device of FIG.
１ リード電極 ２ リード電極 ３ リード電極 ４ ペレット搭載部 ４ａ 取付穴 ５ 半導体ペレット ６ａ ダムバー ６ｂ 枠部 ７ ロウ材 ８ ボンディングワイヤ ９ ボンディングワイヤ １０ａ ダイオード １０ｂ ダイオード １１ リード電極 １２ リード電極 １３ リード電極 １４ ペレット搭載部 １５ ペレット １６ ロウ材 １７ａ ボンディングワイヤ １７ｂ ボンディングワイヤ １８ ダイオード 1 lead electrode 2 lead electrode 3 lead electrode 4 pellet mounting part 4a mounting hole 5 semiconductor pellet 6a dam bar 6b frame part 7 brazing material 8 bonding wire 9 bonding wire 10a diode 10b diode 11 lead electrode 12 lead electrode 13 lead electrode 14 pellet mounting part 15 Pellet 16 Brazing material 17a Bonding wire 17b Bonding wire 18 Diode
Claims (5)
するリードフレームの主面に少なくとも１つの半導体ペ
レットが搭載され、この半導体ペレットの表面電極とペ
レット搭載部に連結されないリード電極との間をボンデ
ィングワイヤで接続する半導体装置であって、前記表面
電極にボンディングワイヤで接続されるリード電極の少
なくとも１本を前記ペレット搭載部に平行するように延
伸させ、このリード電極に対し最短距離で複数のボンデ
ィングワイヤを並列接続することを特徴とする半導体装
置。1. At least one semiconductor pellet is mounted on a main surface of a lead frame having a plurality of lead electrodes arranged in parallel, and between a surface electrode of the semiconductor pellet and a lead electrode not connected to the pellet mounting portion. Is a semiconductor device in which at least one of the lead electrodes connected to the surface electrode by a bonding wire is extended in parallel with the pellet mounting portion, and a plurality of lead electrodes are connected at the shortest distance to the lead electrode. A semiconductor device in which the bonding wires are connected in parallel.
の本数は、規格電流値における電圧降下が期待値内にな
るような数であることを特徴とする請求項１記載の半導
体装置。2. The semiconductor device according to claim 1, wherein the number of bonding wires connected in parallel is such that a voltage drop at a standard current value is within an expected value.
あることを特徴とする請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein the bonding wire is an aluminum wire.
ることを特徴とする請求項１記載の半導体装置。4. The semiconductor device according to claim 1, wherein the semiconductor pellet is a diode.
えると共に、その１本に半導体ペレットを搭載するため
のペレット搭載部が連結されたリードフレームであっ
て、前記ペレット搭載部が連結されたリード電極以外の
リード電極の少なくとも１本が、前記ペレット搭載部に
平行するように延伸していることを特徴とするリードフ
レーム。5. A lead frame comprising a plurality of lead electrodes arranged in parallel, and a pellet mounting portion for mounting a semiconductor pellet on one of the lead electrodes, wherein the pellet mounting portion is connected. A lead frame, wherein at least one of the lead electrodes other than the lead electrode extends parallel to the pellet mounting portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6001046A JPH07202097A (en) | 1994-01-11 | 1994-01-11 | Semiconductor device and lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6001046A JPH07202097A (en) | 1994-01-11 | 1994-01-11 | Semiconductor device and lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07202097A true JPH07202097A (en) | 1995-08-04 |
Family
ID=11490617
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6001046A Pending JPH07202097A (en) | 1994-01-11 | 1994-01-11 | Semiconductor device and lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07202097A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010212682A (en) * | 2009-02-26 | 2010-09-24 | Avago Technologies Ecbu Ip (Singapore) Pte Ltd | Minimization of electromagnetic interference in coil transducer |
| US8063494B2 (en) | 2004-07-21 | 2011-11-22 | Rohm Co., Ltd. | Semiconductor device and power supply unit utilizing the same |
| US9105391B2 (en) | 2006-08-28 | 2015-08-11 | Avago Technologies General Ip (Singapore) Pte. Ltd. | High voltage hold-off coil transducer |
-
1994
- 1994-01-11 JP JP6001046A patent/JPH07202097A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8063494B2 (en) | 2004-07-21 | 2011-11-22 | Rohm Co., Ltd. | Semiconductor device and power supply unit utilizing the same |
| US8704357B2 (en) | 2004-07-21 | 2014-04-22 | Rohm Co., Ltd. | Semiconductor device and power supply unit utilizing the same |
| US8872577B2 (en) | 2004-07-21 | 2014-10-28 | Rohm Co., Ltd. | Semiconductor device and power supply unit utilizing the same |
| US9391038B2 (en) | 2004-07-21 | 2016-07-12 | Rohm Co., Ltd. | Semiconductor device and power supply unit utilizing the same |
| US9812964B2 (en) | 2004-07-21 | 2017-11-07 | Rohm Co., Ltd. | Semiconductor device and power supply unit utilizing the same |
| US9105391B2 (en) | 2006-08-28 | 2015-08-11 | Avago Technologies General Ip (Singapore) Pte. Ltd. | High voltage hold-off coil transducer |
| JP2010212682A (en) * | 2009-02-26 | 2010-09-24 | Avago Technologies Ecbu Ip (Singapore) Pte Ltd | Minimization of electromagnetic interference in coil transducer |
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