JPH07200665A - Simulation device for logic circuit and compiling method for function describing language of logic circuit - Google Patents

Abstract

PURPOSE:To provide a simulation device for logic circuits that can decrease the number of tables where the arithmetic results are previously stored and also can reduce the size of each table. CONSTITUTION:This simulation device is provided with a hardware description language(HDL) describing/analyzing part 11 which analyzes the HDL describing the function of a logic circuit to be simulated and extracts the operator string of each sentence, a merge deciding part 13 which decides the propriety of sharing of each operator string based on the operator string obtained at the part 11 for each sentence, an arithmetic code generating part 14 which generates an arithmetic code that is capable of simulation based on the deciding result of the part 13, and a table producing part 16 which produces a table that performs an arithmetic operation based on the arithmetic code generated at the part 14 and stores this arithmetic result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit simulation apparatus for verifying the operation of a logic circuit, and a language compiling method for describing the function of the logic circuit to be simulated.

[0002]

2. Description of the Related Art In recent years, as the scale of logic circuits has increased, verification work has required a lot of time, and the problem of increasing the design period of logic circuits has arisen. In order to solve this problem, a simulation method based on table lookup has been proposed in the past as a method of improving the execution speed of the simulator.

This method is intended to reduce the calculation execution time because most of the execution time of the simulator is occupied by the calculation execution time. In this method, the calculation result is stored in a table in advance, and the calculation execution time is shortened by referring to this table when the calculation is executed. However, the simulation method by referring to this table has the following problems.

The first problem is that since a table of evaluation values of expressions must be prepared for all combinations of input values, a table size of 2 ⁿ is obtained for an expression with n inputs, and The size is enormous. The second problem is that since a table is created for each sentence, the number of tables is the same as the number of sentences, and it is necessary to create a large number of tables.

To address the second problem, there has been proposed a method of sharing the table in order to reduce the number of tables when different statements have exactly the same operation. However, in this method, since the sharing of the table can be applied only to exactly the same operation, there is a problem that the sharing effect is generally small and the number of tables cannot be reduced so much.

On the other hand, a method using a truth table has been conventionally used as one of the methods for speeding up the processing of the logic simulation apparatus. The truth table is a data structure in which the pattern of the output signal is associated with the pattern of the input signal, and is used to obtain the operation of each circuit constituent element in the circuit to be verified. That is, when the pattern of the input signal is given, one storage area in the truth table is uniquely determined correspondingly. The content of the storage area is an output signal pattern corresponding to the given input signal pattern.

Since the pattern of the output signal for each pattern of the input signal is calculated in advance and stored in the truth table, it is not necessary to recalculate the pattern of the signal output by each circuit component during simulation, All you have to do is search the truth table using the signal pattern as a key.
Therefore, the pattern of the output signal can be obtained at high speed,
It is possible to reduce the time required for simulation.

Next, a conventional truth table of, for example, a 4-bit ALU will be described.

FIG. 26 (a) is a diagram showing a circuit symbol of a 4-bit ALU, and FIG. 26 (b) is a diagram showing an example of its functional specifications.

In FIG. 26, the operation is executed on both or one of the values of the input signals A and B, and the result is output signal Y.
Output to. The input signals A and B are 4-bit data system signals and represent integer values from -8 to +7 by using 2's complement notation. Y is a 5-bit data system signal and represents an integer value from -16 to +15 by using 2's complement notation. The type of operation to be executed is selected by the 4-bit control system input signal OP.

FIG. 27 is a diagram showing a truth table and its element reference method in the conventional logic simulation apparatus.

In FIG. 27, the value of the concatenated bit string 271 created from the values of the input signals OP, A and B is converted into the truth table 2
The value of the output signal Y is obtained by regarding it as a subscript of 72.

For example, OP = 1000 (decimal number 8: operation Y = A + B is selected), A = 0101 (decimal number 5), B =
When the value of Y when 0110 (decimal number 6), that is, the sum 11 of 5 and 6, is obtained, the concatenated bit string 10 of OP, A, and B
The value represented by 0001010110, that is, the decimal number 213
The value of Y is 01011, referring to the truth table with 4 as a subscript
Get (decimal 11).

Assuming that one unit of storage area is required for each element of the truth table, 4-bit A in the conventional method is used.
The size of the storage area required to store the truth table in the example of LU is 40 because the length of the concatenated bit string is 12 bits.
It becomes 96 (= 2 to the 12th power) unit.

However, with this method, the pattern of the output signal must be able to be determined for all possible patterns of the input signal, so that as the number of input signals increases, the possible pattern becomes exponential. However, there is a problem that the storage area required for storing the truth table becomes huge.

Therefore, in the conventional logic simulation apparatus, a speed-up method using a truth table is used for a simple circuit component having a small number of input signals such as a gate unit or a basic cell in which several gates are combined. Although applicable, this technique could not be applied to a relatively large scale circuit component having many input signals.

On the other hand, in the description of the hardware description language (HDL) describing the function of the logic circuit to be simulated, another description can be referred to in one description, and therefore the description of the program is performed in the order of reference. Must have been analyzed.

In the compiler for compiling HDL up to now, even if the description is corrected and recompilation is executed,
I'm just checking to see if the description that is directly referenced has been compiled. Since I am only checking the compile time of the file that is directly referenced, when recompiling a file that has a reference relationship, it is now necessary to check whether the file that is directly referenced by that file has been compiled. , You have to recompile if necessary.

That is, basically, the reference relationship of the description (which is also the analysis order) must be managed by the user of the compiler. Moreover, even if the description was partially modified, it was wasteful because all files belonging to the reference sequence were recompiled.

[0020]

As described above,
In a conventional logic circuit simulation apparatus that refers to a table, the table must be prepared for all combinations of input values, and the table size becomes huge. Since a table is created for each statement, it was necessary to create many tables.

Further, in the conventional logic circuit simulation apparatus using the truth table, the storage area required for storing the truth table becomes enormous for a large-scale circuit constituent element in the circuit to be verified. However, there is a problem that the speed-up method using the truth table cannot be applied.

Further, in the HDL description, the reference relation of the description must be managed by the user of the compiler, and even when the description is partially modified, all files belonging to the reference sequence are recompiled. It took a long time to compile.

Therefore, the present invention has been made in view of the above, and an object of the present invention is to provide a simulation apparatus of a logic circuit in which the number and size of tables in which operation results are stored in advance are reduced. It is in.

Another object of the present invention is to simulate a logic circuit by reducing the storage area for the truth table and enabling logic simulation using the truth table even for complex circuit components having a relatively large scale. To provide a device.

Another object of the present invention is to provide a method of compiling a functional description language for a logic circuit, which can shorten the compilation time by omitting unnecessary recompilation.

[0026]

In order to achieve the above object, the first feature of the present invention is to provide a hardware description language for describing the function of a logic circuit to be simulated in a simulation device for simulating a logic circuit. HDL description analysis means for analyzing (HDL) to extract an operator sequence which is a sequence of operators for each sentence, and each operator sequence from the operator sequence for each sentence obtained by the HDL description analysis means A merge determination unit that determines whether or not sharing is possible, an operation code generation unit that generates a simulation-executable operation code based on a merge determination result by the merge determination unit, and an operation generated by the operation code generation unit. It comprises a table creating means for executing an operation from a code and creating a table storing the operation result.

A second feature of the present invention is that, in a simulation device for simulating a logic circuit, an input signal pattern which is a functional specification of each type of circuit constituent element having a logic operation function with a circuit description as an input. Circuit description analysis means for generating the definition information of the pattern of the output signal, and the functional specifications of the circuit components,
Hierarchized truth table creating means for grouping the input signal groups, creating a partial truth table for each set, and creating a hierarchical truth table configured by hierarchically connecting them, Using the hierarchical truth table, for each of the circuit components,
And a simulation means for determining an output signal pattern from the pattern of the input signal.

A third feature of the present invention is a compiling method for compiling a hardware description language (HDL) which describes the function of a logic circuit to be simulated.
A step of storing reference relationship information between HDL sources in a file, and whether or not the reference source file needs to be recompiled based on the reference relationship information at the time of compiling the HDL source. And a step of performing recompilation in advance when the reference source needs to be recompiled.

A fourth aspect of the present invention is the same as the first aspect of the present invention, in which the operator sequence retaining means retains the operator sequence for each sentence obtained by the HDL description analyzing means, and the merge determining means. Table holding means for holding the merge determination result obtained by the above and the table created by the table creating means.

The fifth feature of the present invention is that, in the second feature of the present invention, a mask pattern for invalidating a part of the pattern of the input signal by the hierarchical truth table creating means is added to the hierarchical truth table. Means for doing so.

[0031]

In the above construction, the first feature of the present invention is that H
The DL description analysis means obtains the operator sequence for each sentence by analyzing the HDL, holds the obtained operator sequence in the operator sequence holding means, and the merge determination means is obtained by the HDL description analysis means. Whether or not the operator sequences can be shared is determined by comparing the operator sequences for the expressions of each statement, and the obtained determination result is held in the holding unit, and the operation code generation unit is based on the merge determination result. It is possible to convert the arithmetic expression of each statement so that the evaluation value of the expression is invariable and the operator sequence is the same for the set of statements that can be shared, and execute the operation from the converted arithmetic expression. Generate opcode,
The table creating means executes the operation based on the operation code generated by the operation code generating means and stores the operation result in the table.

In the above-mentioned configuration, the second characteristic of the present invention is that the circuit description analyzing means generates a functional specification for each kind of circuit constituent element having a logical operation function with the circuit description as an input, and analyzes the circuit description. In addition to this, the means also generates connection information such as information indicating the connection between the circuit components necessary for executing the simulation, and the hierarchical truth table creation means functions the circuit components generated by the circuit description analysis means. Inputting the specifications, the input signal groups are divided into groups, a partial truth table is created for each group, and a truth table is created by hierarchically connecting them, and the simulation means and the circuit description analysis means generate it. A logical simulation is executed with the connection information, the hierarchical truth table created by the hierarchical truth table creating means, and the test pattern as inputs.

In the above structure, the third feature of the present invention is to store the reference relation information between VDL sources in a file, and check whether or not the reference destination source file is changed based on the reference relation information at the time of compiling the HDL source. Then, it is determined whether or not the reference source is required to be recompiled. If the reference source is required to be recompiled, the recompilation is performed in advance.

In the above configuration, the fourth feature of the present invention is that when HDL modification is performed, the operator sequence obtained by the HDL description analyzing means and the pre-modification stored in the operator sequence holding means The corrected sentence is found by comparing the operator sequences, and the merge determination means checks whether or not the operator sequence of the corrected sentence can be shared between the operator sequences. The obtained merge determination result is compared with the merge determination result before correction held by the table holding means, and the operation code generation means generates the operation code only for the updated result, and the table creation means I'm trying to rebuild the table.

In the above structure, the fifth feature of the present invention is that the hierarchical truth table creating means creates a hierarchical truth table including a mask pattern for invalidating a part of the pattern of the input signal, and performs simulation. The means inputs the connection information and the test pattern other than the hierarchical truth table to which the mask pattern is added and executes the logic simulation.

[0036]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the structure of a logic circuit simulation apparatus according to an embodiment of the present invention.

In FIG. 1, a logic circuit simulation device 1 includes an HDL description analysis unit 11 and an operator sequence holding unit 1.
2, merge determination unit 13, operation code generation unit 14, operation execution unit 15, table creation unit 16, table holding unit 17,
The simulation executing unit 18 is provided.

When the simulation apparatus 1 reads the HDL description 2, the HDL description analysis unit 11 obtains an operator sequence for each sentence. After this, the information on the operator sequence of each sentence is held in the operator sequence holding unit 15. When the description is modified, the retained operator sequence is used to find the modified sentence by comparing the modified operator sequences. Next, in the merge determination unit 13, the HDL description analysis unit 11
Whether or not the operator sequence can be shared is checked using the operator sequence obtained in step 1, and the optimum merge is selected from the sharable statements. The result obtained here is held in the table holding unit 17.

Next, the operation code generator 14 generates an operation code for executing the operation for each sentence. When generating the operation code, the mergeable statements are converted so as to be the same operation without changing the logic.

Next, the operation executing section 15 executes the operation according to the operation code obtained previously. The table creation unit 16 creates a table based on the calculation result. The table thus obtained is held in the table holding unit 17.

Next, the processing flow of each processing unit will be described by taking the HDL description of FIG. 7 as an example.

First, when the HDL description 71 shown in FIG. 7 is read, the HDL description analysis unit 11 performs the following processing.

In this processing flow, as shown in FIG. 2, first, at step 21, it is checked whether or not the description is modified. This is determined by whether or not the operator sequence before correction remains in the operator sequence holding unit 12. If the operator string remains, the currently read HDL description is regarded as modified. If the description has not been modified, step 24 is immediately executed to find the operator sequence for each sentence. The operator sequence of the description 71 in FIG. 7 is shown at 81 in FIG.

On the other hand, if the description is modified in step 21, the modified sentence is found in step 22. This compares the uncorrected operator sequence remaining in the operator sequence holding unit 12 with the newly obtained operator sequence,
If the operator sequence is different, it can be seen that the correction has been made.

When the corrected sentence is found in this way, the operator sequence of the corrected sentence is obtained in step 23. The operator sequence of the modified example 72 of the HDL of FIG. 7 is shown at 82 in FIG.

Next, in the table merge determination section 13,
First, as shown in FIG. 3, in step 31, a logical expression is developed using De Morgan's theorem or the like. For example, the arithmetic expression 71 in FIG. 7 is w = (not a1) and (n
ot a2) and a3.

Next, in step 32, it is checked whether there are two or more sentences. If the condition of step 32 is satisfied, the operator sequences in the same description are compared in step 33, and the one having the longest operator sequence is selected. Next, in step 34, the longest operator sequence is compared with other operator sequences to see if all of the operator sequences are included in the longest operator sequence. If included, the two operations can be merged. The algorithm of step 34 is shown in FIG.

Next, step 34 will be described with reference to FIG.

When the longest operator sequence is selected in step 33, one sentence other than the longest operator sequence is selected in step 41. Then, in step 42,
One operator included in the operator sequence of the sentence selected in step 41 is extracted. Next, in step 43, it is checked whether or not the previously fetched operator matches the operator in the longest operator sequence. If the condition of step 43 is satisfied, the routine proceeds to step 44, where it is checked whether all the operators in the operator sequence of the selected sentence have been taken out. If the condition of step 44 is satisfied, the sentence selected in step 41 is the desired sentence that can be merged with the sentence having the longest operator sequence.

On the other hand, if the condition of step 43 is not satisfied, the sentence selected in step 41 is not the sentence obtained in step 34. That is, it cannot be merged with the statement having the longest operator sequence. If the condition is not satisfied in step 44, the process returns to step 42 and another operator different from the operator selected previously is taken out. Therefore,
Steps 42-44 will be repeated for each operator sequence.

Thus, after reaching steps 45 and 46, step 47 is executed, and steps 41 to 45, 46 are executed for all statements other than the statement having the longest operator sequence.
After executing, you will get one merge combination. Thus, when step 34 is completed, the process proceeds to step 35, and the difference between the operator sequence of the sentence obtained in step 34 and the longest operator sequence is obtained. Next, in step 36, the one having the longest operator sequence is removed, and the sentence in which not is not included in the difference is removed, and the process returns to step 32 again.

The reason why only the difference does not include "not" is to prevent the sentence including "not" from being merged. Steps 32-36 are repeated until all merge combinations have been determined.

When the above is applied to the example of the operator sequence 81 of FIG. 8, the combination of sentence numbers to be merged is (1, 2),
It is calculated as (3, 4). Further, if the example of 82 in FIG. 8 is applied to the above, one combination of (2, 3, 4) is obtained. In this way, if all merge combinations can be obtained, the process proceeds to step 37 through step 32.

On the other hand, if the condition is not satisfied in step 32, it means that the combination of all merges is obtained, or that there is only one sentence from the beginning. If the condition of step 32 is not satisfied, the process proceeds to step 37. If a combination of merges is required in step 37, the process proceeds to step 38, and step 3
If the condition 7 is not satisfied, the process immediately proceeds to the process of the operation code generator 14. In step 38, the merge rule is applied, and the optimal merge combination is obtained from the mergeable sentence combinations obtained in steps 31 to 36.

For example, although the sentences (5) and (6) in the HDL description example of FIG. 9 can be merged, this merge is performed by the sentence (5).
When the calculation of is frequently performed, the calculation efficiency of the simulation may be reduced. Therefore, such a merge is overridden by the merge rule of step 38.

FIG. 10 shows a merge rule for avoiding the merge as shown in FIG. 9, for example. The merging rule of FIG. 10 is to prevent merging if the longest operator sequence is 6 or more. By applying this merge rule, merging of sentences (5) and (6) is prohibited.

Next, in step 39, a merge information table is created, and the merge set obtained in step 23 is registered in the merge information table.

FIG. 11 shows an example of the merge information table.

Reference numeral 111 in FIG. 11 is a merge information table created in the description 71 before correction. The statement number of the merge information table is the number of the statement assigned to the statement being described. This sentence number is assigned by the HDL analysis unit 11 in FIG. The merged sentence number column contains the number of the sentence to be merged. Further, [-] in the merge statement number column indicates that there is no statement to be merged. Therefore, for example, from the merge information table 111, the sentence (1)
It can be seen that the calculation table of 1 is merged with the calculation table of sentence (2), and the sentence (3) is merged with the sentence (4).

The corrected merge information table 112
In Fig. 7, it can be seen that the corrected sentence (2) 'and the sentence (3) are merged into the sentence (4). The update check flag is used to determine that the HDL description is modified and the merge statement number is different from that before modification.
This update check flag is set to 1 when the merge statement number before correction and the merge determination result after correction are different,
If they are the same, 0 is set.

For example, since no update is performed in the merge information table 111 before description correction, the update check flag is 0 for all statements. However, in the merge information table 112 after description correction, the update check flag is set to 1 because the merge result before correction and the merge result after correction are different for the statements (1) and (2) ′. The merge information table created as described above is held in the table holding unit 17.

When the processing of the merge determination section 12 is completed in this way, the operation code generation section 14 generates an operation code for executing the operation. When generating the opcode, if the operator string that has the longest combination of sentences to be merged is converted to the opcode as it is, the merged statement, that is, the operator sequence is For the non-longest one, for example, the sentences (1) and (3) in FIG. 7 are converted into the same operation code as the longest operation as in the example of FIG.
This algorithm is shown in FIG.

In FIG. 12, first, in step 121, the longest operator sequence is extracted from the merge combinations. Next, in step 122, the difference with the operator sequence of the sentence to be converted is obtained, and in step 123, if the and operator appears in the difference operators, and is (and 1)
, Or when the or operator appears, replace or with (or
0), and the operation code of the operation replaced with the operation code of the sentence to be converted is added.

After the operation code is generated, the operation execution unit 1
5 executes the calculation, and the calculation result is the table creation unit 16
A table storing the calculation results is created in. The processing flow of the table creation unit differs depending on whether the HDL description is modified or not, as shown in FIG.

First, in step 51 of FIG. 5, it is checked whether or not the description has been modified. If no modification has been made, all tables are created in step 53. On the other hand, if the correction has been made, the table is regenerated only in the case where the correction is made as in step 52, that is, the update check flag of the merge information table is set to 1. The calculation table created in this way is held in the table holding unit 17.

The creation of the table is shown in FIG.

In FIG. 6, after the table area is secured in step 61, the calculation result obtained by the calculation executing section 15 is taken out in step 62, and the calculation result is written in the table in step 63. When the table creation is completed in this way, the simulation executing unit 18 executes the simulation. If the simulation result does not match the expected value, the designer corrects the HDL description, then the simulation apparatus reads the HDL description again, and the above processing is repeated.

As described above, according to the above-described embodiment, it is possible to refer to the same table as other operations by converting the operations that are not completely the same into theoretical equivalent operations. This makes it possible to share a table among a plurality of operations, reduce the number of tables, and reduce the storage capacity during simulation.

Next, an embodiment of the invention described in claim 2 of the present invention will be described.

FIG. 14 is a block diagram of a logic circuit simulation apparatus according to an embodiment of the present invention.

In FIG. 14, a logic circuit simulation device 141 includes a circuit description analysis means 142, a hierarchical truth table creation means 143, and a simulation means 14.
4, and a circuit description 145, a functional specification 146, a hierarchical truth table 147, library information 148, connection information 149, a test pattern 150, and a simulation result 151 are provided outside thereof.

The circuit description analyzing means 142 is used for the circuit description 14.
5 and the library information 148 are input, and the functional specification 146 is generated for each type of circuit component having a logical operation function. If the function of the circuit component is predefined on the system side, the library information 148 is searched to obtain the function specification 146 thereof. If user defined,
The functional specification 146 is obtained from the circuit description 145. In addition to this, the circuit description analysis means 142 also generates connection information 149 such as information indicating the connection between the circuit components necessary for executing the simulation.

The layered truth table creation means 143 receives the functional specification 146 generated by the circuit description analysis means 142 as an input, groups the input signal groups, creates a partial truth table for each group, and creates them. A hierarchical truth table 147 is created by hierarchically connecting.

The simulation means 144 has the connection information 149 generated by the circuit description analysis means 142 and the hierarchical truth value table 147 created by the hierarchical truth value table creation means 143.
And the test pattern 150 is input, the logic simulation is executed, and the simulation result 151 is output.

FIG. 15 is a flow chart showing the processing contents of the hierarchized truth table creating means 143 in the case of creating a hierarchized truth table having a two-stage structure.

In FIG. 15, in step 15-1,
All the input signals are classified into two sets, a control system input signal and a data system input signal. Since the control system input signal determines how the data system input signal is handled, the control system input signal is the “upper signal” and the data system input signal is the “lower signal”.
And Next, in step 15-2, one table capable of storing elements corresponding to all patterns of higher-order signal values is prepared. This is referred to as the "upper table." At this point, all the elements of the "upper table" are undefined. Next, step 15
In -3, if the contents of all the elements of the "upper table" are defined, the process ends. If there are undefined elements, go to step 15-4. Next, in step 15-4,
Select one upper-level signal pattern P1 in which the corresponding element of the "upper table" is undefined. Next, in step 15-5, one table capable of storing elements corresponding to all the patterns of the lower signals is prepared. This is the "lower table". Next, in step 15-6, the pattern P1 of the higher-order signal is generated.
The pattern of the output signal for each pattern P2 of the lower-order signals when is fixed is stored and stored in the lower-order table.

Next, in step 15-7, step 1
If the "subordinate table" created in 5-5 and 15-6 is the same as the "other subordinate table" created previously, step 15-
Move to 9. Next, in step 15-8, "upper table"
Information such as a pointer pointing to the "lower table" is stored in the element corresponding to P1 of No., and the process returns to step 15-3. next,
At step 15-9, the "lower table" is discarded. Next, in step 15-10, information indicating "another lower table" found in step 15-7 is stored in the element corresponding to P1 of the "upper table", and the process returns to step 15-3. The "lower table" having the same content as "another lower table" is once created in steps 15-5 and 15-6 and then destroyed in step 15-9. It may be determined and steps 15-5 to 15-9 may be omitted.

Although FIG. 15 illustrates a hierarchical truth table having a two-level structure, a hierarchical truth table having three or more levels can be created. Generally, when creating a hierarchical truth table having an n-stage structure, input signals are classified into n sets according to their strength. However, the term "strength" here means that S1 is stronger than S2 if another input signal S2 is treated according to the value of a certain input signal S1. After classifying the input signals into n sets, the above procedure may be applied recursively.

FIG. 16 shows the simulation means 144,
It is a figure showing an example of detailed composition.

The simulation means 144 is composed of a simulation clock 1441, an event management means 1442, a signal value storage section 1443, a re-evaluation target determination means 1444, an evaluation means 1445, and a result output means 1446, and a test pattern 150 and a circuit. Description analysis means 14
The connection result 149 generated by No. 2 and the hierarchical truth value table 147 generated by the hierarchical truth value table creating means 143 are input, and the simulation result 151 is output.

The simulation clock 1441 indicates "current time" in simulation.

The event management means 1442 manages an event group. An event is change information of a signal value.

FIG. 17 is a diagram showing an example of the structure of an event.

Each event 170 includes signal identification information 17
It is composed of three pieces of information of 1, a new value 172, and a scheduled change time 173. The event group is registered in the event management means 1442 by the evaluation means 1445, and based on the contents of the simulation clock 1441, the event management means 1
It is taken out from 442. Furthermore, the event management means 14
42 updates the value of the signal in the verification target circuit stored in the signal value storage unit 1443 based on the extracted event group.

The signal value storage unit 1443 stores the value of the signal in the circuit to be verified.

The re-evaluation object determining means 1444 determines the evaluation means 144 from the list of signals whose values have changed and the connection information 149.
Find circuit components that need to be re-evaluated according to 5. For a circuit component, if the pattern of its input signal changes, that is, the value of even one of the input signals changes,
The means 14 for evaluating the pattern of the output signal of the circuit component
45 need to be re-evaluated.

The evaluating means 1445 obtains a new pattern of the output signal from the hierarchical truth table 147 and the pattern of the input signal for a certain circuit component.

The result output means 1446 outputs the time change of the value of the signal of the circuit to be verified to the display device, the external storage medium or the like.

FIG. 18 is a flow chart showing the processing contents of the simulation means 144 shown in FIG.

In FIG. 18, first, step 18-1.
Then, the internal state of the simulation means is initialized. At this time, the event group corresponding to the test pattern 150 is registered in the event management means 1442. Next, in step 18-2, if no event remains in the event management means 1442, the process ends. Next, in step 18-3, the earliest scheduled change time 173 is searched for from the event group registered in the event management means 1443, and the simulation clock 144 until that time.
Advance 1. Next, in step 18-4, all event groups whose scheduled change time 173 is equal to the contents of the simulation clock 1441 are fetched from the event management means 1442, and the value of the signal stored in the signal value storage unit 1443 is updated based on them. To do. Next, in step 18-5, the circuit component (re-evaluation target) including the signal whose value has changed in the input signal based on the connection information 149 is found by the reevaluation target determining means 1444. Next, step 18-
In step 6, a new pattern of the output signal is obtained from the pattern of the input signal and the functional specification 146 of each circuit component found in step 18-5, registered as a new event in the event management means 1442, and the process returns to step 18-2. .

FIG. 19 is a diagram for explaining the processing contents of the evaluation means 1445.

FIG. 19A shows n input signals I1 and I.
2, ..., In and m output signals O1, O2, ...
., Om is a circuit component U. FIG. 19 (b)
Shows the process of obtaining the output signal pattern from the input signal pattern for the circuit component U. The higher-order signals of the input signals are represented as H1, H2, ..., Hp, and the lower-order signals are represented as L1, L2, ..., Lq (p + q =
n).

In FIG. 19B, step 19-1
Then, the value of the higher-order signal expressed in bits is concatenated to obtain one concatenated bit string 191. Next, Step 19-2
Now, reference is made to one element of the upper table 192, which is arrayed using the value represented by the concatenated bit string 191 as a subscript. Next, in step 19-3, the contents (pointers) of the elements referred to in step 19-2 are traced to find the lower table 193 corresponding to the upper signal pattern. Next, in step 19-3, the values of the lower-order signals expressed in bits are concatenated to obtain one concatenated bit string 194. Next, in step 19-5, one element of the lower table 193 is referred to by using the value represented by the concatenated bit string 194 as a subscript. The content is the pattern of the output signal corresponding to the pattern of the input signal.

According to the above embodiment, by implementing the functional specifications of the circuit components as a hierarchical truth table,
A part of the lower partial truth table can be shared by a plurality of elements of the upper partial truth table, and there is an effect of saving the storage area required for storing the truth table. Therefore, since the storage area for the truth table can be saved, there is an effect that the logic simulation using the truth table can be performed even for a relatively large circuit component.

Next, another embodiment of the invention according to claim 2 of the present invention will be described.

FIG. 20 is a block diagram of a logic circuit simulation apparatus according to another embodiment of the present invention.

In FIG. 20, a logic circuit simulation device 201 includes a circuit description analysis means 142, a hierarchical truth table creation means 203, and a simulation means 20.
4 and a circuit description 145, a functional specification 146, a hierarchy truth table 207, and library information 1
48, connection information 149, a test pattern 150, and a simulation result 151 are provided.

The operation of the circuit description analysis means 142 is the same as that of the above-mentioned embodiment, but the layered truth table creation means 203 is used.
Creates a hierarchical truth table 207 including a mask pattern for invalidating a part of the pattern of the input signal. And
The simulation means 204 uses the layered truth table 207.
A logical simulation is executed by using the connection information 149 and the test pattern 150 as input. Details of the procedure will be described using an example of a 4-bit ALU shown in FIG.

FIG. 21 is a diagram showing an embodiment of the hierarchical truth value table 147 in the simulation apparatus 141 for the logic circuit shown in FIG.

FIG. 21 shows one upper table 211 that uses the control system signal OP as a subscript and eleven lower tables 212 that use the concatenated bit strings of the data system signals A and B as subscripts. Therefore, it is expressed as 212 (1) to (11))
It is a truth table having a two-tiered hierarchical structure composed of and.

In FIG. 21, there is a lower table 212 for each type of calculation, and each element thereof is the value of the calculation result Y with respect to the value of the data system signals A and B. Each element of the upper table 211 indicates the lower table 212 corresponding to the operation selected by the value of the control system signal OP. OP value is 0000-00
In any case of 11 (decimal number 0 to 3), the operation selected is Y = 0. Therefore, the four elements of the upper table indicate the lower table 212 (1) corresponding to the operation Y = 0. Become. That is, the lower table 212 (1) is shared.

Similarly, the OP values 0100 and 0101
The lower table 212 (2) corresponding to the operation Y = A can be shared for (decimal numbers 4 and 5), and the operation Y = B for the OP values 0110 and 0111 (decimal numbers 6 and 7). Can share the lower table 212 (3) corresponding to. As a result, if not shared, 16 subordinate tables are required, and 11 sub tables are sufficient.

FIG. 22 is a hierarchical truth table 1 shown in FIG.
It is a figure showing the element reference method of 47.

Similarly to the above, the method for referring to the elements of the hierarchical truth table 147 will be described by taking the case of obtaining the sum 11 of 5 and 6 as an example.

First, one element of the upper table 101 is referred to by using the value 1000 of the control system signal OP (decimal number 8: represented by reference numeral 221 in the figure) as a subscript, and the operation Y =
Find the lower table 212 (4) corresponding to A + B. Next, the value represented by the concatenated bit string 0101110 (reference numeral 222 in the figure) of the value 0101 of the data system signal A and the value 0110 of the B, that is, the lower table 212 (corresponding to the operation Y = A + B using the decimal number 86 as a subscript). 4) Refer to one element. The content 01011 (decimal number 11) is the Y value to be obtained.

Assuming that one unit of storage area is required for each element of the upper table 211 and the lower table 212, the upper table 211 has an element for each possible value of the 4-bit signal OP. Is required, so 16 (= 2 to the 4th power)
A unit storage area is required. For one lower table 212, a concatenated bit string of signals A and B (length 8 bits)
Since an element is required for each possible value of, 256 (=
A storage area of 2 8) is required. The lower table is 1
Since there is one, for the example of the 4-bit ALU, the storage area required for storing the hierarchical truth table 147 in the device shown in FIG. 14 is 2832 (= 16 + 256 × 11) units. This is 69% of the size (4096 units) when the conventional technique shown in FIG. 27 is used, and the storage area of about 30% can be saved.

FIG. 23 is a diagram showing an embodiment of the hierarchical truth value table 207 in the logic circuit simulation apparatus 201 shown in FIG.

FIG. 23 shows one upper table 231 that uses the control system signal OP as a subscript and seven lower table 232 that uses the concatenated bit string of the data system signals A and B as a subscript. Therefore, it is a truth table having a two-tiered hierarchical structure composed of reference numerals 232 (1) to 232 (7).

In FIG. 23, there is a lower table 232 for each type of calculation, and each element thereof is the value of the calculation result Y with respect to the value of the data system signals A and B. Each element of the upper table 231 has two kinds of information, and one indicates the lower table 232 corresponding to the operation selected by the value of the control signal OP, as in the embodiment of FIG. Another piece of information is according to this embodiment, which is a mask pattern for performing a bitwise AND operation with the concatenated bit string of the data system signals A and B when referring to the lower table 232.

Regarding an operation that uses only one value of the data signals A and B, if the value of the signal that is not used is regarded as 0, there is a special case of an operation that uses both values of A and B. It is possible to see. For example, the calculation Y = -B is considered to be the case where A = 0 in the calculation Y = A-B. If this is utilized, instead of referring to the lower table corresponding to the operation Y = −B, the concatenated bit string of the values of A and B is subjected to bitwise AND operation with the mask pattern 00001111, and the operation Y = A−B The correct Y value can also be obtained by referring to the lower table 232 (2) corresponding to. Therefore, calculation Y =
The lower table corresponding to -B is unnecessary.

Similarly, the operation Y = 0 can be regarded as the operation Y = A + B when A = B = 0 (Y = A−B, Y = A &).
B, Y = A | B), and calculation Y = A
Is an operation when B = 0, Y = A + B (or Y = A−B, Y
= A | B), the operation Y = B is the operation Y = A + when A = 0.
It can be treated as B (or Y = A | B). Therefore, calculation Y =
The four lower tables corresponding to 0, Y = A, Y = B, Y = -B are unnecessary.

If A = 0, the operation Y =! B,
It is possible to reduce the three subordinate tables corresponding to Y = B + 1 and Y = B-1. Bitwise AND of concatenated bit string of A and B values with mask pattern 00001111
By performing the operation, the concatenated bit string is 00000000
Since only 16 possible values from 0 to 00001111 are possible, it is possible to reduce the number of elements in the lower table from 256 to 16.

FIG. 24 is a hierarchy truth table 2 shown in FIG.
It is a figure explaining the element reference method of 07.

Next, the value of the signal OP is 1100 (decimal 1
2: calculation Y = -B is selected), and the value of A is 0101
The method of referring to the elements of the hierarchical truth value table 207 will be described by taking the case of obtaining the value of Y when the value of (decimal number 5) and the value of B are 0110 (decimal number 6) as an example.

First, one element of the upper table 231 is referred to using the value 12 (reference numeral 241 in the figure) of the control system signal OP as a subscript. Find the lower table 232 (2) corresponding to operation Y = A−B (rather than operation Y = −B) by its contents. Next, the value 0101 of the data system signal A and the value 011 of the B signal
0 concatenated bit string 0101110 (reference numeral 24 in the figure
2) mask pattern 00001111 (reference numeral 2 in the figure)
43) and bitwise AND operation is performed, and the result 00
Lower table 232 (2) corresponding to operation Y = A-B with 000110 (decimal number 6: 244 in the figure) as a subscript
Refer to one element of. The content 11010 (decimal number-
6) is the calculated Y value.

Since each element of the upper table 231 has information indicating the lower table and the mask pattern, it is assumed that two units of storage area are required. For each of the lower table 232, one unit of storage area is required for each element. Since the upper table 231 needs an element for each possible value of the 4-bit signal OP, it requires a storage area of 32 (= 2 × 2 4) units. Calculation Y = A + B,
The four lower tables 232 (1)-(4) corresponding to Y = A-B, Y = A & B, Y = A | B have 2 for each.
A storage area of 56 (= 2 to the 8th power) units is required. Calculation Y =! The lower tables 232 (5) to 232 (7) corresponding to B, Y = B + 1, Y = B-1 have 16 (= 2
(4 to the fourth power) unit is required.

Therefore, for the example of the 4-bit ALU, the storage area required for storing the hierarchical truth table 207 according to this embodiment is 1104 (= 32 + 256 × 4 + 16 × 3).
It is a unit. This is 27% of the size (4096 units) according to the conventional technique shown in FIG. 27, and the storage area is about 1/4.

According to this embodiment, in addition to the above embodiment, a mask pattern for invalidating a part of the pattern of the input signal is added to each element of the upper table, so that more of the upper table can be obtained. In addition to being able to share the lower table among the elements of, it is also possible to keep the size of some of the lower tables small, which further reduces the storage area required to store the truth table. There is.

In the above embodiment, the truth table having a two-level hierarchical structure is used. However, the present invention can be applied to a hierarchical structure having an arbitrary number of stages, and can be applied to circuit components having complicated functional specifications. Is effective. Also, the AND operation is performed on the lower table for each bit with the mask pattern.
Other operations such as bitwise OR operation can also be used.
Further, the above-described embodiment is not limited to the logical simulation, but may be, for example, a relational operation mechanism in a relational database,
The calculation of a function whose domain is a finite number of discrete values can also be applied to a field such as a basic operation.

FIG. 25 shows V in the compiling method of the description language of the logic circuit according to the third embodiment of the invention.
It is a figure which shows the reference sequence of a HDL description file.

In FIG. 25, a description language (H
The following processing is performed at the time of compiling a VHDL description which is a type of DL). If there is a file referenced by the compiling description, register it in the referenced file table. At that time, the declarative entity name that is referred to is also registered in the reference entity table. In addition, the compiled file name is registered in the reference source file table of the reference destination file.

In FIG. 25, when compiling PKG2 of VHDL description, the file name PKG1 is registered in the reference file table of PKG2, and the file name PKG2 is registered in the reference source file table of PKG1. Also, PKG2
In the reference entity table of the declaration name PKG1. Register T. Such registration can be performed by using the VHDL description PKG1, PKG.
2. Created when compiling ENTA and ENTB.

If these data are registered, for example, when the ENTB of the VHDL description is modified and then recompiled, the file name PKG2 is extracted from the reference file table of the ENTB, and the reference file table of the VHDL description PKG2 is extracted. The file name PKG1 is taken out. And
It is checked whether or not recompilation is necessary by comparing the creation times of the PKG1 source program and the objet program.

First, if the creation time of the object program of PKG1 is later than the creation time of the source program, it is determined that recompilation is not necessary, and the file names PKG2 and ENTB are fetched from the reference source file table of PKG1. Next, the creation time of the object program of PKG2 and ENTB is compared with the creation time of the object program of PKG1. If the creation time of the object program of PKG2, ENTB is earlier than that of PKG1,
Recompile the description PKG2 and ENTB.

If the creation time of the object program of PKG2, ENTB is later than PKG1, PKG2,
Compare the creation time of the source program of the ENTB and the object program, and recompile if necessary. It will automatically compile in the order of this reference sequence.

The following processing is also performed at the time of compiling.
If the description being compiled may be referred to (a package declaration or a configuration declaration in VHDL), various declarations are described therein. If there is a declaration that has been modified during recompilation, register it in the modified entity table. If you are referencing another file, register the referencing name in the reference entity table.

In FIG. 25, the declaration U of PKG1 is modified and registered in the modified entity table. A declared with U is also registered in the modified entity table. Here, when ENTA is recompiled, the file name PKG2 from the referenced file table and the declaration name PKG2. Get B. further,
From the reference file table of PKG2, file name PKG1,
From the reference entity table, declare name PKG1. Get T.

Here, the PKG that has been recompiled
Although the declared names U and A are obtained from the modified entity table of No. 1, it is understood that PKG2 does not need to be recompiled because it is different from the reference entity name T of PKG2. Therefore, without recompiling the PKG2, only the compile time is updated and the ENTA is recompiled. As a result, only the ENTA performs the recompilation, which shortens the compilation time.

[0130]

As described above, according to the first aspect of the invention, in operations that are not exactly the same,
By converting the calculation into an equivalent calculation, it is possible to refer to the same table as other calculation. This makes it possible to share a table between multiple operations,
The number of tables can be reduced, and the storage capacity can be reduced during simulation.

According to the second aspect of the present invention, by implementing the functional specifications of the circuit constituent elements as a hierarchical truth table, a part of the lower ranks of a plurality of elements of the upper partial truth table can be used. The partial truth table can be shared, which has the effect of saving the storage area required for storing the truth table. Therefore, since the storage area for the truth table can be saved, there is an effect that the logic simulation using the truth table can be performed even for a relatively large circuit component.

According to the third aspect of the invention, the work of sequentially compiling in accordance with the reference sequence of the HDL description is automatically processed. In addition, you can determine which files do not need to be compiled and skip the compilation,
You can save compilation time.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a logic circuit simulation apparatus according to an embodiment of the present invention.

FIG. 2 is a flowchart showing an HDL description analysis processing flow of the device shown in FIG.

FIG. 3 is a flowchart showing a merge determination unit processing flow of the apparatus shown in FIG.

FIG. 4 is a flowchart showing an algorithm of some steps shown in FIG.

5 is a flowchart showing a processing flow of a table creating unit of the apparatus shown in FIG.

6 is a flowchart showing a table creation processing flow of the device shown in FIG.

7 is a diagram showing an example of an HDL description of the device shown in FIG.

FIG. 8 is a diagram showing an example of an operator sequence of the apparatus shown in FIG.

FIG. 9 is a diagram showing an example of merge with poor simulation efficiency.

10 is a diagram showing an example of application of a merge rule of the device shown in FIG.

11 is a diagram showing an example of a merge information table of the device shown in FIG.

FIG. 12 is a diagram showing an example of an algorithm of a redundant expression of the apparatus shown in FIG.

13 is a diagram showing an example of conversion of a redundant expression of the apparatus shown in FIG.

FIG. 14 is a diagram showing a configuration of a logic circuit simulation apparatus according to an embodiment of the present invention.

15 is a flowchart showing a processing flow of the hierarchical truth value table creating means of the two-stage structure shown in FIG.

16 is a diagram showing one configuration of the simulation means shown in FIG.

FIG. 17 is a diagram showing the structure of an event of the device shown in FIG.

18 is a flowchart showing a processing flow of the simulation means shown in FIG.

FIG. 19 is an explanatory diagram of the processing contents of the evaluation means of the simulation means shown in FIG.

FIG. 20 is a diagram showing the configuration of a logic circuit simulation apparatus according to another embodiment of the invention as set forth in claim 2;

FIG. 21 is a diagram showing the structure of a hierarchical truth table in the device shown in FIG.

22 is an explanatory diagram of an element reference method of a hierarchical truth value table in the device shown in FIG.

23 is a diagram showing the structure of a hierarchical truth table in the device shown in FIG.

FIG. 24 is an explanatory diagram of an element reference method of a hierarchical truth value table in the device shown in FIG.

FIG. 25 is a diagram for explaining a method of compiling a description language of a logic circuit according to an embodiment of the invention described in claim 3;

FIG. 26 is a diagram showing a configuration example of a 4-bit ALU.

FIG. 27 is an explanatory diagram of a structure of a truth table and an element referring method in a logic circuit simulation device using a truth value according to a conventional technique.

[Explanation of symbols]

1 Simulation device main body 2 HDL description 11 HDL description analysis unit 12 Operator sequence holding unit 13 Merge determination unit 14 Operation code generation unit 15 Operation execution unit 16 Table creation unit 17 Table holding unit 71 HDL description example before correction 72 After correction HDL description example 81 Example of operator sequence before modification 82 Example of operator sequence after modification 111 Merge information table before modification 112 Merge information table after modification 141,201 Logic circuit simulation device 142 Circuit description analysis means 143 Hierarchy Truth table creation means 144 Simulation means 145 Circuit description 146 Functional specifications 147 Hierarchical truth table 148 Library information 149 Connection information 150 Test pattern 151 Simulation result 170 Event 171 Signal identification information 172 Signal new value 17 3 Scheduled change time of signal 191, 221, 241 Concatenated bit string by upper signal 192, 211, 231 Upper table 193, 212, 232 Lower table 194, 222, 242 Concatenated bit string by lower signal 203 Hierarchical truth table Creating means 204 Simulation means 207 Hierarchical truth table 243 Mask pattern 244 Result of AND operation for each bit 271 Concatenated bit string 272 Truth table 1441 Simulation clock 1442 Event management means 1443 Signal value storage section 1444 Re-evaluation target determining means 1445 Evaluation means 1446 result output means

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takashi Ishikawa 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Toshiba Research & Development Center

Claims (3)

[Claims] 1. An HDL description analyzing means for analyzing a hardware description language (HDL) describing a function of a logic circuit to be simulated and extracting an operator sequence which is a sequence of operators for each sentence, and the HDL. A merge determination unit that determines whether or not sharing between the operator sequences is possible from the operator sequence for each sentence obtained by the description analysis unit, and an operation code that can perform simulation based on the merge determination result by the merge determination unit. Simulation of a logic circuit comprising: an operation code generating unit for generating; and a table creating unit for executing an operation from the operation code generated by the operation code generating unit and creating a table storing the operation result. apparatus. 2. A circuit description analysis means for inputting a circuit description and for each kind of circuit constituent element having a logical operation function, and generating definition information of a pattern of an output signal with respect to a pattern of an input signal which is a functional specification thereof. Hierarchy for creating a hierarchical truth table composed of input signal groups of the above-mentioned circuit components, creating partial truth tables for each set, and connecting them hierarchically A logic circuit simulation device, comprising: a conversion truth value table creating means; and a simulation means for determining an output signal pattern from an input signal pattern for each of the circuit components using the hierarchical truth value table. . 3. A step of storing reference relationship information between HDL sources in a file when compiling a hardware description language (HDL) that describes the function of a logic circuit to be simulated, and the reference when compiling the HDL source. The step of determining whether or not the referenced source file has been changed based on the relation information and determining whether or not the referenced source needs to be recompiled; A method of compiling a functional description language for a logic circuit, comprising: a step of compiling.