JPH07198877A - Time data receiver - Google Patents

Abstract

PURPOSE:To provide a time data receiver capable of avoiding that a large error is undesirbly included in the present time data due to the incidental duplication of unavailability in the correction of the present time data in a time counter circuit when it is in an non-receivable circumstance at a wave reception timing. CONSTITUTION:The time data receiver is so constituted as to be controlled with a CPU1, one hour is set in the reception interval memory TM of RAM 9, a time code TC is received at every one hour and exact present time is obtained to correct the present time data of a time counter circuit 7. If wave reception is unavailable, 10 minutes is set in the reception interval memory TM, rereception at every 10 minutes is tried and the present time data in the time counter circuit 7 is corrected as early as possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time data receiving device generally called a radio clock.

[0002]

2. Description of the Related Art Currently, each country (for example, Germany, United Kingdom,
(Switzerland, Japan, etc.), a long wave standard time signal with a time code, that is, a time code, is transmitted. JG in our country
2AS (experimental station) sends out a 40 KHz long-wave standard radio wave amplitude-modulated by a time code in the format shown in FIG. The time code of our country is
Every minute of the exact time is updated (ie, every minute) in a one-minute format. Then, as shown in FIG. 4, in the frame of 1 minute, a pulse having a pulse width of 0.2 seconds, which rises at the start time, that is, the start time of 0 seconds, is arranged. It is also arranged at the time points of 9, 19, 29, 39, 49 and 59 seconds (indicated by symbols P _{0 to} P ₆ in FIG. 4). Therefore, the border of the frame is almost 1
Although there are two pulses having a pulse width of 0.2 seconds (that is, the one indicated by P ₆ and the one indicated by P ₀ ) at intervals of 2 seconds (this recognizes the start of a new frame). As will be possible, the later of the two pulses is referred to as the frame reference marker (hence the frame reference marker or P ₀ , the leading edge of the pulse is exactly the minute of the current time). Will be updated). Then, in the frame, the minute, hour, and accumulated date (the number of days from January 1) of the time when the frame starts
Each data of 1s, 10s and 30-4
It is arranged in a binary coded decimal number in the 0 second generation. In this case, logic 1 and 0 are represented by pulses having pulse widths of 0.5 seconds and 0.8 seconds, respectively (see FIG. 4). In addition, a pulse having a pulse width of 0.8 seconds, which is used as a mere delimiter rather than as data, is appropriately arranged). Note that the frame shown in FIG. 4 displays data at 18:42 on the integrated date 253.

By the way, in recent years, a radio timepiece, that is, a time data receiving device, which has a receiving circuit to receive the time code and corrects the present time data counted by the built-in time counting circuit, has been put into practical use. .

[0004]

In the conventional time data receiving apparatus as described above, the above-mentioned operation of correcting the current time data of the time counting circuit is carried out at intervals of a predetermined fixed time (for example, 1 hour). Be done. Therefore, this time data receiving device happens to be in a poor radio wave reception environment at the above operation timing, the radio wave cannot be received, and the current time data of the time counting circuit is not corrected. However, at the next operation timing, by accident, when the user entered the environment and could not receive the radio wave, and the correction was not performed,
Miscalculations are accumulated in the current time data of the time counting circuit, which is extremely inconvenient in a time data receiving device that places importance on accuracy. The present invention has been made in view of the circumstances as described above, and the fact that the current time data of the time counting circuit cannot be corrected due to an unreceivable environment at the radio wave reception timing is accidentally overlapped. An object of the present invention is to provide a time data receiving device capable of avoiding the time data from including a large error.

[0005]

In order to achieve the above object, the present invention provides a time data receiving device, a time counting means for obtaining time data by counting a reference clock signal, and a time code at a predetermined interval. Receiving means for receiving the standard radio wave including the receiving time data, determining means for determining whether or not accurate receiving time data was obtained by this receiving means, and accurate receiving time data was obtained by this determining means. If it is determined that the time data of the time counting means is corrected to the reception time data obtained by the receiving means, and if the determination means determines that accurate reception data cannot be obtained, It is configured to include an interval changing unit that shortens the predetermined interval.

[0006]

In the receiving timing, when the receiving means happened to have bad receiving conditions and the receiving means could not obtain accurate receiving time data, the discriminating means discriminates to that effect, and based on the discriminating result of the discriminating means. The interval changing means attempts frequent reception with a short receiving interval of the receiving means, obtains the accurate reception time data as early as possible, and corrects the current time data of the time counting circuit.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to an embodiment shown in the drawings. FIG. 1 shows the circuit configuration of this embodiment. That is, in the present embodiment, the CPU 1 is the main component, and the other circuit parts are connected thereto.
Is a circuit section that processes and processes the transmitted data, sends the data, and sends a control signal to the connected circuit section to control them. The antenna 2 is a circuit unit that receives a transmitted electric wave, converts the electric wave into a corresponding electric signal, and transmits the electric signal to the receiving circuit 3. The receiving circuit 3 is activated upon receiving a reception start / end signal C from the CPU 1, selects a signal of a specific frequency from the electric signal from the antenna 2, obtains the time code or time code TC from the signal, and outputs the time code TC.
This is a super-heterodyne type receiving circuit that sends out to PU1 and then stops the operation upon receiving the reception start / end signal C. That is, the receiving circuit 3 includes a tuning circuit for extracting the specific frequency signal from the electric signal from the antenna 2, a high frequency amplifier circuit for amplifying the extracted specific frequency signal, and a PLL frequency synthesizer used as a local oscillator. A mixer that mixes the signal amplified by the high-frequency amplifier circuit with the signal from the PLL frequency synthesizer, a bandpass filter that extracts a desired intermediate frequency signal from the signal from the mixer, and a bandpass filter that extracts the signal. A detection circuit for obtaining a baseband signal from an intermediate frequency signal, and a baseband signal obtained by this detection circuit is converted into a digital signal to obtain C as the time code TC.
It is composed of an A / D conversion circuit for sending to PU1.

The oscillating circuit 5 is a circuit portion which constantly sends a signal of a constant frequency, and the frequency dividing circuit 6 is an oscillating circuit 5.
The signal from 1 is counted and the 1-minute signal M is sent to the total clock circuit 7 each time the count value becomes a value corresponding to 1 minute, and the count value is set to 1 each time the preset signal P from the CPU 1 is received. It is a circuit section that is made larger by a second. The clock counting circuit 7 counts the 1-minute signal M from the frequency dividing circuit 6 to obtain the current time data, that is, the date data of the current day and the current hour data and minute data, and supplies them to the CPU 1 and the CPU 1 It is a circuit unit that corrects the current time data counted by the time data from.

The switch section 8 is a circuit section that includes various switches and sends a corresponding switch input signal to the CPU 1 when any of these switches is operated. The RAM 9 is a circuit unit that includes various registers described below, stores the data from the CPU 1 under the control of the CPU 1, and sends the stored data to the CPU 1. The display unit 10 is a circuit unit that digitally displays the data from the CPU 1, for example, the current time data by the clock counting circuit 7.

Next, various registers provided in the RAM 9 will be described. Reception time memory X1 to X3
Receives the time code TC three times in succession every minute in one time correction operation, that is, a radio wave correction process (step S4 in FIG. 2) described later, and the reception time data extracted from these is received respectively. The reception accumulated date memories D1 to D3 are stored in the reception time memory X.
The date data obtained by converting the integrated date data sent together with the reception time data stored in 1 to X3 is a memory to be stored, respectively, and the reception current time memory X is stored in the reception time memory X3. It is a memory that stores time data that is one minute after the reception time data,
In addition, the reception present cumulative date memory D is the above reception cumulative date memory D.
3 is a memory in which the date data stored in 3 is stored. The reception interval memory TM is a memory that stores the execution interval time of the process of correcting the current time data of the total clock number circuit 7 with the reception time data, that is, the radio wave correction process (step S4). The unreceivable flag F _NG is a flag register that is set to 1 when normal reception was not possible during the current radio wave correction processing, even though normal reception was possible during the previous radio wave correction processing. The improper count register NC is a register that counts from the radio wave correction processing when 1 is set to the reception prohibition flag F _NG to the number of times the radio wave correction processing is continued and normal reception is not possible.

The operation of this embodiment having the above arrangement will be described below. 2 is a general flow chart showing an outline of the operation of this embodiment, and FIG. 3 is a flow chart showing in detail the radio wave correction processing of step S4 of FIG. In the present embodiment, first, in step S1, the switch unit 8
It is determined whether or not there is a switch input by operating one of the switches. When there is a switch input, the process proceeds to step S2, the corresponding switch process is executed, and then the process proceeds to step S3. When there is no input, the process directly proceeds from step S1 to step S3. In step S3, the reception interval memory TM starts from the date and time stored in the reception current accumulated date memory D and the reception current time memory X, that is, from the date and time when the previous radio wave correction process (that is, the process of the next step S4) is performed. It is judged whether the time corresponding to the execution interval time stored in the time has elapsed, and if such time has elapsed, step S
4, and after executing the radio wave correction process described in detail later, the process proceeds to step S5. However, when it is determined in step S3 that the time has not yet elapsed, the process directly proceeds from step S3 to step S5. Proceed to. In step S5, a display process for displaying the current time of the total clock circuit 7 on the display unit 10 is executed, and thereafter, the above-described step S5.
Returning to 1, the same operation is repeated thereafter.

Next, the radio wave correction processing (step S4) will be described in detail. As described above, FIG. 3 shows the radio wave correction processing in detail. That is, the reception interval memory T
The time corresponding to the execution interval time stored in M has elapsed,
When this processing is entered, first, in step S10, the reception start / end signal C is sent to the reception circuit 3 to activate the reception circuit 3 to start the reception operation, and at the same time, the reception operation of the reception circuit 3 causes this reception circuit 3 to start. Take in the time code TC sent from 3. And the next step S1
In No. 1, the above time code TC is checked for the frame reference marker, and the operation is repeated until the frame reference marker is sent. When the frame reference marker is found, this step S1
From 1 to step S12, the reception time data (that is, the minute and hour data) and the reception integrated date data are extracted from the time code TC sent subsequently to the frame reference marker, and in the next step S13, the above The reception time data is stored in the reception time memory X1 of the RAM 9,
After that, the process proceeds to step S14, the received cumulative date data is converted into date data (data of what month and what day), and the obtained date data is stored in the received cumulative date memory D1 of the RAM 9. Next, in step S15, the total clock number circuit 7
A display process of digitally displaying the current time data and the like on the display unit 10 is executed, and then the process proceeds to step S16. In step S16, since the reception start / end signal C is sent to the receiving circuit 3 this time to start reception, the detection of the frame reference marker (which is sent every 1 minute as described above) is performed 3 times.
It is judged that the operation has not been performed (that is, the extraction of the three types of reception time data that differ by 1 minute has not been completed), and the process returns to step S11.

As described above, after returning to step S11, the frame reference marker (that is, the first frame reference marker) sent next to the frame reference marker (hereinafter referred to as the first frame reference marker) in step S11. It is a frame reference marker sent one minute after the frame reference marker is sent.
Search for the second frame reference marker) from among the time codes TC sent one after another. When the second frame reference marker is found, step S12
Proceed to. Then, in step S12, the reception time data and the reception integrated date data are extracted from the time code TC following the second frame reference marker, and in the following step S13, the reception time data is received.
2 and then the process proceeds to step S14 to convert the received accumulated date data into date data and store it in the received accumulated date memory D2. After that, in step S15, the current time data of the total clock circuit 7 is displayed on the display unit 10, and the process proceeds to step S16, in which the reception operation of this time is started in the same manner as described above, and the frame reference marker is still detected. After determining that the process has not been performed three times, the process returns to step S11.

After returning to step S11 as described above, frame reference markers (hereinafter referred to as third frame reference markers) sent next to the second frame reference marker in step S11 are sent one after another. Search from the time code TC that is received. When the third frame reference marker is found, step S
In step S12, the reception time data and the reception integrated date data are extracted from the time code TC following the third frame reference marker, and in step S13, the reception time data is stored in the reception time memory X3. In step S14, the received accumulated date data is converted into date data and stored in the received accumulated date memory D3.
After that, in step S15, the current time data of the total clock circuit 7 is displayed on the display unit 10, and the process proceeds to step S16, in which the frame reference marker has already been detected three times since the current reception operation was started. If it is determined that it exists, the process proceeds to step S17.

When the process proceeds to step S17 as described above, it is determined in this step whether or not the reception is normally performed in the current radio wave correction processing without being affected by the radio wave obstacles and the like. That is, the data obtained by this reception is meaningful and the reception time memories X1 to X1
The three reception time data stored in X3 are sequentially delayed by one minute, and the reception accumulated date memory D1
It is determined whether the three date data stored in D3 are the same. When it is determined that the current reception is normally performed, the process proceeds to step S30, the value of the reception disable flag F _NG is set to 0, the value of the reception disable count register NC is set to 0 in the next step S31, and further in step S32. One hour is set in the reception interval memory TM to perform the next radio wave correction processing after one hour. In a succeeding step S33, the time data obtained by adding 1 minute to the reception time data stored in the reception time memory X3 is stored in the reception current time memory X (the time data obtained by adding 1 minute is stored in the reception current time memory X in this manner). It should be remembered that, as will be described below, after waiting for the frame reference marker, that is, the fourth frame reference marker sent at a time point of 1 minute after the third frame reference marker is sent, This is because the operation of correcting the current time data of the total clock number circuit 7 is executed).

After the process of step S33 is completed, the date data of the reception integrated date memory D3 is also stored in the reception current integrated date memory D in step S34, and in the subsequent step S35, the fourth frame reference marker is stored. However, when the fourth frame reference marker is detected, the process proceeds to step S36. In step S36, 1 is set from the rising time of the fourth frame reference marker.
The rising edge of the pulse that rises when the second has elapsed (that is, in FIG.
In waiting for the time) represented by T _1, when detecting the rise, the process proceeds to step S37. Then, in this step S37, the time data stored in the reception current time memory X (as described above, since this is the time data at the time of the rising of the fourth frame reference marker, at the present time, the time data of 1 second old is used. Time data) and the reception date data stored in the reception current accumulated date memory D are forcibly set in the total clock circuit 7 as the current time data. In the following step S38, the above step S2
As described above, the current time data set in the total clock circuit 7 in 7 is one second older than the current time, that is, the time is delayed, so to correct this, the following 1
A preset signal P is given to the frequency dividing circuit 6 so that the minute signal M is transmitted after 59 seconds instead of after 60 seconds, and the count value of the frequency dividing circuit 6 is forcibly increased by a count value corresponding to 1 second. I will keep it. Step S3 as described above
After finishing the process of 8, the process proceeds to step S39, the reception start / end signal C is sent to the receiving circuit 3, the receiving operation of the receiving circuit 3 is stopped, the radio wave correction process is finished, and the process proceeds to step S5 of FIG. And proceed.

The above operation is performed when the time data receiving device is placed in a place where the radio wave reception environment is good and the radio wave correction processing is performed normally every one hour. The following operation is performed when the device is taken to a place where the radio wave reception environment is bad and normal reception cannot be performed. That is, steps S1 to S in FIG.
When 1 hour (that is, the execution interval time) has elapsed from the time of the previous execution of the radio wave correction processing while repeating the processing of 3 and S5, that is detected in step S3 of FIG. Proceed to radio wave correction processing. Then, after executing the same processing (steps S10 to S16) as described above, it is determined in step S17 that normal reception was not possible this time, and the process proceeds to step S18. This step S
In 18, it is determined whether the received invalid flag F _NG is set to 0, this case, the Ready flag F _NG is set to 0 the process proceeds to the next step S19, the value of the Ready flag F _NG In this radio wave correction process, the fact that normal reception could not be performed is stored, and then step S2 is performed.
At 0, 10 minutes later, 10 minutes is set in the reception interval memory TM to try reception again. And step S2
In the case of 1, the set value of the unreceivable frequency register NC is incremented by 1, that is, in this case, it is set to 1 and it is stored that there is one radio wave correction process that cannot be received, and the process proceeds to step S39 to start reception.・ Reception circuit 3 receives the end signal C
To stop the reception operation of the receiving circuit 3 to end the current radio wave correction processing, execute the display processing of step S5 of FIG. 2, and return to step S1.

When 10 minutes (that is, the execution interval time set in the reception interval memory TM) elapses from the above state, it is detected in step S3 of FIG. 2, and step S4, that is, the radio wave correction process of FIG. 3 is performed again. And proceed. And
Steps S10 to S16 are executed in the same manner as described above, and the process proceeds to step S17, and it is determined whether the current reception is normally performed, as described above. Then, if the reception is not normally performed this time, the process proceeds to step S18, and the value of the reception disabled flag F _NG is 1 instead of 0, and it is confirmed that the reception cannot be normally performed even in the previous radio wave correction process, and the step is performed. S2
Go to 5. In this step S25, it is determined that the value of the unreceivable frequency register NC has not reached 6, and in the next step S21 the value of the unreceivable frequency register NC is increased by 1 by 2, and in the following step S39, the reception circuit 3 When the reception operation is stopped and the radio wave correction processing is completed,
The process proceeds to steps S5 and S1.

Hereinafter, unless normal reception is performed, the same operation as described above is repeated and the radio wave correction processing is performed every 10 minutes (see FIG. 2).
Performing step S4 of FIG.
Each time, the value of the unreceivable frequency register NC is increased by 1, but when the radio wave correction processing that cannot perform normal reception is successful before 7 consecutive times, it is set as shown in FIG. Detected in step S17
Proceed to 30. Then, in this step S30, the value of the reception disable flag F _NG is returned from 1 to 0 to store the fact that normal reception is performed, and in the next step S31, the value of the reception disable count register NC is cleared to 0, Then, set 1 hour as the execution interval time in the reception interval memory TM,
Hereinafter, the same processing (steps S33 to S39) as described above is executed.

The above is the case where the abnormal reception does not continue seven times in succession and there is a normal reception before that, but the value of the unreceivable number register NC becomes 6, that is, continuously. If normal reception cannot be performed 6 times and normal reception is not possible even in the next radio wave correction processing, the process proceeds to step S25 through steps S17 and S18 of FIG. When it is detected that the number is already 6, the process proceeds to step S26, the value of the reception disable flag F _NG is set to 0, 24 hours is set as the execution interval time in the reception interval memory TM in step S27, and the number of times of reception failure is received in step S28. After clearing the value of the register NC, the receiving operation of the receiving circuit 3 is stopped in the following step S39, the radio wave correction process is completed, and the process proceeds to steps S5 and S1 in FIG.
That is, when normal reception is not possible 7 times in a row (at this time, 60 minutes have passed from the first time),
It is judged that the time data receiving device is left in a place where the radio wave reception environment is bad, and it is considered useless to try reception every 10 minutes thereafter, and the next radio wave correction operation should be performed 24 hours later. To do.

[0021]

As described in detail above, according to the present invention, the time counting means for counting the reference clock signal to obtain the time data, and the standard time signal including the time code at a predetermined interval to receive the received time data. A receiving means for obtaining, a judging means for judging whether or not accurate receiving time data is obtained by this receiving means, and a time of the time counting means when it is judged that accurate receiving time data is obtained by this judging means. A correction unit that corrects the data to the reception time data obtained by the reception unit, and an interval changing unit that shortens the predetermined interval when the determination unit determines that accurate reception data cannot be obtained. Since it is related to the time data receiving device provided, at the radio wave reception timing, it is in an unreceivable environment
This makes it possible to provide a time data receiving device that can prevent the fact that the current time data of the time counting circuit cannot be corrected from accidentally overlapping and enclosing a large error in the current time data.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a general flowchart showing an outline of the operation of the above embodiment.

FIG. 3 is a flowchart showing in detail the radio wave correction processing of FIG.

FIG. 4 is a diagram showing a format of a time code.

[Explanation of symbols]

M 1-minute signal TC time code X1 to X3 reception time memory D1 to D3 reception accumulated date memory X reception current time memory D reception current accumulated date memory TM reception interval memory F _NG reception disabled flag NC reception disabled count register

Claims (1)

[Claims] 1. A time counting means for counting a reference clock signal to obtain time data, a receiving means for receiving a standard radio wave including a time code at predetermined intervals to obtain received time data, and an accurate receiving means for the receiving means. Determination means for determining whether or not the reception time data is obtained, and the reception time obtained by the reception means for the time data of the time counting means when the determination means determines that accurate reception time data is obtained A time data receiving apparatus comprising: a correction unit that corrects the data and an interval changing unit that shortens the predetermined interval when the determination unit determines that accurate received data cannot be obtained.