JPH07194105A - Synchronous rectifier - Google Patents

Abstract

PURPOSE:To suppress a reverse recovery current and simplify a circuit by a method wherein an insulating gate which is separated from a back gate is provided and a reverse bias is applied to the back gate. CONSTITUTION:After a MOS-FET 6 is turned on once, it is turned off. At the timing when the MOS-FET 6 is turned on again, a lateral MOS-FET 5 is turned off. After an output current is regenerated by an SBD 7 in a period during which both the MOS-FET's 5 and 6 are in off-states and switched to an input current by the MOS-FET's. At that time, as the electric continuity of the parasitic diode of the lateral MOS-FET is blocked by the reverse bias effect of the back gate of the lateral MOS-FET, problems caused by a reverse recovery phenomenon are not produced. With this constitution, noises, commutation dV/dt breakdown, etc., can be avoided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous rectification circuit, and more particularly to a DC / DC converter.

[0002]

2. Description of the Related Art Referring to FIG. 5 showing a cross section of a vertical MOSFET for rectification used in a conventional synchronous rectification circuit, this device has an electrode for a drain 2'on a lower main surface of an N + type region. , There is an N-type region on the upper surface of this region, and further there is a region of the back gate 1 ', and there is an N-type region in this, the source electrode 3'is formed on the surface, and the insulated gates 4'are formed on both sides thereof It is provided. This device is a so-called vertical MOSFET in which the region of the back gate 1'and the electrode of the source 3'are connected to each other.

Referring to FIG. 6 showing a conventional synchronous rectification circuit using this element, MOSFETs 6 and 17 correspond to the above elements, a Schottky barrier diode (SBD) 7 is connected in parallel with the elements, and an inductance 9 is provided. MOSFET for switching the input power source 8 by connecting the load 12 as a resistance in parallel with the smoothing capacitor 10 via
6 is connected to the drain electrode of MOSFET 17. The gate electrodes of these MOSFETs 6 and 17 are the control circuit 1
Controlled by 1.

In this conventional circuit, the rectifying MOSFET 17 connected in parallel with the SBD 7 is forward biased during regeneration, and a regenerative current flows through the channel of the MOSFET.

That is, the MOSFET 6 for the main switch
When is off, the regenerative current of the coil is SBD7 and MOSFE.
Flows through T17 (gate ON). At this time, in the conventional N-channel vertical MOSFET, the parasitic diode in the substrate also conducts, so that a reverse recovery phenomenon occurs when the MOSFET 6 is turned on, a reverse recovery current flows, and loss occurs.

Here, the SBD 7 is a MOSFET when the MOSFET 17 is turned off or turned off.
It is used to suppress the voltage drop (about 0.6V) of the parasitic diode of T17 to about 0.4V.

Further, as another example of the prior art [Japanese Patent Laid-Open No. 4-12
No. 7869].
The recovery loss and the reverse channel current are adjusted by properly adjusting the MOSFET turn-off timing so that the FET turn-off timing is judged and the current is not passed through the body diode and the reverse current is not passed through the channel. MO that prevents loss due to
A synchronous rectification circuit using SFET has been proposed.

[0008]

In the conventional example shown in FIG. 6, the parasitic diode of the MOSFET 17 connected in parallel with the SBD 7 is forward biased to cause a minority carrier accumulation phenomenon, and the parasitic diode is reversed when the MOSFET 6 is turned on. A recovery phenomenon occurs. When this reverse recovery phenomenon occurs, reverse recovery loss occurs, and a peak reverse recovery current occurs between the drain and source of the MOSFET during the reverse recovery period, which causes noise and the like. Also, the MOSFET itself has various problems such as the risk of commutation dV / dt breakdown.

In addition, the other conventional example has a drawback that an algorithm for determining timing is considerably complicated and a circuit scale is remarkably increased.

An object of the present invention is to provide a synchronous rectification circuit which solves the above-mentioned drawbacks, prevents reverse recovery phenomenon, suppresses reverse recovery current, and requires a very simple circuit.

[0011]

The first structure of the present invention is as follows.
A diode and a rectifying field effect transistor are connected in parallel via an inductance to a parallel connection circuit of a smoothing capacitor and a load, and a voltage from a power source is turned on / off to be supplied to the field effect transistor. In the synchronous rectification circuit including a transistor, the rectifying field effect transistor has an insulated gate structure separated from a back gate, and means for applying a reverse bias to the back gate is provided.

According to a second aspect of the present invention, a diode and a first field effect transistor are connected in parallel via an inductance to a parallel connection circuit of a smoothing capacitor and a load, and a second field effect transistor and a transformer are connected. In a synchronous rectification circuit, in which a series circuit with the secondary side of the transformer is connected in parallel with the diode and a power supply voltage is turned on / off to supply the primary side of the transformer, the first and second field effect transistors are The insulated gate structure is separated from the gate, and means for applying a reverse bias to the back gate is provided.

[0013]

1 is a sectional view of a rectifying MOSFET included in a synchronous rectifying circuit according to a first embodiment of the present invention. In FIG. 1, in the lateral FET of this embodiment, a back gate 1 made of a P-type substrate has an electrode on the lower surface, and a drain 2, a source 3, and an insulated gate 4 on a channel between them are formed on the upper surface. . In this lateral MOSFET, the insulated gate 4 is forward-biased so that a current can be bidirectionally applied between the drain and the source. The back gate 1 is separated from the insulated gate 4 and can be used by applying a negative bias.

Step-down type D using the above lateral MOSFET
Referring to FIG. 2 showing the synchronous rectification circuit of the C / DC converter, in the lateral MOSFET 5, the back gate 1 is applied with the negative bias VSUB by the bias power supply 13. Other circuit configurations are the same as those in FIG. 6 and will not be described in detail.

In the circuit of this embodiment, the power source 8 for the input voltage Vin is turned on by the MOSFET 6 for the output stage main switch.
Turn off. When the MOSFET 6 is off, the energy of the inductance 9 is regenerated by the SBD 7 and the lateral MOSFET 5 connected in parallel with the SBD 7, so that a current flows through the inductance 9. The control circuit 11 includes a MOSFET 6 for the main switch and a lateral MOSF for synchronous rectification.
Control each gate electrode with ET5.

The back gate 1 of the lateral MOSFET 5
Is a negative bias (about 1.0V) from the bias power supply 13.
Since VSUB is applied, it can be used in a state where the parasitic diode does not conduct.

The operation of the above configuration will be described with reference to FIG. In FIG. 3, the upper stage shows the current IL flowing through the inductance 9, the middle stage shows the current Iin of the input power supply 8, and the lower stage shows the source-drain current IFET of the lateral MOSFET 5 and the current ISBD of the SBD 7. Here, the waveform 30 shows the current IFET and the waveform 31 shows the current ISBD.

Now, when the MOSFET 6 is turned on,
Immediately before this, the regenerative current flowing in the lateral MOSFET 5 and the SBD 7 switches to the input current, and flows into the inductance 9 via the MOSFET 6. When it is turned on for a predetermined period, the off signal of the control circuit 11 causes the MOSFE
T6 turns off. As a result, the inductance 9
Immediately after turn-off, the regenerative current of
Is turned on by the SBD7 and the lateral MOS
When the FET 5 is turned on, it is regenerated by the lateral MOSFET 5. At the timing when the MOSFET 6 is turned on again, the lateral MOSFET 5 is turned off. Both M
After the OSFETs 5 and 6 are regenerated by the SBD 7 during the simultaneous off period, the MOSFET 6 switches the input current. At this time, in the lateral MOSFET 5, since the conduction of the parasitic diode is blocked by the reverse bias effect of the back gate, the problem due to the reverse recovery phenomenon does not occur.

FIG. 4 is a circuit diagram showing a forward converter according to the second embodiment of the present invention. In FIG. 4, two MOSFETs shown in FIG. 1 are used as a rectifying lateral MOSFET 5. The MOSFET 15 that switches the voltage of the input power supply 8 is gate-controlled by the control circuit 11. The series connection circuit of the capacitor and the resistor is the transformer 1.
4 is connected in parallel, and on the secondary side thereof, the lateral MOSF is connected.
A parallel connection circuit of the ET5, the inductance 9, the smoothing capacitor 10 and the load is connected in series. Another lateral MOSFET 5 and SBD 7 are connected in parallel with the load 12, and another SBD is connected in parallel with the lateral MOSFET 5 described above.
7 is connected. The two lateral MOSFETs 5 are gate-controlled by the control circuit 11. 2 horizontal MOSFEs
All the back gates of T5 are biased by the bias power supply 13 and used. As the bias power supply required for this, the input power supply 8 or another power supply may be used, or a dry battery may be used separately.

[0020]

As described above, according to the present invention, the reverse recovery phenomenon caused by the parasitic diode of the rectifying MOSFET can be prevented by using the lateral MOSFET in which the back gate is separated and the negative bias is possible. As a result, it is possible to prevent the occurrence of reverse recovery loss caused by the reverse recovery phenomenon, the generation of noise due to the reverse recovery current, and the breakdown of commutation dV / dt.

[Brief description of drawings]

FIG. 1 is a lateral MOS used in a first embodiment of the present invention.
It is sectional drawing of FET.

FIG. 2 is a circuit diagram showing a synchronous rectification circuit according to a first embodiment of the present invention.

FIG. 3 is a waveform chart showing the operation of the circuit of FIG.

FIG. 4 is a circuit diagram showing a synchronous rectification circuit according to a second embodiment of the present invention.

FIG. 5 is a sectional view of a conventional vertical MOSFET.

FIG. 6 is a circuit diagram of a conventional synchronous rectification circuit.

[Explanation of symbols]

 1,1 'Back gate (substrate) 2,2' Drain 3,3 'Source 4,4' Insulated gate 5 Lateral MOSFET 6,15,17 MOSFET 7 SBD 8 Input power supply 9 Inductance 10 Smoothing capacitor 11 Control circuit 12 Load 13 Bias power supply 14 Transformer 30,31 Waveform

Claims (2)

[Claims] 1. A diode and a rectifying field effect transistor are connected in parallel via an inductance to a parallel connection circuit of a smoothing capacitor and a load, and a voltage from a power supply is turned on / off to be supplied to the field effect transistor. In the synchronous rectification circuit including the switching field effect transistor, the rectification field effect transistor has an insulated gate structure separated from the back gate, and means for applying a reverse bias to the back gate is provided. Characteristic synchronous rectification circuit. 2. A diode and a first field effect transistor are connected in parallel via an inductance to a parallel connection circuit of a smoothing capacitor and a load, and a second field effect transistor and a secondary side of a transformer are connected in series. In a synchronous rectification circuit, in which a circuit is connected in parallel with the diode and a power supply voltage is turned on / off to supply the primary side of the transformer, the first and second field effect transistors are insulated gates separated from a back gate. A synchronous rectification circuit having a structure, wherein means for applying a reverse bias to the back gate is provided.