JPH07182181A - Interruption priority setting circuit - Google Patents

Abstract

PURPOSE:To reduce the burden of a CPU and to eliminate the need for preparing the memories in number equal to the interruption factors by calculating the interruption request frequency by a changing means and changing and resetting the interruption priority when the count value of the request frequency reaches the changing threshold value. CONSTITUTION:A down-counter 12 counts the interruption request frequency within a fixed period by applying -1 to the increment reference value set at an increment reference value setting register 11 for each input of an interruption request signal. Then the counter 12 outputs an increment signal when its count value is O. Meanwhile the interruption priority value is set at an interruption priority setting register 21, and +1 is applied to the set priority value for each input of the increment signal. Thus the interruption priority is increased. It is just required to write the interruption priority increment reference value in the register 11 since the interruption priority is increased by the interruption occurring frequency. As a result, the burden of a CPU is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt priority setting circuit for setting an interrupt priority according to the number of interrupt requests generated within a fixed time.

[0002]

2. Description of the Related Art Interrupt priorities are prepared for each interrupt factor, and can be set by the CPU writing each interrupt priority in an interrupt priority setting register by a program. At the same time, when interrupt requests with the same interrupt priority occur, processing is performed according to the default priority.

On the other hand, there is a system in which the priority of interrupts is changed depending on the frequency of occurrence of interrupts, and in the conventional technique, the number of times of interrupts must be counted by an interrupt processing program. The number of interruptions differs depending on the external environment in which the CPU is used, for example, when an ECU (engine control unit) mounted on an automobile is used in a cold region and a warm region. The priority of interrupts is set assuming a certain external environment, and when used in an environment other than the assumed external environment, the number of interrupts generated may decrease, which may affect control. is there. Also, although it has a great influence on control, it is thought that the frequency of occurrence is low,
The number of times a certain interrupt with a low priority is generated suddenly increases, which may affect the control.

In these cases, in order to perform optimum control, it is necessary to increase the priority and increase the occurrence of interrupt processing for control. In order to increase the occurrence of interrupt processing, the CPU may rewrite the interrupt priority setting register in the program so as to raise the priority, but the criterion for rewriting is that the CPU must count the number of interrupt occurrences in the program. . Then, when the number of occurrences exceeds a certain value, the interrupt priority setting register is rewritten.

[0005]

As described above, since the CPU counts the number of interrupt occurrences in the program and compares the number of occurrences with a certain set value, the load on the CPU is heavy and the number of interrupt occurrences is stored in the memory. However, there is a drawback that it is necessary to prepare memory for the number of interrupt factors.

Therefore, the present invention has been made in view of the above, and an object of the present invention is to reduce the load on the CPU for counting the number of interrupt occurrences, and to provide the memory for the number of interrupt factors. It is to provide an interrupt priority setting circuit that is not needed.

[0007]

In order to achieve the above object, the invention according to claim 1 has a change threshold value for changing the interrupt priority every fixed period or every time a change signal is output. Change means that is externally given and set, counts the number of interrupt requests that occur within a fixed period, and outputs a change signal when the count value reaches the change threshold, and an interrupt priority order for each fixed period. The initial value is set, and the setting unit changes the priority order set according to the change signal output from the changing unit and resets the priority.

[0008]

In the above structure, the invention according to claim 1 is such that the changing means counts the number of interrupt requests and changes the interrupt priority when the counted value reaches the change threshold.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of an interrupt priority setting circuit according to the first aspect of the present invention.

In FIG. 1, the interrupt priority level setting circuit uses an increment criterion as a change threshold value for increasing the interrupt priority level every time a constant period signal is given or an increment signal for increasing the interrupt priority level is output. A value is given by an external CPU and is set. The interrupt request that counts the number of interrupt requests that occur within a fixed cycle defined by the fixed cycle signal and outputs an increment signal when the count value reaches the increment reference value. An interrupt priority setting in which the priority change value of the priority change block 1 and the initial value of the interrupt priority value are set at regular intervals, and the interrupt priority value is increased and reset according to the increment signal output from the interrupt priority change block 1. And block 2.

In the interrupt priority changing block 1, an increment reference value setting register 11 in which an increment reference value is given and set by an external CPU and an increment reference value set in the increment reference value setting register 11 are set, By counting the number of interrupt requests generated within a fixed period by decrementing the increment reference value set for each input of the interrupt request signal by -1, the down counter 12 that outputs the increment signal when the count value becomes 0, and the fixed counter It comprises a logical sum (OR) gate 13 for receiving the periodic signal and the increment signal and setting the increment reference value set in the increment reference value setting register 11 in the down counter 12.

The interrupt priority setting block 2 includes an interrupt priority setting register 21 in which an initial value of the interrupt priority is set by an external CPU at regular intervals, and is set.
The interrupt priority level value set in the interrupt priority level setting register 21 is set, and the up counter 22 is configured to increase the interrupt priority level by incrementing the interrupt priority level value set by +1 for each input of the increment signal. The interrupt priority level changing block 1 and the interrupt priority level setting block 2 are provided for each interrupt factor.

Note that the increment reference value is an external environment to which processing for generating an interrupt request is applied, for example, C for setting an increment reference value or an interrupt priority value.
When the PU is used in an engine control unit that controls the engine of the automobile, a plurality of increment criteria prepared in advance according to the external environment such as the state of the road surface when the automobile controlled by the CPU is running. One of the values is selected.

Next, the operation of the above configuration will be described with reference to the operation timing chart shown in FIG.

First, the initial value of the interrupt priority value for determining the priority of the interrupt is written in the interrupt priority setting register 21. The interrupt priority increment reference value for incrementing the interrupt priority value is written in the increment reference value register 11. Then, the increment reference value (A1) of the interrupt priority is set in the down counter 12, and the initial value of the interrupt priority value is set in the up counter 22 (FIG. 2A).

Next, the interrupt priority increment reference value set by the interrupt request signal is down-counted. Then, when the down counter 12 becomes 0, the increment signal supplied to the up counter 22 is activated, the set interrupt priority value is incremented, and the initial value of the interrupt priority value is incremented by 1 (FIG. 2).
<B>). However, when the value of the up counter 22 reaches the maximum value, it does not increment and remains at the maximum value. At this time, the down-counter 12 is reset with the interrupt priority increment reference value (A2) (see FIG. 2).
<B>).

Next, the interrupt request signal is used to down-count the reset interrupt priority increment reference value. Then, when the constant period signal becomes active, the up-counter 22 and the down-counter 12 are reset with the interrupt priority value and the interrupt priority increment reference value (A1), respectively (FIG. 2C).

Thus, the basic operation is as shown in FIG.
The operations of <b> and <c> are repeated.

The operation of FIG. 2D is the same as the operation of FIG. 2B, and since the down counter 12 has become 0, the interrupt priority value is incremented by one. In addition, the down counter 12
The interrupt priority increment reference value (A2) is reset.

The operation of FIG. 2 <e> is the same as that of FIG. 2 <b>, <d>.
Since the down counter 12 becomes 0 in the same operation as the operation of, the interrupt priority value is incremented by one. +1 in this action
In total, the interrupt priority value becomes +2. Also, the interrupt priority increment reference value (A3) is reset in the down counter 12.

The operation shown in FIG. 2F is the same as the operation shown in FIG. 2C, and the constant period signal becomes active.
The up counter 22 has an interrupt priority value, and the down counter 12 has an interrupt priority increment reference value (A
Reset 1).

FIG. 3 is a diagram showing the configuration of an interrupt priority setting circuit according to the third aspect of the invention.

In FIG. 3, the feature of this embodiment is that the interrupt priority change block 1 compares the count value of the number of interrupt requests with the increment reference value, and the two are equal. The interrupt priority changing block 1 sets the same in the increment reference value setting register 11 and the increment reference value setting register 11 as shown in FIG. The buffer 14 in which the increment reference value thus set is set, the up counter 15 for counting the number of interrupt requests, the count value of the up counter 15 and the increment reference value set in the buffer 14 are compared, and if the two match. A comparator 16 that outputs an increment signal, a constant cycle signal and an increment The interrupt priority setting block 2 is configured by including a logical sum (OR) gate 17 which receives a signal and sets the increment reference value set in the increment reference value setting register 11 in the buffer 14 and clears the up counter 15. Is configured similarly to that shown in FIG.

Next, the operation of the above configuration will be described with reference to the operation timing chart shown in FIG.

First, an initial value of an interrupt priority value for determining an interrupt priority is written in the interrupt priority setting register 21. Next, an interrupt priority increment reference value (B1) for incrementing the interrupt priority value is written in the increment cycle setting register 11. Then, the interrupt priority increment reference value (B1) is set in the buffer 14, the initial value of the interrupt priority value is set in the up counter 22, and the up counter 15 is cleared (FIG. 4A).

Next, the value of the up counter 15 and the value of the buffer 14 are compared by the comparator 16. The up counter 15 is incremented by the interrupt request signal. When the value of the up counter 15 and the set interrupt priority increment reference value match, the increment signal supplied to the up counter 22 is activated and the set interrupt priority value is incremented to set the interrupt priority value. +1 (Fig. 4
<B>). However, when the value of the up counter 22 reaches the maximum value, it does not increment and remains at the maximum value. At this time, the interrupt priority increment reference value (B2) is reset in the buffer 14 and the up counter 15 is cleared (<b> in FIG. 4).

Next, the up counter 15 is counted up by the interrupt request signal, and the reset interrupt priority increment reference value and the value of the up counter 15 are compared by the comparator. Then, when the fixed period signal becomes active, the interrupt priority value is reset in the up counter 22 and the interrupt priority increment reference value (B1) is reset in the buffer 14 (FIG. 4C).

As described above, the basic operation is as shown in FIG.
The operations of <b> and <c> are repeated.

The operation shown in FIG. 4D is the same as the operation shown in FIG. 4B. Since the value of the up counter 15 and the set interrupt priority increment reference value match, the interrupt priority value is set to +1. To do. Further, the interrupt priority increment reference value (B2) is reset in the buffer 14.

The operation of FIG. 4E is the same as that of FIGS. 4B and 4D.
In the same operation as, the value of the up counter 15 and the set interrupt priority increment reference value match, so
Increment the interrupt priority value by 1. + In the operation of Fig. 4 <d>
Together with 1, the total interrupt priority value is +2.
Also, the interrupt priority increment reference value (B3) is reset in the buffer 14.

The operation shown in FIG. 4F is the same as the operation shown in FIG. 4C, and the constant period signal becomes active.
The interrupt priority value is stored in the up counter 22 and the buffer 1
4 is reset to the interrupt priority increment reference value (B1).

As described above, in each of the above-described embodiments, in order to raise the interrupt priority by the number of interrupt occurrences, it is only necessary to write the interrupt priority increment reference value in the increment cycle setting register 11. The load on the CPU is lightened. Further, since it is prepared for each interrupt factor, it is not necessary to store the number of interrupt occurrences in the memory, so the memory can be saved.

[0034]

As described above, according to the present invention, it is possible to reduce the load on the CPU for counting the number of interrupt occurrences and to eliminate the memory for the number of interrupt factors.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an interrupt priority level setting circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing an operation timing of the circuit shown in FIG.

FIG. 3 is a diagram showing a configuration of an interrupt priority level setting circuit according to an embodiment of the invention as set forth in claim 3;

FIG. 4 is a diagram showing an operation timing of the circuit shown in FIG.

[Explanation of symbols]

 1 Interrupt priority change block 2 Interrupt priority setting block 11 Increment reference value setting register 12 Down counter 13, 17 OR circuit 14 Buffer 15, 22 Up counter 16 Comparator 21 Interrupt priority setting register

Claims (4)

[Claims] 1. A change threshold for changing the interrupt priority is set externally every fixed period or each time a change signal is output, and the number of interrupt requests generated within a fixed period is counted. Then, the changing means that outputs a change signal when the count value reaches the changing threshold, and the initial value of the interrupt priority order is set at regular intervals, and the priority set according to the changing signal output from the changing means. An interrupt priority setting circuit, comprising: setting means for changing and resetting the order. 2. The changing means recognizes that the number of interrupt requests has reached the change threshold value by decreasing the set change threshold value each time an interrupt request signal is input. The interrupt priority setting circuit according to claim 1, 3. The changing means recognizes that the number of interrupt requests has reached the change threshold because the count value of the number of interrupt requests and the change threshold are compared and both are equal. The interrupt priority level setting circuit according to claim 1, wherein: 4. The change threshold is alternatively selected from a plurality of change thresholds according to an external environment of a target to which a process for generating an interrupt request is performed. The interrupt priority setting circuit according to claim 1, 2, or 3.