JPH07181916A - Driving circuit of display device - Google Patents

Abstract

PURPOSE:To obtain a wider dynamic range with a small number of gradations. CONSTITUTION:The driving circuit of display device is equipped with a shift register 8a and a latch circuit 8b which convert K bits of M-bit (M=K+L) pixel data inputted as digital data of a serial signal into a parallel signal by horizontal lines, a comparison part 8c and a gate part 8e which impose pulse- width-modulate the image data converted into the parallel signal, a ROM 8g which stores correction data corresponding to the value of L bits of the pixel data, a high voltage selection part 8h which selects and outputs a voltage value for the pulse amplitude modulation according to the correction data in the ROM 8g, and a high-voltage buffer 8f which imposes pulse-amplitude-modulates the pulse-width-modulated pixel data with the voltage value selected by the high voltage selection part 8h.

Description

Detailed Description of the Invention

[0001]

The present invention relates to, for example, a television receiver, a personal computer, a medical device, a measuring instrument, a P
The present invention relates to a drive circuit of a field emission type light emitting element used in a display device of an information terminal such as an OS (Point Of Sales) system.

[0002]

2. Description of the Related Art An addressing method of a field emission display (FED ... Field Emission Display) constructed by a flat surface emission type field emission cathode (FEC) is an emitter and a gate electrode of a field emission device. In the XY matrix structure in which are wired in a matrix, general sequential scanning is performed.

6 (a) and 6 (b) show an example of the FEC called the Spindt type. (A) of this figure is a perspective view of an FEC created using a semiconductor processing technique, and (b) is a view showing a cross section of the FEC taken along the line AA shown in (a). In these figures, a cathode electrode formed of a metal such as aluminum is provided on a substrate, and a cone-shaped emitter is formed on the cathode electrode. Further on the cathode electrode, S _i O ₂ film gate through - and the gate electrode is provided, the emitter into Hirakiana opened in the gate electrode is to be positioned. That is, the tip of the cone-shaped emitter faces through the hole formed in the gate electrode.

The pitch between the cone-shaped emitters is 10
Since it can be set to a micron or less, it is tens of thousands to tens.
Ten thousand FECs can be provided on one substrate. Further, since the distance between the gate electrode and the tip of the cone of the emitter can be made submicron, by applying a voltage of only several tens of volts between the gate electrode and the cathode electrode, electrons are emitted from the emitter by field emission. You can do it. Since this FEC has a planar shape as shown in the figure, it can be used as a surface emission type field emission cathode, and an FED can be formed by using such a surface emission type field emission cathode. Can be built.

FIG. 7 is a perspective view showing the structure of such an FED. In this FED, 21 indicates a first substrate arranged in a vacuum container, and y1 to yn formed in stripes on the first substrate 21 indicate cathode electrodes as Y electrodes. This cathode electrode y1
Cathode terminals CT1 to CTn to which a drive pulse described later is supplied are connected to yn.

Further, x1 to xm are gate electrodes as X electrodes, and are formed in stripes on the cathode electrodes y1 to yn so as to be orthogonal to the cathode electrodes y1 to yn via an insulator. And the gate electrodes x1 to xm
Drive pulses are supplied to the gate terminals G1 to Gm
Are connected. Reference numeral 22 is a hole formed in each of the gate electrodes x1 to xm, which is formed for passing electrons emitted from the cone-shaped emitter (see FIG. 6) formed on the cathode electrodes y1 to yn. It is a thing.

Reference numeral 23 denotes a second substrate which is arranged in the vacuum container so as to face the first substrate 21. Then, 24, 24 ... Formed on the second substrate 23.
.. is the anode electrode, and the gate electrode x1 as shown
They are arranged in stripes corresponding to the positions of ~ xm.
An anode lead electrode A is connected to each anode electrode 24. In the case of a color display, the anode extraction electrode A has three components R, G, and B.
Three will be extracted corresponding to the primary colors. Reference numeral 25 denotes a phosphor, which is a gate electrode x1 to
It is provided on the surface opposite to xm and is excited by the collision of electrons.

Therefore, an example of a driving method for displaying an image by the FED will be schematically described. The anode electrode 24 formed on the second substrate 23 is supplied with a substantially constant voltage by the anode extraction electrode A. On the other hand, the cathode electrodes (Y electrodes) y1 to yn are sequentially selected and driven by the stripe-shaped cathode electrodes being sequentially selected by supplying scanning pulses to the respective cathode terminals CT1 to CTn and scanning.

Therefore, the cathode terminals CT1 to CTn are sequentially scanned with a positive anode voltage being applied to the anode extraction electrode A for driving the anode electrode 24. At this time, when a voltage according to the data of the image signal is applied to the gate terminals G1 to Gm according to the scanning timing, the gate electrodes x1 to xm and the cathode electrodes y1 to yn are applied.
The pixels of the phosphor 25 provided on the anode electrode 24 are scanned by the electrons emitted from the FEC block located at the intersection of, and the emission control of the pixels is performed according to the voltage applied to the gate terminals G1 to Gm. Thus, one screen (one field) of the image is displayed in this manner.

By the way, a method of performing gradation control for adjusting the degree of lightness or darkness or lightness in the image display is PWM (pulse width modulation) for controlling the application time of the drive pulse applied to the gate terminals G1 to Gm. ) Drive system,
There is a PAM (Pulse Amplitude Modulation) driving method that controls the voltage value of the driving pulse applied to the gate terminals G1 to Gm.
In the PWM drive method, gradation is controlled by controlling the pulse width tw of the waveform of the drive voltage as shown in FIGS. 8A, 8B, and 8C, for example. FIG. 9 is a diagram schematically showing the light amount when the number of gradations is 16, for example, and the pulse voltage value HVcc is shown along the vertical axis and the pulse width is shown along the horizontal axis. Sp represents the light amount determined by the voltage value HVcc and the 16-step pulse width 0, 1 / 15tw, 2 / 15tw, ... tw.

The pulse width tw shown in FIG.
Corresponds to 1 / 15tw shown in FIG. 9, for example,
As the pulse width tw expands as shown in (b), it becomes 2/1.
5tw, 3 / 15tw, ... 14 / 15tw, the light amount Sp also increases, and the gradation has the highest brightness with the pulse width tw shown in (c).

Further, the PAM drive system is, for example, as shown in FIG.
As shown in (a), (b) and (c), the voltage value HVc
The gradation is controlled by controlling c. FIG. 11 is a diagram schematically showing the light amount when the number of gradations is 16, for example, as in FIG. In this figure, Sv is 16 steps of voltage value 0, 1 / 15HVcc, 2 / 15HVcc, ... HV
The amount of light determined by cc and the pulse width tw is shown. Figure 10
The voltage value HVcc shown in FIG.
Corresponding to 1/15 HVcc shown in (2), and as the voltage value HVcc increases as shown in (b), 2/15 HVcc
cc, 3 / 15HVcc, ... 14 / 15HVcc, the light quantity Sv also increases,
As shown in (c), the gradation has the highest luminance at the voltage value HVcc.

[0013]

By the way, in the Spindt type FEC as shown in FIG. 6, the mutual conductance is large, and the electron flow emitted is exponentially proportional to the driving voltage. Due to (difference in the value indicating the performance of the element depending on the process), the light emission brightness differs greatly for each dot even when driven with the same drive voltage, causing uneven brightness of the screen light emission and accurate gradation expression. Can be difficult. It has been pointed out that the gradation display by the PWM driving method described above has an increase in power consumption due to high-speed switching, but the luminance modulation linearity does not deteriorate. On the other hand, in the PAM drive system, the operating point is F
In order to move on the I / V (I = emission current, V = driving voltage ... potential difference between cathode and emitter) characteristic curve of the EC element, the characteristics of the FEC element must be the same for each dot. However, since the brightness modulation linearity deteriorates, there is a problem that uneven brightness is more likely to be promoted than in the PWM drive method. Further, the correction of the variation in the element characteristics can be performed as the actual display data by performing the correction calculation of the image data based on the brightness data of each dot measured in advance, but the display data with the low emission brightness is obtained by the PWM drive method. Therefore, the number of gray scales that can be displayed is reduced by the correction, resulting in an image with a low dynamic range.

Further, even when performing the variation correction, the variation characteristics differ depending on the model, and when performing the suitable variation correction corresponding to each model, it is necessary to take measures such as changing the number of gradations. It was difficult to make such corrections.

[0015]

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and it is possible to convert from K pixel data to M bit (M = K + L) pixel data input as image data.
A pulse width modulation means for pulse width modulating a bit, a memory for storing correction data corresponding to the value of the L bit of the image data for correcting the light emission characteristics of the display device, and a correction data corresponding to the memory. High voltage selecting means for selecting and outputting a voltage value and pulse amplitude modulating means for pulse amplitude modulating the pulse signal pulse width modulated by the pulse width modulating means with the voltage value selected by the high voltage selecting means. The field emission device is scanned with a signal output from the pulse amplitude modulation means to display an image. The pulse width modulated signal is added to the gate voltage of the field emission device.

[0016]

By using the PAM driving method and the PWM driving method together as the gradation driving method, a wider dynamic range can be realized with a small number of gradations. In particular, amplitude-modulated data can be used to correct variations in FEC characteristics.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the drive circuit for a field emission device according to the present invention will be described below with reference to FIGS. First, Fig. 1
The circuit configuration of a display device using the FED is shown in FIG. In this figure, 1 is an FED, and an FED having the same configuration as that shown in FIG. 8 is used. In this figure, the anode electrode 24 (and the phosphor 2
5) and the anode extraction electrode A are not shown, but the anode electrode 24 is supposed to be arranged on the gate electrodes x1 to xm, and the anode extraction electrode A is connected to an anode driver 9 described later. To be taken.
For the sake of convenience, the cathode electrodes y1 to yn will be unified as Y electrodes, and the gate electrodes x1 to xm will be unified as X electrodes.

Reference numeral 2 denotes an image input terminal to which an image data signal is input. An image input circuit 3 transmits, for example, data necessary for controlling image display to the CPU 4 based on an image data signal supplied from the image input terminal 2, and
It performs operations such as outputting image data for controlling the X scan driver 8 and the Y scan driver 6 to the driver controller 5. Reference numeral 4 denotes a CPU that performs processing such as control relating to image display scanning, which will be described later. A driver controller 5 controls the application timing of the scan voltage of the Y scan driver 6 and the application timing of the signal according to the image data of the X scan driver 8 according to the image data from the image input circuit 3 and the control timing by the CPU 4. . In this case, the voltage application timing of the anode driver 9 is also controlled.

Reference numeral 6 denotes a Y scan driver, which has cathode terminals CT1 to CT1 corresponding to the Y electrodes (y1 to yn) at predetermined timing under the control of the driver controller 5 described above.
The scan voltage is output to CTn.

Reference numeral 8 denotes an X scan driver, and in this case, the gate terminal G1 corresponding to each X electrode (x1 to xm) at a predetermined timing under the control of the driver controller 5.
The voltage corresponding to the image data is output to Gm.

Reference numeral 9 denotes an anode driver, which is actually FE
It is connected to the anode lead electrode A of D1. Then, according to the control of the driver controller 5, a positive anode voltage for driving the anode electrode 24 is output at a predetermined timing. It should be noted that this anode driver can be omitted when the anode electrode is configured in beta (black and white image).

Next, the PAM drive system and P in this embodiment
The gradation control using the WM drive method together will be described. FIG. 2 is a diagram showing the configuration of the X scan driver 8 shown in FIG. In the figure, 8a indicates a shift register for storing pixel data input as serial data for one horizontal line. If the number of bits of the data length of one pixel in the serial data is M (M = K + L) bits, K-bit data for PWM driving is input to the shift register 8a, and the remaining L bits are for PAM driving. Is input to the high voltage selection unit 8h described later. In this embodiment, for example, K = 4 bits and L = 2 bits will be described.

Reference numeral 8b denotes a latch circuit, which serial-parallel converts the K-bit pixel data by the shift register 8a and holds the data for one horizontal period. Reference numeral 8c is a comparison unit composed of a plurality of comparators 8c1, 8c2, ... 8cm, and compares each pixel data input from the latch circuit 8b with the output of a K-bit counter 8d that counts a gradation clock. When the measured values match, the signals output from the comparators 8c (1, 2, 3, ..., M) are supplied to the gate unit 8e.

The gate section 8e forms a gate signal having a pulse width which is the time until the coincidence signal is output after the K-bit counter 8d is cleared, and supplies this gate signal to the high voltage buffer section 8f. . The high voltage buffer section 8f includes a plurality of buffer amplifiers 8f1, 8f2, 8f3 ... 8 which are switching-controlled by the gate signal.
This buffer amplifier 8f (1,2,3, ... m) equipped with fm
Is supplied to each X electrode. 8g is a ROM table (or RAM table) in which data for setting the voltage value supplied to the high voltage buffer section 8f is stored
Further, for example, the voltage of the value designated by the ROM table 8g read out by the L-bit data is supplied to the high voltage buffer unit 8f via the high voltage selection unit 8h. The L-bit data may be directly converted into a voltage value by the A / D converter. Then, the high voltage selection unit 8h selects the voltage value output by the L-bit data of the pixel data input as the serial data, and each buffer amplifier 8f (1, 2, 3, ...) Of the high voltage buffer unit 8f. ····· m) It will be supplied as a drive voltage.

By providing circuits corresponding to the shift register 8a, the latch circuit 8b, and the comparison unit 8c in the high voltage selection unit 8h as well, a high voltage corresponding to L bits is selected and the horizontal direction is selected. The drive voltage to be corrected is applied to each of the pixels arranged in line.

The operation of each of the above functional circuits will be described below with reference to the clocks and output data waveforms shown in FIGS. 3 (a) to 3 (h). The image data of one horizontal line is sequentially stored in the shift register 8a by the shift clock (c) as 4 bits of serial data (e) of one pixel composed of 6 bits. Image data for one horizontal line, for example 320 pixels, is latched as parallel data by the latch signal in the latch circuit 8b. Then, the parallel data for each horizontal line is output to the comparison unit 8c. The comparator 8c compares the output data (4 bits) of the latch circuit 8b with the count value of the K-bit counter 8d. The K-bit counter 8d is initialized by the rising edge of the clear clock (a) and then counted up. When the count data value and the output data value of the latch circuit 8b match, the comparators 8c1, 8c2, ... Output data is output via the gate circuit 8e. That is, the output data of the comparison unit 8c is the drive pulse application time (pulse width), and the gradation application time is controlled by the PWM modulation by the comparison unit 8c and the gate circuit 8e.

On the other hand, the L-bit data of the data of one pixel is also sequentially input to the high-voltage selecting section 8h for one horizontal line. The high voltage selection unit 8h uses the ROM 8 for each image to obtain the voltage value as the gradation voltage corresponding to the 2-bit data.
It is selected based on the data of g and is supplied so as to become the drive voltage of each buffer amplifier 8f (1, 2, 3, ..., M) of the high voltage buffer section 8f. The L-bit data is mainly data for correcting the display characteristics (light emission characteristics) of the FED, and for example, the lower L bits of M bits are assigned.
Then, as will be described later, display unevenness on the image surface, gamma characteristics, etc. are corrected by the L-bit data.

In this way, the gradation voltage value selected by the high voltage selection unit 8h, the comparison unit 8b and the gate circuit 8e.
The application time (pulse width) obtained by controlling the buffer amplifiers of the high-voltage buffer 8f at the same time is as shown in FIG.
The drive pulse is formed with the waveforms shown in (f), (g), and (h). (F) shows that the voltage value is V1 and the pulse width is W1 in the drive pulse for driving a certain eleventh pixel, for example. Further, (g) is a drive pulse for driving a certain pixel, for example, the 23rd pixel, having a voltage value of V2 and a pulse width of W2. Similarly, (h) shows one waveform example of a drive pulse for driving the 3Fth image, for example, and shows that the voltage value is V3 and the pulse width is W3. In the case of the present invention, as described above, the drive pulse is obtained by using the PWM modulation and the PAM modulation together, so that the gradation drive is performed by the drive pulse having the different voltage level V and the application time W for each pixel on the horizontal line. Will be able to.

FIG. 4 is a diagram schematically showing an example of a change in the light amount in the case of gradation driving in 16 steps, for example, by driving pulses obtained by PWM modulation and PAM modulation. The application time is shown, and the amount of light obtained from this voltage level and the application time is shown by Spv. The number of gradation steps shown in this figure is also 16 as in the case described with reference to FIGS. 9 and 11, but since the gradation voltage value and the application time can be controlled simultaneously, PWM modulation and PAM modulation are performed respectively. The dynamic range of the light amount becomes wider than in the case of Further, since the voltage value selection data stored in the ROM 8g can be arbitrarily set, it is possible to simultaneously correct variations in the element characteristics of the FEC without changing the setting of the number of gradations.

In particular, by setting the gradation voltage value arbitrarily in consideration of the contrast characteristic of the monitor image, for example, the curves A (γ = 1) and B (γ =) shown in FIG.
2), luminance modulation characteristics (gamma correction) such as C (γ = 0.5) can be arbitrarily set, and high-quality image display can be achieved even in a monitor device such as a television receiver. You will be able to do it.

In the above embodiment, the ROM table is used to output the voltage corresponding to the correction data. However, the L-bit image data is converted into the voltage value to directly perform the pulse amplitude modulation. Good.

[0032]

As described above, the drive circuit of the field emission device according to the present invention controls the voltage value of the drive pulse and the application time (pulse width) by simultaneously performing the PWM gradation control and the PAM gradation control. Therefore, even when expressing the same number of gradations, it is possible to reduce the number of division steps of the applied pulse width and the voltage value as compared with the conventional case. Particularly, since the drive voltage can be set by a part of the image data, for example, the FEC
Even if there are variations in device characteristics such as
By forming a ROM table corresponding to the variation between the display devices using EC, there is an effect that the light emission characteristics of the display device can be made uniform. Further, similarly, the brightness modulation characteristic (gamma correction) can be arbitrarily set, so that a high-quality image display can be performed as a monitor device such as a television receiver.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit block of a display device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a circuit block of an X scan driver in the display device of the present embodiment.

FIG. 3 is a diagram showing waveforms of various clocks and output data in the X scan driver.

FIG. 4 is a diagram schematically showing a change in light amount due to gradation driving according to the present embodiment.

FIG. 5 is a diagram showing an example of gamma correction that can be set in this embodiment.

FIG. 6 is a perspective view and a cross-sectional view showing a Spindt type field emission cathode.

FIG. 7 is a diagram showing a configuration of a field emission display.

[Explanation of symbols]

 1 tablet 6 Y scan driver 8 X scan driver 8a shift register 8b latch circuit 8c comparison unit 8d K bit counter 8e gate unit 8f high voltage buffer 8g ROM 8h high voltage selection unit 8i amplifier unit

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[Procedure amendment]

[Submission date] June 17, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit block of a display device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a circuit block of an X scan driver in the display device of the present embodiment.

FIG. 3 is a diagram showing waveforms of various clocks and output data in the X scan driver.

FIG. 4 is a diagram schematically showing a change in light amount due to gradation driving according to the present embodiment.

FIG. 5 is a diagram showing an example of gamma correction that can be set in this embodiment.

FIG. 6 is a perspective view and a cross-sectional view showing a Spindt type field emission cathode.

FIG. 7 is a diagram showing a configuration of a field emission display.

FIG. 8 is a drive voltage when gradation control is performed by a PWM drive method.
It is a figure which shows the pulse width of pressure typically.

9 is a relationship between the pulse width of the drive voltage and the light amount shown in FIG.
FIG.

FIG. 10: Driving when gradation control is performed by PAM driving method
It is a figure which shows the voltage value of voltage typically.

11 is a diagram showing the relationship between the voltage value of the drive voltage and the light amount shown in FIG.
It is a figure which shows a person in charge.

[Explanation of Codes] 1 tablet 6 Y scan driver 8 X scan driver 8a shift register 8b latch circuit 8c comparison unit 8d K bit counter 8e gate unit 8f high voltage buffer 8g ROM 8h high voltage selection unit 8i amplifier unit

Claims (3)

[Claims] 1. A pulse width modulation means for pulse-width modulating K bits from M-bit (M = K + L) pixel data input as image data, and L of the image data for correcting light emission characteristics of a display device. Voltage selecting means for selecting and outputting a voltage value corresponding to the bit value; pulse amplitude for pulse-amplitude modulating the pulse signal pulse-width modulated by the pulse width modulating means with the voltage value selected by the voltage selecting means. A drive circuit of a display device, comprising: a modulation unit, wherein the field emission device is controlled by a signal output from the pulse amplitude modulation unit to display an image. 2. The drive circuit of a display device according to claim 1, wherein the pulse width modulated signal is applied to a gate electrode of a field emission device. 3. The drive circuit for a display device according to claim 1, wherein the voltage selection means is composed of an A / D converter.