JPH07177058A - Synchronous tracking circuit for spread spectrum communication - Google Patents

Abstract

PURPOSE:To reduce the number of parts used for a high frequency band in the synchronous tracking circuit for spread spectrum of the tau-dither system. CONSTITUTION:The same PN code sequence Pr which is included in a spread reception signal Sr is outputted from a PN code sequence generator 10. A phase control circuit 16 alternately outputs PN code sequences Pe and Pl, which are obtained by shifting the phase of the sequence Pr by minute extents +tau/2 and -tau/2, synchronously with a control signal Sc of a square wave. A correlator 28 subjects the spread reception signal Sr to down conversion and inverse spreading. A multiplier 24 multiplies the PN code sequence Pe or Pl and the sequence Pr. A correlator 18 obtains correlations between the output of this multiplication and the output of the correlator 28. A multiplier 19 multiplies the output of the correlator 18 and the control signal Sc. The output or this multiplication is inputted to a VCO 12 through an LPF 20 to control the clock frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to so-called tau after synchronization of a received signal in a spread spectrum communication system.
Regarding a circuit for synchronous tracking by a dither method, the number of elements used in a high frequency band is reduced, which enables cost reduction and circuit integration.

[0002]

2. Description of the Related Art A spread spectrum communication system has been conventionally known. There, a carrier whose spectrum is spread by a binary PN code (pseudo noise code) sequence having a spectrum width sufficiently wider than that of an information signal is transmitted,
The receiving side demodulates the original information signal by detecting the received signal with the same PN code sequence as that used on the transmitting side.

In such a spread spectrum communication system, in order to accurately demodulate an information signal, the receiving side PN code sequence generated at the receiving side must be synchronized with the transmitting side PN code sequence. This synchronization sequence is divided into synchronization acquisition (initial pull-in) and synchronization holding (tracking), and various methods have been proposed conventionally.

As a method of synchronous tracking, tau dither (t
au-dither) method. A principle diagram of the tau dither method is shown in FIG. From the PN code sequence generator 10,
The PN code sequence Pr is generated in synchronization with the oscillation clock of the VCO (voltage controlled oscillator) 12. Control signal generator 1
4 outputs a control signal Sc having a square wave whose half cycle has a length that is an integral multiple of the entire PN code sequence Pr and whose amplitude changes by ± e. The phase control circuit 16 outputs a PN signal according to the levels + e and −e of the control signal Sc, which change alternately.
Small amount of code sequence Pr within 1 chip + τ / 2, -τ /
2 By controlling the phase shift, +
The PN code sequence Pe advanced by τ / 2 and the PN code sequence Pl delayed by -τ / 2 with respect to the PN code sequence Pr are alternately output every half cycle of the control signal Sc.

The correlator 18 is a PN code sequence Pe and Pl alternately output from the input PN code sequence and the phase control circuit 16.
Find the correlation with. The correlation output is multiplied by the control signal Sc in the multiplier 19, the multiplication output is filtered by the loop filter 20 and then input to the VCO 12 to control its clock frequency.

The operation of the circuit of FIG. 2 will be described with reference to FIGS. FIG. 3 shows the PN code sequence P for the input PN code sequence.
This is the state when the phases of e and Pl are both delayed. At this time, the correlation output X (Pe) for the PN code sequence Pe
And the correlation output X (Pl) for the PN code sequence Pl are as shown in FIG. 3 (b), where X (Pe)> X
(Pl). FIG. 4 shows P for the input PN code sequence.
This is the state when the phases of the N code sequences Pe and Pl are both advanced. At this time, the correlation output X (Pe) for the PN code sequence Pe and the correlation output X for the PN code sequence Pl
The relationship with (Pl) is as shown in FIG.
(Pe) <X (Pl).

As a result, the waveform of each part in FIG. 2 becomes as shown in FIG. That is, when the PN code sequences Pe and Pl are both delayed with respect to the input PN code sequence, the correlation output of the correlator 18 becomes as shown by (a) in FIG. When the control signal Sc of (A) is multiplied by, the multiplication output of (C) is obtained. The multiplication output is averaged by the loop filter 20 to give a positive value. By applying this positive output to the VCO 12, the clock frequency is increased and the phase of the PN code sequences Pe and Pl is advanced. Further, when the PN code sequences Pe and Pl are both advanced with respect to the input PN code sequence, the correlation output of the correlator 18 becomes as shown by (a) in FIG. When the control signal Sc of (A) is multiplied by,
The multiplication output of (c) is obtained. The multiplication output is averaged by the loop filter 20 to give a negative value. By applying this negative output to the VCO 12, the clock frequency is lowered and the phases of the PN code sequences Pe and Pl are delayed. By such control, X (Pe) = X (Pl), that is, PN is applied to the input PN code sequence.
The code sequences Pe and Pl are drawn so as to be in the state shown in FIG.

Next, FIG. 7 shows a conventional synchronization tracking circuit for spread spectrum communication using the above-mentioned tau dither method. This constitutes a heterodyne type synchronization tracking circuit for spread spectrum communication. Spread reception signal Sr
Is a signal spread by the direct spreading method, and is modulated by a carrier wave of frequency fc. The frequency is f from the local oscillator 22.
A local oscillation signal Sl of c + fi (fi: intermediate frequency) is output. From the PN code generator 10, the PN code sequence Pr
Is output. This PN code sequence Pr is the phase control circuit 1
6, the phase shift control is performed by the square wave control signal Sc, and Pr
The PN code sequence Pl delayed by -Tc / 2 and the PN code sequence Pe advanced + Tc / 2 with respect to Pr are alternately output at a predetermined cycle.

The multiplier 24 multiplies the PN code sequences Pe and Pl alternately output with the local oscillation signal Sl. The correlator 18 down-converts the carrier of the spread reception signal Sr to the intermediate frequency fi and multiplies the spread reception signal Sr by multiplying the multiplied output by the spread reception signal Sr.
Is despread with the PN code sequences Pe and Pl. The output of the correlator 18 is multiplied by the control signal Sc in the multiplier 19, and the multiplied output is filtered by the loop filter 20 and then the VCO 12
Input to control the clock frequency. As a result, this control loop locks in the state shown in FIG. 6 (the PN code sequence Pr locks the input PN code sequence with a phase difference of 0), and synchronization tracking is realized.

The multiplier 26 multiplies the local oscillation signal Sl by the PN code sequence Pr. The correlator 28 down-converts the carrier of the spread reception signal Sr to the intermediate frequency fi and despreads the spread reception signal Sr with the PN code sequence Pr by multiplying the multiplied output and the spread reception signal Sr. Since the PN code sequence Pr is locked to the input PN code sequence with a phase difference of 0, the correlation output of the correlator 28 is output at the maximum level. The correlation output of the correlator 28 is the bandpass filter 3 having the intermediate frequency fi as the center frequency.
After being filtered by 0, it is input to the demodulator 32 and the received information is demodulated.

[0011]

Generally, the carrier frequency fc of the spread reception signal Sr in FIG. 7 is 100M to 300MHz.
Often set to a high frequency. Therefore, the local oscillation frequency fc + fi is also a high frequency of the same level. Therefore, in the circuit of FIG. 7, the multipliers 24 and 26 and the correlators 18 and 28 use this high frequency band. In general, electronic components tend to become more expensive as the frequency handled increases, so the circuit configuration of FIG. 7 has the drawback of high cost. Further, it has been quite difficult to form a component handling a frequency of 100 MHz band by an integrated circuit such as an LSI.

The present invention solves the above-mentioned problems in the prior art, reduces the number of parts used in a high frequency band, and enables cost reduction and circuit integration, and a tau dither system spread spectrum. It is intended to provide a synchronization tracking circuit for communication.

[0013]

The invention according to claim 1 is
Variable clock generating means for generating a clock signal with variable frequency, PN code sequence generating means for generating a PN code sequence in synchronization with this clock signal, down-converting a spread reception signal with a local oscillation signal, and said PN code Down-conversion and de-spreading means for despreading using a sequence to output a demodulation signal, and a control signal for outputting as a control signal a square wave signal having a half cycle longer than one cycle of the entire PN code series. Generating means, phase control means for changing and outputting the phase of the PN code sequence within one chip in accordance with the alternating signal level of the control signal, and PN code sequence generated from the phase control means. And a multiplication means for multiplying the PN code sequence used for the despreading, a multiplication output of the multiplication means, the down-conversion and despreading means. Correlation means for obtaining a correlation with the output of, the amplitude modulation means for amplitude-modulating the output of the correlation means according to the alternating signal level of the control signal, and the correlation output from the down-conversion and despreading means. Clock signal frequency control means for controlling the frequency of the clock signal generated from the variable clock generation means according to the average value of the output of the amplitude modulation means so that the output shows a value close to its peak value. It will be.

The invention according to claim 2 is characterized in that at least the multiplication means and the correlation means are constructed on an integrated circuit.

[0015]

According to the invention described in claim 1, the multiplication means is PN.
Since the code sequence is handled and the correlating means handles the frequency obtained by down-converting the carrier wave, it is possible to use components for a relatively low frequency band, and the cost can be reduced. Further, it can be integrated in an LSI or the like as in the invention described in claim 2.

[0016]

FIG. 1 shows an embodiment of the present invention. The spread reception signal Sr is a signal spread by the direct spread method and has a frequency f.
It is modulated with the carrier wave of c. The local oscillator 22 outputs a local oscillation signal Sl having a frequency of fc + fi (fi: intermediate frequency). VCO1 from the PN code generator 10
The same PN code sequence Pr as the input PN code sequence included in the spread reception signal Sr is output in synchronization with the 2 clock.

The multiplier 26 multiplies the local oscillation signal Sl by the PN code sequence Pr. The correlator 28 down-converts the carrier of the spread reception signal Sr to the intermediate frequency fi and despreads the spread reception signal Sr with the PN code sequence Pr by multiplying the multiplied output and the spread reception signal Sr.

The control signal generator 14 outputs a control signal Sc having a square wave whose half period is an integral multiple of the entire PN code sequence Pr and whose amplitude changes by ± e. . The phase control circuit 16 controls the phase shift of the PN code sequence Pr according to the signal level of the control signal Sc, and Pr
With respect to + Tc / 2 (Tc is a time for one chip), the PN code sequence Pe advanced and -Tc / 2 delayed PN code sequence P
1 is alternately output in a predetermined cycle. The multiplier 24 multiplies the PN code sequence Pr and the PN code sequences Pe and Pl. The correlator 18 obtains these correlations by multiplying the multiplication output and the correlation output of the correlator 28. Correlator 18
Is multiplied by the control signal Sc in the multiplier 19, and the multiplication output is filtered by the loop filter 20 and then VCO1.
2 to control its clock frequency.

An equation shows that the output of the correlator 18 is the same between the conventional circuit of FIG. 7 and the circuit of FIG. Here, the spread reception signal Sr = d (t) · Pt (t) · cos (2
πfc · t) 2πfc · t: carrier wave fi: intermediate frequency d (t): information data to be demodulated Pt (t): input (transmission side) PN code sequence Pl (t), Pr (t), Pe (t) : PN code sequence P
l, Pr, Pe. (1) In case of FIG. 7 Correlator 18 output = d (t) .Pt (t) .cos (2.pi.fc.t) .Pe (t) (or Pl (t)). Cos {2.pi. (fc + fi) .t } (1) (2) In the case of FIG. 1 Output of correlator 18 = d (t) .Pt (t) .cos (2.pi.fc.t) .Pr (t) .cos {2.pi. (fc + fi) .t}. Pr (t) · Pe (t) (or Pl (t)) (2) In equation (2), Pr (t) · Pr (t) is an autocorrelation function of the PN code sequence Pr, and m sequence PN. Because of the nature of the code sequence, Pr (t) · Pr (t) = 1, so by substituting this into equation (2), the output of correlator 18 = d (t) · Pt (t) · cos (2πfc・ T) ・ Pe (t) (or Pl (t)) ・ cos {2π (fc + fi) ・ t} (3) It is clear from the formulas (1) and (3). Thus, the output of the adder 18 is the same in FIGS. 1 and 7. In other words, in the circuit of FIG. 1, the PN code sequence Pr used for despreading in the correlator 28 for obtaining the demodulation signal is multiplied by the PN code sequences Pl and Pe for tau dither to be used for tau dither. Correlator 18
7 for despreading, the PN code sequence Pr is canceled by despreading in the correlator 18 and the correlator 18 outputs the PN code sequence Pr.
The same correlation output as is obtained. As a result, the control loop for tau dither in FIG. 1 is locked in the state shown in FIG. 6 (the PN code sequence Pr is locked in the input PN code sequence with a phase difference of 0), and synchronous tracking is realized. . Therefore, the correlation output of the correlator 28 is output at the maximum level.

In FIG. 1, the correlation output of the correlator 28 is
After being filtered by a bandpass filter 30 having an intermediate frequency fi as a center frequency, it is input to a demodulator 32, and the information data d (t) is demodulated.

According to the configuration of FIG. 1, since the multiplier 24 handles the PN code sequence and the correlator 18 handles the intermediate frequency fi, relatively inexpensive elements can be used, and these can be used in the LSI. Can be incorporated into (correlator 2
8, the multiplier 26, the local oscillator 22, and the bandpass filter 30 can be incorporated in the LSI. ).

[0022]

[Other Embodiments] In the above embodiment, three PN code sequences P are used.
Although I, Pr, and Pe are used, as shown in FIG. 8, the phase control circuit 16 outputs the PN code sequence Pr as it is instead of the PN code sequence Pl (or Pe), so that PN
The code sequence Pl can be omitted. In this case, the input PN
The code sequence and the PN code sequence Pr are locked in the state where a phase difference is generated (locked at an intermediate phase between Pr and Pe), but the phase difference between the PN code sequences Pr and Pe is Tc (time for one chip). If the following is done, the correlation output of the correlator 18 is
It is possible to secure a value of ½ or more of the peak value.

[0023]

As described above, according to the invention described in claim 1, since the multiplication means handles the PN code sequence and the correlation means handles the frequency obtained by down-converting the carrier wave, it is for a relatively low frequency band. Parts can be used and can be constructed at low cost. Further, it can be integrated in an LSI or the like as in the invention described in claim 2.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a principle diagram of tau dither synchronization tracking.

3 is an operation explanatory diagram of the circuit of FIG. 2 (when both Pe and Pl are delayed with respect to the input PN code sequence).

4 is an explanatory diagram of the operation of the circuit of FIG. 2 (when both Pe and Pl advance with respect to the input PN code sequence).

5 is a waveform diagram of each part of FIG.

FIG. 6 is an operation explanatory diagram of the circuit of FIG. 2 (when Pr is synchronized with a phase difference of 0 with respect to an input PN code sequence).

FIG. 7 is a block diagram showing a conventional synchronization tracking circuit for spread spectrum communication using the tau dither method.

FIG. 8 is a block diagram showing another embodiment of the present invention.

[Explanation of symbols]

10 PN Code Sequence Generator (PN Code Sequence Generating Means) 12 Voltage Controlled Oscillator (Variable Clock Generating Means) 18 Correlator (Correlation Means) 19 Multiplier (Amplitude Modulating Means) 20 Low Pass Filter (Clock Signal Frequency Control Means) 24 Multiplication 28 (multiplier means) Correlator (down-conversion and despreading means)

Claims (2)

[Claims] 1. A variable clock generating means for generating a clock signal with a variable frequency, and a P for generating a PN code sequence in synchronization with the clock signal.
N code sequence generation means, down conversion and despreading means for down-converting a spread reception signal with a local oscillation signal and despreading using the PN code sequence to output a demodulation signal, and a half cycle of the PN code Control signal generating means for outputting a square wave signal having a period longer than one period of the entire sequence as a control signal, and the phase of the PN code sequence within one chip according to the signal level of the control signal which alternates. A phase control means for changing and outputting the PN code sequence generated from the phase control means and a multiplication means for multiplying the PN code sequence used for the despreading; a multiplication output of the multiplication means and the down conversion and A correlating means for obtaining a correlation with the output of the despreading means, and an output of the correlating means depending on the alternating signal level of the control signal. Generated from the variable clock generating means in accordance with the average value of the output of the amplitude modulating means so that the correlation output output from the down converting and despreading means exhibits a value close to its peak value. Synchronization signal tracking circuit for spread spectrum communication, which comprises a clock signal frequency control means for controlling the frequency of the clock signal. 2. At least the multiplying means and the correlating means,
2. It is constructed on an integrated circuit.
A synchronization tracking circuit for spread spectrum communication as described.