JPH07175665A - Input/output interruption control circuit - Google Patents

Abstract

PURPOSE:To provide the input/output interruption control circuit for flexibly selecting an interruption destination processor by converting the value of an interruption vector with a table or the input/output interruption control circuit for relating the start and end of an input/output concerning the input/output interruption control circuit of an input/output controller at a multiprocessor system. CONSTITUTION:The input/output interruption control circuit for an input 7 output controller 2 is provided with an interruption vector converting table T to be written from each processor 1i and when input/output interruption is generated, the interruption vector showing an interruption source is read by a vector reading circuit 42 and converted by the interruption vector converting table T. Corresponding to that value, an interruption generating circuit 41 selects the processor at the interruption destination.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output interrupt control circuit for a channel controller in a multiprocessor system. In a multiprocessor system, which of a plurality of processors the I / O interrupt is transmitted to becomes a problem. It is required to make interrupt processing as efficient as possible.

[0002]

2. Description of the Related Art FIG. 3 is a conceptual diagram of the configuration of a conventional system. This is a multiprocessor system including a plurality of processors 11 to 1n, a plurality of input / output control devices (or adapters, controllers, etc.) 31 to 3m for controlling the input / output devices, and a channel control device 2. When the processor 1i issues an I / O command, the channel controller 2 informs the I / O controller 3j which controls the designated I / O device. When the input / output control device 3j and the input / output device end the instructed processing, the end is notified to the processor by the input / output interrupt. The input / output interrupt control circuit 4 of the channel control device 2 uses the information for distinguishing the input / output device that caused the interrupt by the vector read circuit 42, that is, the number set by the input / output control device 3j (this is called an interrupt vector v). ) Is read, and the interrupt generation circuit 41 causes an interrupt to an appropriate processor.

There are the following conventional I / O interrupt methods. When an I / O interrupt occurs, all processors are interrupted, and each processor analyzes the interrupt factor to determine whether or not the interrupt is relevant to itself. Limit the number of processors that accept I / O interrupts to one.
The read interrupt vector is used to specify the processor to interrupt.

[0004]

According to the method of the present invention, even a processor which does not need to interrupt is interrupted, so that the processing capacity of the system is lowered. This method does not have system flexibility. The interrupt processor becomes a bottleneck in the system, and the processing capacity of the system decreases.

In the method (1), since the interrupt destination processor (input / output device-input / output control device) has different interrupt destination processors and the interrupt processing is distributed, there is no drawback of the former two. Is fixed or semi-fixed and has a problem of lacking flexibility. That is, the source of the I / O interrupt is the I / O controllers 31 to 3m for I / O control connected to the bus of the channel controller 2, and the interrupt vector (vector number) v is This is because it is usually determined by the slot number of the inserted bus or a semi-fixed switch installed in the input / output control device.

The present invention provides an input / output interrupt control circuit that can flexibly select an interrupt destination processor by converting an interrupt vector value, or an input / output interrupt control circuit that associates activation and termination of input / output. It is intended to be realized.

[0007]

FIG. 1 is a block diagram of an embodiment of the present invention. The system shown in the figure is a multiprocessor system and comprises a plurality of processors 11 to 1n, a plurality of input / output control devices 3j for controlling the input / output devices, and a channel control device 2 for controlling them.

The input / output interrupt control circuit 4 of the channel controller 2 is provided with an interrupt vector conversion table T which can be written by each processor 1i. When an I / O interrupt occurs, the interrupt vector v indicating the interrupt source is read by the vector read circuit 42 and converted by the interrupt vector conversion table T, and the interrupt generation circuit 41 determines the interrupt destination processor according to the value. select. Each processor 1i can write an arbitrary value in the interrupt vector conversion table T as an interrupt destination.

A second aspect of the present invention is an interrupt vector when the channel controller 2 activates the input / output controller 3j in response to the processor 1i issuing an input / output operation start command to the input / output device. Input / output control device 3j for conversion table T
To the entry corresponding to the vector number v of
The write circuit 43 is configured to write the value 1i selected as the interrupt destination.

[0010]

The OS can freely set the interrupt destination processor by writing the contents of the interrupt vector conversion table T before issuing the input / output command. In the second invention, the contents of the interrupt vector conversion table T are written so that the processor that issued the command at the time of issuing the I / O command is designated as the interrupt destination, so that the processor that issued the I / O command must be used. The resulting I / O interrupt will be notified.

[0011]

Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram of an embodiment of the present invention. The channel controller 2 controls, for example, the VME bus (B). To the VMEbus (B), a VMEbus adapter 3j such as a LAN controller or SCSI interface controller corresponding to an input / output control device can be connected. VM
The housing frame of the E bus has, for example, 16 slots and is a VM.
It can accommodate up to 16 E-bus adapters. The VMEbus adapter 3j sets the slot number in which it is inserted to the vector number v
It is equipped with a circuit.

The input / output interrupt control circuit 4 of the channel controller 2 has an interrupt vector conversion table T, the contents of which can be written by an arbitrary processor 1i by a write circuit 43. The input / output interrupt control circuit 4 uses the vector read circuit 42 at the time of an input / output interrupt to send a VM through the VME bus.
Read the vector number v of the E-bus adapter 3j. Then, the interrupt generation circuit 41 converts the read vector number in the interrupt vector conversion table T, and selects the interrupt destination processor according to the value.

FIG. 2 shows the flow of processing. The processor writes the interrupt target processor number in the entry of the interrupt vector conversion table T. Then issue the command. The channel controller 2 transmits the command to the VMEbus adapter which controls the designated input / output device. VME
The bus adapter 3j executes the command and, when completed, causes an I / O interrupt. The input / output interrupt control circuit 4 of the channel controller 2 receives the interrupt vector (vector number) v from the adapter by the vector read circuit 42. The adapter sends the slot number as the interrupt vector v when the vector read circuit 42 reads the interrupt vector. The interrupt generation circuit 41 determines an interrupt destination processor based on the interrupt vector conversion table and causes an interrupt.

As an embodiment corresponding to the second invention, the input / output interrupt control circuit detects that a command is issued from the processor 1i, and the vector of the activated adapter in the'interrupt vector conversion table 'is detected. The number of the processor 1i can be written in the entry corresponding to the number. In this case, the OS does not need to write the entry of the interrupt vector conversion table T in advance.

[0015]

As described above, according to the first aspect of the present invention, in the multiprocessor system, the OS can flexibly determine the processor as the interrupt destination of the input / output interrupt. Therefore, an efficient system can be obtained.
Further, in the second invention, the resulting interrupt is automatically applied to the processor which started the input / output operation.
S does not need to take extra trouble.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment.

FIG. 2 is an explanatory diagram of a processing flow of the embodiment.

FIG. 3 is a conceptual diagram of the configuration of a conventional system.

[Explanation of symbols]

11 12 1i 1n Processor 2 channel controller 31 32 3i 3m I / O controller (I / O adapter) 4 I / O interrupt control circuit 41 Interrupt generation circuit 42 Vector read circuit 43 Write circuit T Interrupt vector conversion table v Included vector (vector number)

Claims (2)

[Claims] 1. An I / O interrupt control circuit of a channel controller (2) in a multiprocessor system is provided with an interrupt vector conversion table (T) which can be written from each processor (1i), and an I / O interrupt is provided. When an interrupt occurs, an interrupt vector (v) indicating an interrupt source is read, and an interrupt destination processor is selected according to a value converted by the interrupt vector conversion table (T). Output interrupt control circuit (4). 2. When the channel controller (2) activates the input / output controller (3j) in response to the processor (1i) issuing an input / output operation start command to the input / output device, I / O controller (3) of the built-in vector conversion table (T)
The input / output interrupt control according to claim 1, wherein the processor (1i) is configured to write a value selected as an interrupt destination into an entry corresponding to the interrupt vector (v) of j). Circuit (4).