JPH07174800A - Surface measuring instrument - Google Patents

Surface measuring instrument

Info

Publication number
JPH07174800A
JPH07174800A JP22922494A JP22922494A JPH07174800A JP H07174800 A JPH07174800 A JP H07174800A JP 22922494 A JP22922494 A JP 22922494A JP 22922494 A JP22922494 A JP 22922494A JP H07174800 A JPH07174800 A JP H07174800A
Authority
JP
Japan
Prior art keywords
electrode
measurement
gap
oxide film
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22922494A
Other languages
Japanese (ja)
Other versions
JP2682465B2 (en
Inventor
Shigeru Nishimatsu
茂 西松
Tatsumi Mizutani
巽 水谷
Kanji Tsujii
完次 辻井
Akira Haruta
亮 春田
Tadasuke Munakata
忠輔 棟方
Shigeyuki Hosoki
茂行 細木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP22922494A priority Critical patent/JP2682465B2/en
Publication of JPH07174800A publication Critical patent/JPH07174800A/en
Application granted granted Critical
Publication of JP2682465B2 publication Critical patent/JP2682465B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To prevent generation of leak current due to the contact of an electrode and accurately measure charge distribution by using an electrode where the air gap on a semiconductor surface can be varied and by measuring C-V (capacityvoltage) while applying voltage by changing the gap. CONSTITUTION:Silicon oxide film 2 is formed on silicon 1 and an electrode 3 is brought closer to the oxide film 2 by a variable mechanism 4 for measuring C-V characteristics. A rough-move mechanism by a micrometer and a fine-move mechanism by a piezoelectric actuator are provided at the movable mechanism 4 and capacity is measured and then the distance from the oxide film 2 is obtained. The electric field in the most of oxide film 2 exists M on the outermost surface of the interface with the silicon 1 and is nearly uniformly distributed in the film 2. Therefore, by changing gap and performing C-V measurement at three points, each electric charge can be measured. Also, when electric charge is properly distributed, C-V measurement is performed for many times by changing gap. Then, when data are analyzed by a CPU, the electric charge distribution in the film 2 can be estimated without any destruction.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体表面計測に係り、
特に半導体と絶縁物界面の界面準位密度や、絶縁膜中の
電荷およびその分布等を測定するに好適な計測方法およ
び装置に関する。
The present invention relates to semiconductor surface measurement,
In particular, the present invention relates to a measuring method and apparatus suitable for measuring the interface state density of the interface between a semiconductor and an insulator, and the charge and its distribution in an insulating film.

【0002】[0002]

【従来の技術】従来の半導体表面測定法として代表的な
ものに容量−電圧(C−V)特性を求める方法がある。
C−V測定には高周波(1MHz)法、低周波法、ケイ
サイスタティック(quasi-static)法等がある。これは
通常は図2に示したように、半導体基板1の上に絶縁物
2を形成し、その上に蒸着や化学気相成長(CVD)法
で金属や多結晶シリコン等の電極3を形成し、いわゆる
金属−酸化物−半導体のMOS構造としてC−V特性を
求めた。また簡便な方法として、図3に示したように絶
縁物上に水銀やインジウム・ガリウム合金を乗せてMO
S構成としていた。
2. Description of the Related Art A typical method for measuring a semiconductor surface is a method for obtaining a capacitance-voltage (CV) characteristic.
The CV measurement includes a high frequency (1 MHz) method, a low frequency method, a quasi-static method and the like. Usually, as shown in FIG. 2, an insulator 2 is formed on a semiconductor substrate 1, and an electrode 3 made of metal or polycrystalline silicon is formed on the insulator 2 by vapor deposition or chemical vapor deposition (CVD). Then, CV characteristics were obtained as a so-called metal-oxide-semiconductor MOS structure. Further, as a simple method, as shown in FIG. 3, MO or a mercury or indium-gallium alloy is put on the insulator.
It had an S configuration.

【0003】また表面光起電圧測定は、ジャパニーズ・
アプライド・フィジックス,23(1984年)第14
51頁から第1461頁(Japanese Journal of Applie
d Physics, 23 (1984) PP1451-1461)に示される。これ
を図4に示す。すなわち、透明電極3”と半導体の間に
マイラーなどの透明絶縁物6を入れて、光8を照射して
行っていた。
The surface photovoltage is measured by Japanese
Applied Physics, 23 (1984) 14th
51 to 1461 (Japanese Journal of Applie
d Physics, 23 (1984) PP1451-1461). This is shown in FIG. That is, a transparent insulator 6 such as Mylar is placed between the transparent electrode 3 ″ and the semiconductor, and the light 8 is emitted.

【0004】[0004]

【発明が解決しようとする課題】上記従来技術のC−V
測定法では、電極が絶縁物と接触する場合には、絶縁物
の表面近くの情報、すなわち電荷分布を得ることが難し
かった。絶縁膜を少しずつ化学エッチ法等で除去してC
−V測定を行うことを繰り返して表面近くの情報を得て
いた。逆に図4のような形では、薄いスペーサーは得ら
れず、せいぜい数10μmの厚さのもので、後述するよ
うにシリコン酸化膜の厚さに換算して2μm以下になら
ないと、正確な表面計測はできない。
CV of the above-mentioned prior art
In the measurement method, when the electrode contacts the insulator, it was difficult to obtain information near the surface of the insulator, that is, the charge distribution. Remove the insulating film little by little by chemical etching, etc.
The information near the surface was obtained by repeating the -V measurement. On the contrary, in the shape as shown in FIG. 4, a thin spacer cannot be obtained, and the thickness is at most several tens of μm. If the thickness of the silicon oxide film does not become 2 μm or less as described later, an accurate surface can be obtained. It cannot be measured.

【0005】また半導体表面の絶縁膜が非常に薄い場合
には、電極を付けるとリーク電流が流れて、C−V特性
が正確に測定できないなどの問題があった。
When the insulating film on the surface of the semiconductor is very thin, a leak current flows when the electrode is attached, and the CV characteristic cannot be measured accurately.

【0006】本発明の目的はこれらの問題点を解決する
ことにある。
An object of the present invention is to solve these problems.

【0007】[0007]

【課題を解決するための手段】上記問題点は、半導体表
面とのエアギャップ可変の電極を設けることにより解決
される。すなわち絶縁物と空気のコンデンサーを直列に
した形で計測を行うことになる。空気の代りに乾燥した
窒素等の不活性ガス中あるいは真空であっても良い。
The above problems can be solved by providing an electrode having a variable air gap with the semiconductor surface. That is, the measurement is performed in the form of an insulator and an air condenser connected in series. Instead of air, an inert gas such as dry nitrogen or vacuum may be used.

【0008】半導体のドーピング量にもよるが、通常M
OS構造ではSiO2膜厚が1μm以下でC−V測定が
行われる。2μm以上になると電圧に対して容量がほと
んど変化しないためである。従って比誘電率(SiO2
で3.9)を考慮すると、エアギャップは0.5μm以下
にすることが望ましいことになる。
Depending on the doping amount of the semiconductor, it is usually M
In the OS structure, CV measurement is performed when the SiO 2 film thickness is 1 μm or less. This is because the capacitance hardly changes with voltage when the thickness is 2 μm or more. Therefore, the relative permittivity (SiO 2
3.9), it is desirable that the air gap be 0.5 μm or less.

【0009】本発明の要旨は、被計測物と電極との間に
電圧を印加する表面計測装置において、一つの前記被計
測物に対し、前記被計測物と前記電極との間の距離を複
数の異なる距離に保持し、それぞれの距離において前記
電圧を印加する手段を有することを特徴とする表面計測
装置にある。
The gist of the present invention is to provide a surface measuring device for applying a voltage between an object to be measured and an electrode, wherein a plurality of distances between the object to be measured and the electrode are set for one object to be measured. In the surface measuring device, the surface measuring device is provided with means for holding at different distances and applying the voltage at each distance.

【0010】[0010]

【作用】エアギャップ電極では、容量を測定することで
半導体表面からの距離を求めることができる。多くのS
iO2の中の電界は半導体(Si)との界面と最表面に
多く、膜中には少なくほぼ均一に分布する。従って、界
面と最表面にデルタ関数的に電荷があり、膜中には均一
分布と仮定すると、エアギャップ電極のギャップを変え
て3点でC−V測定することによりそれぞれの電荷を求
めることができる。また適当に電荷が分布している場合
でもギャップを変えて多くのC−V測定を行い、コンピ
ューターによるデータ解析で、非破壊で膜中の電荷分布
を求める(推測)することができる。
In the air gap electrode, the distance from the semiconductor surface can be obtained by measuring the capacitance. Many S
The electric field in iO 2 is large at the interface with the semiconductor (Si) and the outermost surface, and is small in the film and distributed almost uniformly. Therefore, assuming that there is a delta function electric charge at the interface and the outermost surface, and assuming a uniform distribution in the film, it is possible to obtain each electric charge by changing the gap of the air gap electrode and performing CV measurement at three points. it can. Even when the charge is appropriately distributed, a large number of CV measurements can be performed by changing the gap, and the charge distribution in the film can be determined (estimated) nondestructively by data analysis by a computer.

【0011】ケイサイスタテック(quasi-static)法で
C−V特性を求める場合等で絶縁膜にリークがあると正
確な測定ができないが、本法では必ずギャップがあるか
ら、トンネル電流や放電が起らない限り、非常に薄い絶
縁物の場合でもC−V測定を行うことができる。
Accurate measurement cannot be performed if there is a leak in the insulating film when the C-V characteristic is obtained by the quasi-static method, but since there is always a gap in this method, tunnel current and discharge may occur. Unless it happens, CV measurements can be made even with very thin insulators.

【0012】通常の交流表面光電圧測定では、半導体表
面が反転していないと測定できない。従ってSiウエハ
評価はN形Siしかできなかった。これに対して本ギャ
ップ電極を用いると、透明電極に直流バイアスを印加す
ることによりP形Si表面を反転することができ、N形
半導体でも評価できるようになる。
Normal AC surface photovoltage measurement cannot be performed unless the semiconductor surface is inverted. Therefore, only N-type Si could be evaluated in the Si wafer. On the other hand, when this gap electrode is used, the P-type Si surface can be inverted by applying a DC bias to the transparent electrode, and it becomes possible to evaluate even an N-type semiconductor.

【0013】[0013]

【実施例】以下、本発明を実施例により説明する。EXAMPLES The present invention will be described below with reference to examples.

【0014】(実施例1)図1に示したように、シリコ
ン1上にシリコン酸化膜2を厚さ100nm形成し、こ
のウエハを試料台上に設置し、電極3を可動機構4によ
りシリコン酸化膜表面から約100nmの距離と約15
0nmの距離に近づけてC−V特性を測定することがで
きた。この場合の電極可動機構4はマイクロメータによ
る粗動調整部と圧電アクチュエータによる微動調整の組
合せで行った。
(Embodiment 1) As shown in FIG. 1, a silicon oxide film 2 having a thickness of 100 nm is formed on silicon 1, this wafer is placed on a sample table, and an electrode 3 is oxidized by a movable mechanism 4. Distance of about 100 nm from the film surface and about 15
It was possible to measure the CV characteristics by approaching the distance of 0 nm. In this case, the electrode moving mechanism 4 is a combination of a coarse adjustment unit using a micrometer and a fine adjustment unit using a piezoelectric actuator.

【0015】通常の図3に示した水銀プローブでは図5
(イ)の構成で、図下に示した正電荷分布を仮定する
と、半導体表面に誘起される電荷Qは、
In the conventional mercury probe shown in FIG. 3, the mercury probe shown in FIG.
Assuming the positive charge distribution shown in the lower part of the configuration in (a), the charge Q induced on the semiconductor surface is

【0016】[0016]

【数1】 [Equation 1]

【0017】で示される。ここでeは電子電荷、t0
絶縁膜の厚さ、ρ(χ)は絶縁膜中の電荷分布である。
(1)式は膜内電荷がq0で一定なら次式となる。
[0017] Here, e is the electronic charge, t 0 is the thickness of the insulating film, and ρ (χ) is the charge distribution in the insulating film.
The equation (1) becomes the following equation if the charge in the film is constant at q 0 .

【0018】[0018]

【数2】 [Equation 2]

【0019】これに対して上述のエアギャップ電極の場
合には、図5(ロ)のようになり、
On the other hand, in the case of the air gap electrode described above, the result is as shown in FIG.

【0020】[0020]

【数3】 [Equation 3]

【0021】となる。ここでεは絶縁物の比誘電率であ
る。ここでt1を変えてt2にすれば未知数Qi,q0,Q
3を求めることができる。このような正電荷分布は、S
iO2付Siをプラズマ照射した場合等には非常に良く
当てはまる。即ち、SiO2をステップエッチして求め
た正電荷分布はまさに図5(イ)のようになっている場
合が多い。
[0021] Here, ε is the relative permittivity of the insulator. Here, if t 1 is changed to t 2 , unknowns Q i , q 0 , Q
You can ask for 3 . Such a positive charge distribution is S
This is very well applicable when plasma is irradiated with Si with iO 2 . That is, in many cases, the positive charge distribution obtained by step-etching SiO 2 is exactly as shown in FIG.

【0022】図5(イ)の正電荷分布でない場合でも、
1を変えて多くのC−V特性から、誘起電荷量を測定
して、コンピュータ処理等により電荷分布を推定するこ
とが可能である。
Even if the positive charge distribution shown in FIG.
It is possible to estimate the amount of induced charges from various CV characteristics by changing t 1 and estimate the charge distribution by computer processing or the like.

【0023】(実施例2)本発明実施に於いて重要な点
はエアギャップ電極を試料の半導体と平行度を保つこと
である。図6に示したように、主電極3に対してその両
側に副電極10と10’を設け、それぞれの容量のバラ
ンス具合をフィールドバックし、試料台9の傾きを調整
する可動機構4’を動かして平行度補正をすることによ
り平行度を保つことができた。実際には副電極は図7に
示したように4つの副電極10,10’,10”,1
0'''を用い、可動機構も2つ用いた。副電極は3つ以
上あれば平行度補正が可能である。
(Embodiment 2) An important point in carrying out the present invention is to keep the air gap electrode parallel to the semiconductor of the sample. As shown in FIG. 6, the sub-electrodes 10 and 10 'are provided on both sides of the main electrode 3, and the movable mechanism 4'for adjusting the inclination of the sample table 9 by field-backing the balance of the respective capacities. It was possible to maintain the parallelism by moving it to correct the parallelism. Actually, the sub-electrodes are four sub-electrodes 10, 10 ', 10 ", 1 as shown in FIG.
0 '''was used, and two movable mechanisms were also used. Parallelism can be corrected if there are three or more sub-electrodes.

【0024】なお、この他コンパクトディスクプレイヤ
ーで用いられているスプリット光ビームを用いて平行度
を検出する等、光応用による平行度検出も考えられる。
In addition to this, parallelism detection by optical application, such as detecting parallelism using a split light beam used in a compact disc player, is also conceivable.

【0025】(実施例3)上記実施例では、電極として
金の蒸着膜を使用した。蒸着膜の表面は、凹凸がはげし
いことがあり、平面電極といえない場合もある。そこ
で、砒素(As)を大量ドープした鏡面研摩したSiウ
エハを加工して電極とした所、良好な測定結果を得るこ
とができた。
(Embodiment 3) In the above embodiment, a vapor deposition film of gold was used as an electrode. The surface of the vapor-deposited film may have a rough surface and may not be a flat electrode. Therefore, when a mirror-polished Si wafer heavily doped with arsenic (As) was processed into an electrode, good measurement results could be obtained.

【0026】(実施例4)シリコンウエハは通常20Å
程度の自然酸化膜が表面に形成されている。これに電極
を付けてC−V特性を測定しようとしてもリーク電流が
大きいため実際上測定不可能である。図1に示した構成
でエアギャップ電極を用いたところ約500Å(50n
m)でC−V特性を得ることができた。すなわちSiの
表面処理等の効果も本発明を用いて評価することが可能
と言える。100-cmのN型Siではエアギャップ0.
5μm以下でC−V測定可能で、0.1μm以下で良好
なC−V特性が得られた。
(Embodiment 4) A silicon wafer is usually 20 Å
A degree of natural oxide film is formed on the surface. Even if an electrode is attached to this and an attempt is made to measure the C-V characteristic, the leakage current is large and it is practically impossible to measure. When an air gap electrode is used in the configuration shown in FIG. 1, it is about 500Å (50n
It was possible to obtain C-V characteristics in m). That is, it can be said that the effects of surface treatment of Si can be evaluated using the present invention. For N-type Si of 100 - cm, the air gap is 0.
C-V measurement was possible at 5 μm or less, and good C-V characteristics were obtained at 0.1 μm or less.

【0027】(実施例5)図8に示したように、透明電
極3'''にバイアス電圧を印加することにより、半導体
(Si)1の表面ポテンシャルを制御することができ、
任意の表面ポテンシャルで光8を照射することにより表
面光誘起電圧を測定することが可能であることを確認し
た。これは表面電荷や界面準位、さらにはバルクSiの
ライフタイム等を分離して求めることを容易ならしめる
効果がある。
(Embodiment 5) As shown in FIG. 8, by applying a bias voltage to the transparent electrode 3 ''', the surface potential of the semiconductor (Si) 1 can be controlled.
It was confirmed that it is possible to measure the surface light induced voltage by irradiating the light 8 with an arbitrary surface potential. This has the effect of facilitating the surface charge, interface state, and lifetime of bulk Si to be separately determined.

【0028】また通常のSiウエハはアンモニカルバー
オキサイド(NH4OHとH22)処理を行っているた
め、表面がP型化している。このためN型Siのライフ
タイム測定は従来の図4で容易に行えたが、P型Siで
も困難であった。これに対し図8ではSi表面を透明電
極に正電圧を印加することにより表面をN型化できライ
フタイム測定も可能とすることができた。
Further, since a normal Si wafer is subjected to an ammonium hydroxide (NH 4 OH and H 2 O 2 ) treatment, its surface is made P-type. Therefore, the lifetime measurement of N-type Si can be easily performed in FIG. 4 of the related art, but it is also difficult for P-type Si. On the other hand, in FIG. 8, by applying a positive voltage to the transparent electrode on the Si surface, the surface can be made N-type and the lifetime measurement can be performed.

【0029】(実施例6)LSIのSiウエハは表側か
ら基板Siを観察しようとしても通常は配線やゲート電
極等によって妨げられて困難であった。これに対し、図
9に示すようにSiウェハの裏側に穴を明けて、Siを
厚さ20μm程度とすることで交流表面光誘起電圧を観
測することにより、約1μmの分解能でSiを評価する
ことが可能となった。
(Embodiment 6) In the Si wafer of LSI, it was difficult to observe the substrate Si from the front side because it was usually hindered by the wiring and the gate electrode. On the other hand, as shown in FIG. 9, by making a hole on the back side of the Si wafer and setting the thickness of Si to about 20 μm, the AC surface photoinduced voltage is observed to evaluate Si with a resolution of about 1 μm. Became possible.

【0030】(実施例7)実施例4は大気中で測定を行
った。しかし大気中の湿気等により安定な(再現性の良
い)測定が困難な場合があった。測定系に乾燥窒素を流
すことによりかなりこの問題が改善されることを確認し
た。測定系全体を真空中に設置するとさらに安定した測
定ができることも確認した。
Example 7 In Example 4, the measurement was performed in the atmosphere. However, stable (good reproducibility) measurement may be difficult due to atmospheric humidity. It was confirmed that flowing dry nitrogen in the measurement system significantly ameliorated this problem. It was also confirmed that more stable measurement can be performed by placing the entire measurement system in a vacuum.

【0031】(実施例8)図1に於いて可動機構の一つ
である積層型圧電アクチュエーターに交流電圧を印加す
ることによってギャップ電極を数100KHzで振動さ
せることができる。これにより試料表面の電位を測定す
ることができた。
(Embodiment 8) In FIG. 1, the gap electrode can be oscillated at several 100 KHz by applying an AC voltage to the laminated piezoelectric actuator which is one of the movable mechanisms. As a result, the potential of the sample surface could be measured.

【0032】(実施例9)今までの実施例ではすべてギ
ャップは空気あるいは窒素あるいは真空であったが、ギ
ャップを液体で埋めることも可能である。シリコンホイ
ルの(C26OSi)4を用いたところ、4μm程度のギ
ャップでもC−V測定が可能である。
(Embodiment 9) In all the embodiments so far, the gap is air, nitrogen or vacuum, but it is also possible to fill the gap with a liquid. When silicon foil (C 2 H 6 OSi) 4 is used, CV measurement is possible even with a gap of about 4 μm.

【0033】これはシリコンオイルの比誘電率が2.4
であるためである。より比誘電率の大きな液体を用いれ
ばギャップを大きくとれるが、後で洗浄・乾燥しなけれ
ばならない場合が多いので、有効でない場合もありう
る。
This is because the relative permittivity of silicone oil is 2.4.
This is because. If a liquid having a higher relative dielectric constant is used, the gap can be increased, but it is often ineffective because it must be washed and dried later.

【0034】以上の実施例では半導体としてSiを用い
たが、GaAs等のIII−V族やII−VI族等の化合物半
導体についても本発明が有効である。
Although Si is used as a semiconductor in the above embodiments, the present invention is also effective for compound semiconductors of III-V group or II-VI group such as GaAs.

【0035】本発明の実施例によれば、ステップエッチ
することなく半導体表面の絶縁膜中の電荷分布を求める
ことが可能という効果がある。またリーク性の絶縁膜や
極めて薄い絶縁性膜が表面にある半導体の表面計測すな
わち界面準位や表面電荷を求めることができる。
According to the embodiment of the present invention, it is possible to obtain the charge distribution in the insulating film on the semiconductor surface without step etching. Further, it is possible to measure the surface of a semiconductor having a leaky insulating film or an extremely thin insulating film on its surface, that is, obtain the interface state and surface charge.

【0036】また本発明の実施例によれば、表面光誘起
電圧を用いた走査光子顕微鏡すなわちSPM(Surface
Photon Microscope,(棟方忠輔,応用物理,第53
巻,第3号(1984年)PP176)に於いて、誘明電極に
直流バイアスを印加することにより多くの情報すなわち
界面準位やライフタイムを容易に求めることができる。
またSiウエハの受入検査に於いても、N型,P型両方
の評価が可能となり応用範囲が広くなる。またLSIの
不良解析等に於いても、裏側からSiをエッチングした
数10μmから数μmのSiを残した構造で1μm前後
の分解能で、SiおよびSi表面の情報が得られるよう
になる。
Further, according to the embodiment of the present invention, a scanning photon microscope, that is, an SPM (Surface) using the surface photoinduced voltage is used.
Photon Microscope, (Tadasuke Munekata, Applied Physics, 53rd
Vol. 3, No. 3 (1984) PP176), it is possible to easily obtain much information, that is, the interface state and lifetime, by applying a DC bias to the attracting electrode.
In addition, in the acceptance inspection of the Si wafer, both N type and P type can be evaluated, and the application range is widened. Further, also in the defect analysis of the LSI and the like, information on the Si and Si surfaces can be obtained with a resolution of about 1 μm in the structure in which Si of several tens μm to several μm left by etching Si from the back side is left.

【0037】[0037]

【発明の効果】本発明によれば、効率良く被計測物中の
電荷分布を推定することができる。
According to the present invention, the charge distribution in the object to be measured can be estimated efficiently.

【0038】[0038]

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す断面図。FIG. 1 is a sectional view showing an embodiment of the present invention.

【図2】従来の半導体表面計測法を示す図。FIG. 2 is a diagram showing a conventional semiconductor surface measuring method.

【図3】従来の半導体表面計測法を示す図。FIG. 3 is a diagram showing a conventional semiconductor surface measuring method.

【図4】従来の半導体表面計測法を示す図。FIG. 4 is a diagram showing a conventional semiconductor surface measuring method.

【図5】本発明の一実施例の効果を示すための図で、従
来法(イ)と本発明(ロ)の場合の電荷分布を示してい
る。
FIG. 5 is a diagram showing an effect of one embodiment of the present invention, showing charge distributions in the conventional method (a) and the present invention (b).

【図6】本発明の一実施例を示す図。FIG. 6 is a diagram showing an embodiment of the present invention.

【図7】本発明の一実施例を示す図。FIG. 7 is a diagram showing an embodiment of the present invention.

【図8】本発明の一実施例を示す図。FIG. 8 is a diagram showing an embodiment of the present invention.

【図9】本発明の一実施例を示す図。FIG. 9 is a diagram showing an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1…半導体基板、2…絶縁膜、3…電極、4…可動機
構、5…電極接続棒、6…透明スペーサー、7…ガラス
板、8…光線、9…試料台、10…副(補助)電極、1
1…デバイス・配線層。
DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Insulating film, 3 ... Electrode, 4 ... Movable mechanism, 5 ... Electrode connection rod, 6 ... Transparent spacer, 7 ... Glass plate, 8 ... Ray, 9 ... Sample stand, 10 ... Sub (auxiliary) Electrode, 1
1 ... Device / wiring layer.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 春田 亮 東京都国分寺市東恋ケ窪1丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 棟方 忠輔 東京都国分寺市東恋ケ窪1丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 細木 茂行 東京都国分寺市東恋ケ窪1丁目280番地 株式会社日立製作所中央研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ryo Haruta 1-280, Higashi Koikekubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor, Tadasuke Mitsukata 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi, Ltd. Central Research Laboratory (72) Inventor Shigeyuki Hosoki 1-280, Higashi Koikekubo, Kokubunji City, Tokyo Inside Central Research Laboratory, Hitachi, Ltd.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】被計測物と電極との間に電圧を印加する表
面計測装置において、 一つの前記被計測物に対し、前記被計測物と前記電極と
の間の距離を複数の異なる距離に保持し、それぞれの距
離において前記電圧を印加する手段を有することを特徴
とする表面計測装置。
1. A surface measuring apparatus for applying a voltage between an object to be measured and an electrode, wherein a distance between the object to be measured and the electrode is set to a plurality of different distances with respect to one object to be measured. A surface measuring device comprising means for holding and applying the voltage at each distance.
JP22922494A 1994-09-26 1994-09-26 Surface measuring device Expired - Lifetime JP2682465B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22922494A JP2682465B2 (en) 1994-09-26 1994-09-26 Surface measuring device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22922494A JP2682465B2 (en) 1994-09-26 1994-09-26 Surface measuring device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP62238726A Division JP2690908B2 (en) 1987-09-25 1987-09-25 Surface measuring device

Publications (2)

Publication Number Publication Date
JPH07174800A true JPH07174800A (en) 1995-07-14
JP2682465B2 JP2682465B2 (en) 1997-11-26

Family

ID=16888782

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22922494A Expired - Lifetime JP2682465B2 (en) 1994-09-26 1994-09-26 Surface measuring device

Country Status (1)

Country Link
JP (1) JP2682465B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010038697A (en) * 2008-08-04 2010-02-18 Nihon Univ Device and method for evaluating crystallinity of silicon semiconductor thin film

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015161136A1 (en) 2014-04-17 2015-10-22 Femtometrix, Inc. Wafer metrology technologies
EP3794335A4 (en) 2018-05-15 2022-03-02 Femtometrix, Inc. Second harmonic generation (shg) optical inspection system designs

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010038697A (en) * 2008-08-04 2010-02-18 Nihon Univ Device and method for evaluating crystallinity of silicon semiconductor thin film

Also Published As

Publication number Publication date
JP2682465B2 (en) 1997-11-26

Similar Documents

Publication Publication Date Title
JP2690908B2 (en) Surface measuring device
US7893703B2 (en) Systems and methods for controlling deposition of a charge on a wafer for measurement of one or more electrical properties of the wafer
US6300756B2 (en) Micro-mechanical probes for charge sensing
US6265890B1 (en) In-line non-contact depletion capacitance measurement method and apparatus
US6459482B1 (en) Grainless material for calibration sample
US6915232B2 (en) Film thickness measuring method, relative dielectric constant measuring method, film thickness measuring apparatus, and relative dielectric constant measuring apparatus
JPH06349920A (en) Electric charge measuring method of semiconductor wafer
US6456082B2 (en) Method for polysilicon crystalline line width measurement post etch in undoped-poly process
US7521946B1 (en) Electrical measurements on semiconductors using corona and microwave techniques
JPH07174800A (en) Surface measuring instrument
JPH02205046A (en) Method and apparatus for measuring semiconductor surface
JP2682464B2 (en) Surface measuring device
JPH07167902A (en) Surface measuring method
EP1610373A2 (en) Method and apparatus for determining generation lifetime of product semiconductor wafers
Schwarzenbach et al. Systematic evaluation of SOI buried oxide reliability for partially depleted and fully depleted applications
JP2977172B2 (en) Method for measuring semiconductor characteristics
Yoshida et al. A Novel Non-Destructive Characterization Method of Electronic Properties of Pre-and Post-Processing Silicon Surfaces Based on Ultrahigh-Vacuum Contactless Capacitance-Voltage Measurements
Mego Guidelines for interpreting CV data.
Allen et al. Sheet and line resistance of patterned SOI surface film CD reference materials as a function of substrate bias
US6642518B1 (en) Assembly and method for improved scanning electron microscope analysis of semiconductor devices
Stacey et al. Using surface charge analysis to characterize the radiation response of Si/SiO/sub 2/structures
Roy et al. Non-contact characterization of ultrathin dielectrics for the gigabit era
JPH05183036A (en) Measurement of c-v characteristic
JP2709351B2 (en) CV characteristic conversion method in non-contact CV measurement device
JPH11274258A (en) Method and device for measuring charge amount