JPH07170201A - Interleave circuit - Google Patents

Abstract

PURPOSE:To unnecessitate a memory by composing the circuit of three kinds of shift registers of N steps of serial/parallel converting shift registers, delay shift registers and N steps of parallel/serial converting shift registers. CONSTITUTION:Input data inputted from an input terminal 1 are converted into N stages) of parallel data by a serial/parallel shift register 3. This shift register 3 outputs N stages of parallel signals which are read by a high-speed clock signal inputted from a clock input terminal 2 and define a clock signal frequency-divided into 1/N stages by an N frequency divider circuit 4 as a clock signal. Further, these N stages of parallel converted data are inputted to N-1 pieces of shift registers 5-1-5-(N-1) for delaying the respective data. The N stages of parallel data delayed by the shift registers 5-1-5-(N-1) are inputted to a parallel/serial converting shift register 6. The output data of the shift register 6 are outputted as data interleaving the input data of the input terminal 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interleave circuit, and more particularly to an interleave circuit required in a digital modulation circuit.

[0002]

2. Description of the Related Art A conventional interleave circuit is composed of a memory as disclosed in, for example, Japanese Patent Laid-Open No. 59-154836.

FIG. 4 shows an example of a conventional interleave circuit. The switch 9 is a data write changeover switch, and the switch 10 is a data read changeover switch, and switches between writing and reading of data in the memories 11 and 12. The control circuit 13 sets addresses of the memories 11 and 12 and controls writing / reading switching.

The operation will be described below with reference to FIG. When the switch 9 is switched to the memory 11 and the switch 10 is switched to the memory 12, one frame of input data is written in the memory 11, and one frame of data is read from the memory 12 and becomes output data. At this time, the control circuit 13 gives a write address to the memory 11 and a read address to the memory 12. When the writing / reading of the data for one frame is completed, the switch 9 switches the memory 12
Then, the switch 10 is switched to the memory 11, one frame of input data is written in the memory 12, and one frame of data is read from the memory 11 and becomes output data. At this time, the control circuit 13 gives a read address to the memory 11 and a write address to the memory 12. When the reading / writing of data for one frame is completed, the switch 9 is switched to the memory 11 and the switch 10 is switched to the memory 12 again, and the memory 11 writes and the memory 12 reads. After that, the writing / reading is alternately switched, and the input data is interleaved for each frame and obtained as output data.

FIG. 5 shows an example of a data writing direction and a data reading direction in the memory. In the figure, the address is 8 bits, the frame is 256 bytes, and the interleave depth is 4, and the data is interleaved by switching the address for writing and the address for reading.

[0006]

In the conventional interleave circuit, since several memories are used, it is necessary to control the reading and writing of a plurality of memories, and at that time, the timing with the reading / writing switch of data is taken. There were difficult drawbacks. In particular, in the interleave circuit for high-speed data signals, there is a drawback that timing correction is required because switching timing processing for a short time is required.

[0007]

An interleave circuit according to the present invention includes a shift register for converting input data into N (N is a natural number of 2 or more) parallel data, and an N- delay circuit for delaying the N parallel data. 1 M to M *
(N-1) (M is a natural number of 2 or more) stages of shift registers, N stages of shift registers for serially converting the delayed data, and clocks to the N-1 delay shift registers. And an N divider.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an interleave circuit according to the present invention.

Input data is input from the input terminal 1, and this input data is parallel-converted in N stages by the serial / parallel conversion shift register 3. The shift register 3 reads the high-speed clock signal fc (Hz) input from the clock input terminal 2 and uses the clock signal fc / N (Hz) which is 1 / N by the N frequency dividing circuit 4 as a clock signal. It outputs N parallel signals. Further, the N-stage parallel-converted data has N-1 shift registers 5-1 to 5-for giving a delay to each data.
Input to (N-1). This shift register 5-1
The number of stages of 5- (N-1) is M to M * (N-1). Further, these shift registers have the above-mentioned fc / N (H
z) is used as a clock signal. The N-stage parallel data delayed by the shift registers 5-1 to 5- (N-1) are input to the parallel / serial conversion shift register 6. The output data of the shift register 6 is output from the output terminal 7 as data obtained by interleaving the input data of the input terminal 1. At this time, the clock frequency of the N-stage parallel data was fc / N (Hz), but the data output at the same speed as the data input can be obtained by operating the shift register 6 again with the clock signal fc.

Now, assuming that the input data series input to the terminal 1 is ... A (-1), a (0), a (1), a (2) ..., N = 4. The output data of No. 3 is as shown in FIG.

In the figure, the data string a (-
8), a (-7), a (-6), and a (-5) are sequentially output as output data of the shift register 3.

This output data is delayed by passing through the 2-stage, 4-stage and 6-stage shift registers by the shift registers 5-1, 5-2 and 5-3 with M = 2, and the output data at that time is shown in FIG. 3 shows. In the figure, the data interval is 7 (2 × 4-1), and the data string a
(-29), a (-22), a (-15), a (-8)
Will be output sequentially.

Although the case where N = 4 and M = 2 has been described above, the same can be applied to the general case as follows.

According to the circuit configuration of FIG. 1, the interleave depth D is D = N (1) The interleave interval L is L = (N-1) + (M-1) * N = N * M-1 ( 2) If the input data of the input terminal 1 is {a (n)} (n = 0,1,2 ...) (3), the output data obtained from the output terminal 7 is a (k), a (k + N * M). -1), a (k + 2 * (N * M-1)) ... a (k + (N-1) * (N * M-1)) (k = 0,1,2 ...) (4) and Become.

As described above, the present invention includes three stages of the N-stage serial / parallel conversion shift register 3, the delay shift registers 5-1 to 5- (N-1), and the N-stage parallel / serial conversion shift register 6. An interleave circuit is composed of different types of shift registers.

Further, the deinterleave circuit can be easily realized by performing an operation reverse to that of the interleave circuit of the present invention.

[0018]

As described above, the present invention resides in that the interleave circuit is configured by three types of shift registers, that is, a serial / parallel conversion shift register, a delay shift register, and a parallel / serial conversion shift register.

This has the effect that an interleave circuit can be constructed without the need for a memory.

[Brief description of drawings]

FIG. 1 is a block diagram of an interleave circuit according to the present invention.

FIG. 2 is output data of the shift register 3 of the interleave circuit of the present invention.

FIG. 3 is input data of the shift register 6 of the interleave circuit of the present invention.

FIG. 4 is an example of a conventional interleave circuit.

5 is an example of an interleave circuit in the conventional circuit diagram shown in FIG.

[Explanation of symbols]

 1 data input terminal 2 clock input terminal 3 serial / parallel conversion shift register 4 clock divider 5 delay shift register 6 parallel / serial conversion shift register 7 data output terminal 8 clock output terminal 9 data input terminal 10 data output terminal 11 memory 12 Memory 13 Control circuit

Claims (1)

[Claims] 1. Input data is N (N is a natural number of 2 or more).
A shift register for converting into parallel data of two stages;
N-1 M's that give delay to each stage parallel data
~ M * (N-1) (M is a natural number of 2 or more) stage shift registers, N stage shift registers for serially converting the delayed data, and clocks to the N-1 delay shift registers. And a 1 / N frequency divider for giving an interleave circuit.