JPH0716254B2 - Control signal expansion device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a system for smoothing or stretching transitions between regions of a video transmitted by a TV signal processed by the first and second methods. It is a thing.

Conventional technology and problems Standard T such as NTSC or PAL system signals that represent video
The processing of the V signal often changes to adapt to the signal environment. This adaptive processing produces areas of one image processed by one method and other adjacent areas processed by another method. If the above processing differences are perceived by the viewer, or if differently processed areas and transitions between areas are recognized, the image quality will be degraded.

For example, a frame comb filter is used when separating chromaticity and luma components from a composite video signal. The chromaticity and luminance components cannot be completely separated unless there is a change in the frame time interval from the image. If the screen changes at frame time intervals, some chromaticity information will appear in the separated luma component and some luma information will appear on the chromaticity component.

The line comb filter also separates the luminance and chromaticity components from the composite video signal and does not generate a severely degraded component signal in the presence of image movement. However, the line comb filter reduces the vertical resolution of the reproduced image as compared to the frame comb filter. In addition to that, at the point where the vertical transition occurs, the chromaticity information introduced into the luminance component and the vicinity area of the transition are generated by the line comb filter, which produces an image artifact known as a hanging dot. Produces the wrong chromaticity. The quality is degraded by the luminance information introduced into the chromaticity component.

The TV signal is adaptively processed by detecting the presence or absence of video movement. A frame comb filter is used in the area where the image is stopped, and a line comb filter is used in the area where the image is changed.

Another example of such adaptive processing is an adaptively double-scanned (non-interlaced) progressive scan converter. The lines between the scan lines in such a converter are shown between the lines of the current field. However, if there are changes that produce noticeable artifacts, such as gear-like contours, the lines between the scan lines are from the previous field. The lines between the scan lines can also be interpolated with the lines in the current field, but the vertical resolution is reduced and line flicker is generated. Lines between interpolated scan lines within the field are shown, and lines between field-delayed scan lines are indicated by other methods, in the region detected in the image.

Another example is an adaptive peaking circuit, where areas with relatively high noise are processed with a relatively low peaking factor, and areas with relatively low noise are processed with a relatively high peaking factor. It

In all of the above examples, the processing of the TV signal varies in response to the estimated parameter values of the image. The parameters above are movements in the context of luma / chromaticity separation and double scan progressive conversion, and relative noise levels in the above peaking situation. The apparent boundaries between differently treated regions and regions with and without parameters are undesired artifacts introduced by the adaptive processing scheme.

According to the invention disclosed in U.S. Pat. No. 4,868,650 issued September 19, 1989, H. J. Wekkenbrock, the parameters of a composite video signal are estimated in terms of image points. The control signal is then generated by the above parameters. This control signal is used to control the selection of the processing mode. Then, the control signal is proportionally stretched by a direction that decreases the value of the control signal in at least one direction around the area where the control signal is generated. These generate an area in which the above processing changes from an area where one processing method is performed to an area where another processing method is performed more and more.

In the following description of the device for expanding the control signal,
The word "horizontal" refers to the direction of the scan line,
The word "vertical" refers to the direction perpendicular to the scan line. The invention can be carried out by analog circuits, but will be described in digital form.

Since the control signal is derived for the pixel along the scan line, the control signal has a fixed control signal amplitude such as "1", and the rest of the signal has a reference value such as "0". Hold.
As is well understood by those having ordinary skill in the technical field of the present invention, each scanning line has a fixed number of pixels, and when such a number of pixels is input, the image forming apparatus is Position the next pixel at the beginning of the line.

According to the present invention, the control signal is input to a vertical stretcher and a horizontal stretcher connected in series in one direction. The horizontal stretcher repeats each logic "1" control signal n times, where n is equal to the number of clock delay elements in the vertical stretcher 32. Also, the vertical stretcher repeats each scan line m times, where m is the same as the number of line delays represented in the vertical stretcher 34 as 1H delays. In this way, there are m + 1 identical scans each having a logic "1" at a point along the line where the original control signal is generated and n additional "1" s occurring immediately thereafter. Lines are generated.

When a stretched series of control signal values encompassing the repeated scan line indicates to the horizontal and vertical stretchers, this is
The first original control signal pixel is input to the line signal expander which produces a ramp of increasing value which is expanded through the pixels of the logic "1" which follow. The line signal expander holds the maximum value generated at the end of the slope of n pixels until the end "1" is input. At this fulcrum, the line signal generator generates a ramp of a value that decreases the next r pixels in between, and the r value and the n value are the same in order to make an opposition between the slope of the increasing value and the slope of the decreasing value. You will understand what you have to do.

Instead of having a control signal that suddenly changes from 0 to 1 and back to 0, a line signal expander that produces a signal that gradually changes from the original control signal above to a maximum value such as 0 to 7 at the point where it now appears. Holds this value as long as the number of clock cycles is the same as the number of adjacent control signals, and then gradually reduces the signal to a value of zero. At this point there are m + 1 identical lines.

This stretches the control signal horizontally along each of m + 1 lines, while there is no vertical stretch since all the lines have the same value. Vertical stretching is accomplished in accordance with the preferred form of the invention by effectively forming a window that is one clock cycle wide and m + 1 line high. This window is scanned horizontally to the end of the line, then one line at a time before being further scanned across the line. The control signal value for the point corresponding to the lower part of the window is a function of all the values in the window. It can be seen that even simple addition of values within this window can be accomplished.

As will be appreciated by one of ordinary skill in the art of the present invention, the required delay required to obtain the decompression control signal in such a manner is that the decompression control signal relative to the original control signal. The signal value is delayed by the interval of n pixels for the corresponding video signal plus the interval of m scanning lines. This can be corrected by delaying the video signal by the interval of n pixels and m line scans.

The obvious advantage of such a method for stretching the control signal is that the maximum of the rising slope occurs at the first original control signal pixel rather than at some later pixels as in the other methods. .

Embodiments The embodiments disclosed below are described in terms of a dynamic adaptive luma / chromaticity separator. Similar configurations can be used in different adaptive processing circuits such as double-scan progressive adaptive scan conversion and adaptive peaking.

A composite video signal, such as that derived from NTSC broadcast by the TV receiver in FIG. 1, is input to terminal 10. The motion detector 12 has a value such as "1" when it is considered to be moving and a signal having a reference signal "0" value when it is considered to be not moving, such as the one shown on the screen. It is transmitted to the expander 14. The k-value generator 16 inputs the signal at the output of the signal expander 14 in order to generate k-values and 1-k-values for controlling the soft switches 18,20. The composite video signal from the terminal 10 is input to the frame comb filter 24 via the delay circuit 22 and to the line comb filter 28 via the matching delay circuit 26. When there is no movement in the image The above frame comb filter
The 24 outputs are used to generate a luminance signal Y _FC and a chromaticity signal C _FC .

The frame comb filter takes advantage of the fact that in the absence of movement, two composite video images separated by a frame time interval differ only in the phase of the chromaticity signal. Therefore, when two composite video signals separated by one frame are combined, the luminance component is enhanced so as to generate a luminance signal free of color contamination, while the color component is lost. Generates a chromaticity signal with no brightness contamination and eliminates the brightness signal. However, when there is movement, the output of the line comb filter 28 is used. Normally, there is no other change from one line to the next line, and since the chromaticity signal has a phase difference of 180 ° with the adjacent line, signals from the same point on the adjacent line have the above chromaticity component. Besides eliminating and enhancing the luminance component, subtraction eliminates the luminance component and enhances the chromaticity component to produce uncontaminated luminance and chromaticity signals. However, the line comb filter reduces the vertical resolution by half.

If the frame comb wave signal from the frame comb filter 24 is used only when there is no movement, and the line comb wave signal from the line comb filter 28 is used only when there is no movement. The differences between areas of the screen, with and without movement, are mostly noticeable in most cases. Therefore, when scanning an image close to a moving area, the frame comb filter
It is better to use less and more signal from 24 and more and more signal from the above line comb filter 28. In this case, k is "1" when there is movement and k is "0" when there is no movement. In the area where the moving area is covered and hidden, the k value has an intermediate value. Thus, the k value determines the relative sum of the outputs of the comb filters 24,28 which are mixed together in the soft switches 18,20.

The signal stretcher 14 outputs the maximum value from a certain point of movement,
Outputs smaller and smaller values as the distance from the area where movement increases increases.

The main components of the control signal expander constructed according to the present invention will be described with reference to the block diagram of FIG.

A control signal having a value of "1" when there is a motion-like phenomenon and having a value of "0" when there is no motion-like phenomenon is a terminal 30.
Entered in. A suitable means for generating such a control signal is the motion detector 12 of FIG.

The horizontal stretcher 32 is connected to the input terminal 30 and transmits all “1” s input to the terminal 30, the final “1” being the terminal 30.
Generate n additional "1s" after being input to A vertical stretcher 34 connected to the output of the horizontal stretcher 32 repeats the line indicated by the horizontal stretcher m times each.

The first n + of each line derived from the vertical stretcher 34
Stretcher 34 that produces a ramp of increasing value during one "1"
The line signal expander 36, which is connected to the line signal generator, maintains the maximum value of the slope as long as "1" is present, and generates a slope having a decreasing value for the next r pixels. In the general case, n and r are the same in order to balance between the two slopes (n =
r). Thus there are m + 1 lines with increasing value slopes, a series of maximum values and a decreasing value range.

Vertical signal expander 38, each connected to line signal expander 36
And a time stretcher 40 controls the soft switches 18, 20 and derives the control signal values used by the k-value generator 16 to generate the k and 1-k values used in sequence. If required, the time stretcher 40 can be suitably configured with a pass filter LPF. Gradual transitions occur from the time domain to the moving and static areas of the screen.

This control signal value is one clock cycle wide and m
It is formed by sliding a +1 height window across the raster and combining the values within this window by one particular method. It will be appreciated that other functions are possible to combine this value, but can also be accomplished as a simple addition.

Please refer to the schematic diagram of FIG. 3 for a description of the detailed embodiment of the invention shown in the block diagram of FIG. 2 which excludes the time stretcher 40, which is an optional specification not commonly used. To do. The horizontal stretcher 32 has an input terminal 44 in which a series of n clock delay elements are serially connected. Six clock delays 46-56 are used in this embodiment. The output of the OR gate 58 is an output terminal
The seven inputs of the OR gate 58 are coupled to the input terminal 44 and the outputs of the clock delays 46-56, which are separated from the input terminal 44, respectively. The control signal with a value of amplitude 1 which indicates the presence of a movement-like phenomenon is repeated 6 times at the output terminal 60.

The vertical stretcher 34 of FIG. 3 is similarly constructed. m
The 1H delay device is connected in series with the input terminal 62, but in this embodiment, there are four 1H delay devices 64, 66, 68 and 70.
Has a value of 4. The output of the logical gate 72 is an output terminal
It is connected to 74, and each of the five inputs is the above input terminal 62.
And the outputs of the 1H delay devices 64-70 remote from the input terminal 62. All lines of the control signal applied to the input terminal 62 are repeated four times at the output terminal 74.

The horizontal stretcher 32 and the vertical stretcher 34 are serially connected in series between an input terminal 30 for a stretching system and an output terminal 76 for a stretching circuit. However, the order of the horizontal and vertical stretchers can be reversed as described below. In all cases, a control signal with a logic "0" value passes through the decompression circuits 32, 34 without any delay, and a control with a logic "1" value that indicates the presence of phenomena such as movement. The signal is repeated to form a square of logic "1", which is n + 1 clock cycles wide and m + 1 lines high.

The line signal expander 36 is coupled to the output terminal 76 and increases the value of "0" from a maximum value such as "7" during the first n control signal regions mentioned above. It functions to generate a ramp of signal values that increases along with. One maximum value indicated by a "1" at the terminal 76 is maintained, and when the "1" is interrupted, a ramp of the value of the signal which decreases along the line is generated during the period of r clock cycles. To do. In a general case, the r value and the n value are the same. This is accomplished in the same way along every line and m consecutive lines when the control signal is assumed to be a logic "1" value, and there are m + 1 identical lines.

In order to perform the line signal expansion function described above, the multiplexer 78 in the circuit explicitly shown in FIG.
It has an input terminal "0", an input terminal "1", and a switching control input 82 to which logic signals "0" and "1" are input. Output 80 is connected to input terminal “0” when logic “0” is applied to the control input 82, and output terminal “1” when logic “1” is applied to the input 82. It The generator 86 and the clock delay element 84, which perform the function f (x) = x-1, are connected in series between the output 80 and the input terminal "0". The generator 86 above cannot go below the "0" value. In this way, when a movement is detected and a logic "0" is present at the input terminal 30, the logic "0" is transmitted to the terminal 76 via the decompressor circuits 32, 34 and the output 80 of the multiplexer 78 is It becomes "0". If the signal from the output 80 of the multiplexer 78 were not "0", the operation of the generator 86 would reduce it to "0" out of at most m clock cycles. The multiplexer above, as specified below
78 produces the aforementioned decreasing value ramp.

The ramp of increasing values described above is formed by the multiplexer 88. The multiplexer 88 has an output 90 connected to the input of a multiplexer 78 having a terminal labeled "1", and also an input terminal "0" and an input terminal missing 1 ".
Switching control input 92 for which the value of “0” or “1” is input
With. Applying a logic "1" to the control input terminal 92, as in the multiplexer 78, connects the output 90 and the input terminal labeled "1" and applies a logic "0" to the control input terminal 92. Then, the output 90 is connected to the input terminal indicated by "0". Function f (x) = x
The clock delay unit 94 and the generator 96 for performing +1 are connected in series between the output 90 and the input terminal "1". The generator 96 cannot generate signal values above any selected value such as "7". Above multiplexer
The input terminal "0" of 88 is coupled to the output 80 of the multiplexer 78.

A second to generate the values of k and 1-k at each pixel location
The vertical signal expander 38, which generates the signal value that can be used by the k-value generator 16 in the figure, continuously outputs the signal value of each point and the signal value of the point above the scan line along which the k-value is obtained. And a means for combining a series of values that encode a predetermined function.

The means for usefully producing the above signal values which code the pixels along the scan line are here composed of m 1H delayers. Delay device 98,10
0, 102, 104 are clearly shown, and m in this embodiment is 4.

On the other hand, output 80 and four 1H delays remote from output 80
The control signal values at the ends of 94-104 are each weighted before being combined in the adder 104 which is the means for combining them.

The circuit operation of FIG. 3 will be described with reference to FIGS. 3A to 3F which clearly show the values of the signals existing at the corresponding points in FIG.

For purposes of this description, the control signal applied to the input terminal 30 at point A of the control signal expander is two consecutive "1" indicating the existence of a given phenomenon such as motion. Suppose we have a reference value of logic "0" at every other point on the scan line. Scan line L1
A state in which the original control signal of "1" value generated along is surrounded by a rectangle 108 is shown in FIG. 3A. It can be seen that line L1 can have more signal values than those shown. FIG. 3B illustrates the signal at point B, which is the output terminal 60 of the horizontal expander 32. This signal contains the original control signal in box 108 and n iterations of the logic "1" of the second control signal value. In this embodiment, it is assumed that the n value is 6 and that there are eight logic "1" s along the scan line L1.

At point B, the signal is input to the input terminal 62 of the vertical expander 34, which repeats the line L1 m times. In the above embodiment, since the m value is 4, the signal value having the same width as the number of control signals repeated by logic "1" and the control signal repeated n times and the height of m + 1 lines. It is generated from a predetermined point C included in the rectangle.

If the vertical stretcher 34 is performed before the horizontal stretcher 32, the output of the vertical stretcher is described as in FIG. 3C, and this signal is input to the horizontal stretcher 32 immediately. The signal of FIG. 3D is generated at.

The line signal expander 36 is operated as follows. 3D
The control signal values for all lines, including the lines L1 to L2 above in the figure, are multiplexer 78,8 as indicated.
It is continuously input to a terminal 76 connected to the eight switching control inputs 82 and 92. If the output 80 of the multiplexer 78 is not "0", then some "0" input to the terminal 76 will count down the multiplexer 80 to "0", which is shown at the output terminal 80. Above multiplexer 88
The output 90 of the
Since it is connected to the output 80 of 78, its switching input 92 is a single "0" value inputting a logic "0".

As soon as the value of the first logic "1" of the original control signal in the rectangle 108 is input to the input terminal 76, the outputs 80, 90 of the multiplexers 78, 88 are connected to their input terminals "1". To be done. This is because the output 80 of the multiplexer 78 is connected to the output 90 of the multiplexer 88, the output 90 of the multiplexer 88 is connected to the input terminal “1” of the multiplexer 78, and the generator 96 outputs each clock. It means that the output terminal 90 of the multiplexer 78 is connected to the input terminal "1" of the multiplexer 78 for receiving the increased value supplied to the multiplexer 78. After n clocks, the signal value in this case is "7", which is the same as when the maximum output of the generator 96 is "7". The maximum value "7" is maintained during the next two logic "1" values on the line L1. However, since the next control signal value is logic "0", the multiplexers 78 and 88 are switched. The output 80 of the multiplexer 78 is now connected to the input terminal "0" so that the value from the output 80 is decremented by one clock every clock count.
The output of the above generator 86 cannot be less than "0". Of course, the above process is repeated when another control signal having a logic "1" value is matched.

FIG. 3E illustrates the output value at the output 80 of the multiplexer 78, which is point D in the circuit. Since each line is processed as described above, it has the same value at the corresponding fulcrum.

The generators 86, 96 can be programmed to generate a slightly non-linear slope rather than an explicit linear one, e.g., they may be different increments or decrements for a given input value. Understand that it can be programmed to have

The operation of the vertical stretcher 38 will now be described with reference to Figures 3E and 3F. As indicated above, FIG. 3E shows the values of consecutive same lines starting from D, the input point of the vertical stretcher. The output 80 and the 1H delays 98-104 effectively form a vertical window such as W1 in FIG. 3E, which is one clock cycle wide and m + 1 line high. Scan across the above lines and then descend one line at a time and scan across the next line. In this embodiment,
The 1H delay device 98-104 and the adder 106 are "1" at the W1 position.
, Which is the value used in point 1 above, explicit for L1. Since the above four pixels are "0", the output of the adder 106 is the same as the value at L1 in FIG. 3E.

In the next scan, the window is one line below the vertical point indicated by W2 and the output of the adder 106 is the same as the value indicated by L2 in Figure 3F. Due to the continuous scanning of the window, the resulting signal values are the same as those shown in Figure 3F. For illustration purposes, one has to consider what the output of the adder 106 would look like, starting at the point of the quadrangle W1 and vertically separating one line at a time. The values obtained above are those of the first column affected by the expander of the present invention. At successive vertical fulcrums, the matching of values into the above window increases by 1 until the maximum value is "5". In the next stage, the lowest pixel in the window will be "0",
A value of "4" is generated.

From the values in Figure 3E, it is clear that the combination of values in the above window increases as the window moves from the left to the center and decreases further toward the right, as clearly shown in Figure 3F. . It is also clear that the combination of the above values increases as the window goes down the line in Figure 3E and further down the fulcrum.

The maximum value “35” emphasized by the square 110 in FIG. 3F refers to the position of the original control signal of the square 108. After the original control signal, it generates a phase in which n clock counters (6 in this embodiment) and m lines (4 in this embodiment) are combined. The above value "36" can be made to occur at the same time as video by inserting an appropriate matching delay in the video signal path.

FIGS. 4A to 4E illustrate the signal values produced by the control signal expander of FIG. 3 in response to a series of mutually different series of control signal pulses explicit in FIG. 4A. However, there are the following differences. Figures 3A-3F show the future sample by moving to the right and down, while Figures 4A-4E show moving to the left and up. There are only two other perceptions in the same situation.

The line expander 36 is a fifth circuit for explaining other circuits.
It will be described with reference to the drawings. The components and points in the circuit of FIG. 5 are designated by the same reference numerals in FIG. The important difference is the PROM
110 is programmed to perform the functions of the above generator 86 and multiplexer 78 and PRON.
112 is to be programmed to perform the functions of generator 96 and multiplexer 88 above. The table of FIG. 5A illustrates the operation of the circuit of FIG. 5 in response to the "0" and "1" control signal values shown at terminal 76 of multiplexer 78 in FIG. This circuit expands the line signal in a manner basically similar to the circuit explicitly shown in FIG. 3, so that further explanation is not required for those having ordinary knowledge in the technical field of the present invention.

Although some specific embodiments of the present invention have been described, means other than those explicitly set forth herein will be apparent to those of ordinary skill in the art of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows that a control signal indicating movement is expanded in order to obtain a good chromaticity image from a signal transmitted by the standard NTSC system.
FIG. 2 is a block diagram of a TV apparatus, FIG. 2 is a block diagram of a control signal expander constructed according to the present invention, FIG. 3 is a circuit of an embodiment of the present invention, and FIGS. 3A to 3F are specific points in FIG. Shows the signal values appearing in Fig. 3, Fig. 3C is a diagram explaining the operation when the positions of the horizontal and vertical stretchers are inverted, and Figs. 4A to 4E are the end control signals clearly shown in Fig. 4E. FIG. 5 each uses a PROM in place of the multiplexer shown in FIG. 3 to show the signal value generated at the same particular point in FIG. 3 as calculated to derive the value. FIG. 5A is a table showing the line signal expander, and FIG. 5A is a table for explaining the switching function of FIG. 10,30 ... Terminal, 12 ... Motion detector, 14 ... Signal expander, 16 ... k
Value generator, 18, 20 ... Soft switch, 22, 26 ... Matching delay circuit, 24 ... Frame comb filter, 28 ... Line comb filter, 30 ... Terminal, 32 ... Horizontal expander, 34 ... Vertical expander,
36 ... Line signal expander, 38 ... Vertical signal expander, 40 ... Time expander, 44 ... Input terminal, 46, 48, 50, 52, 54, 56, 94 ... Clock delay device, 58, 72 ... OR gate , 60,74,76 ... Output terminal, 64,66,68,70,98,100,102,104 ... 1H delay device, 78,88 ...
Multiplexer, 80, 90 ... Output, 82, 92 ... Switching control input, 84 ... Delay element, 86, 96 ... Generator, 106 ... Adder, 108, 110 ... Square, 112 ... PROM.

Claims (6)

[Claims] 1. A device for expanding a control signal generated along any one of a plurality of scanning lines, which comprises an input terminal (30) to which the control signal is applied; a line signal expansion means (36). ) And; vertical expansion means (38), which is coupled to the input terminal (30) and extends each control signal for a while along the line where it is generated to form an extended control signal ( 32) and a vertical expansion means (34) that repeats the line a predetermined number of times; the line signal expansion means (36) is connected to the expansion means (32, 34) to output the extended control signal on each line. Generating a ramp of increasing value during the first part and maintaining a maximum of that slope for the rest of the extended control signal and generating a ramp of decreasing value at the end of the extended control signal; The vertical expansion means (38) is coupled to the line signal expansion means (36). Including a combining means for combining the control signals received from the in-signal expanding means to derive a certain function of corresponding signal values along a plurality of lines. A device for stretching. 2. The control signal is a 1-bit signal, and the control signal expansion means (32, 34) comprises first and second circuits connected in series; the first circuit is an input terminal (44). And an output terminal (60),
N clock delay elements (46,48,52,5) connected in series
4) and each of which has n + 1 inputs connected to the input terminal (44) and an end of the clock delay element remote from the input terminal and an output (B) connected to the output terminal (60) An OR gate; and the second circuit has an input terminal (62) and an output terminal (74),
M line delay elements connected in series (64,66,68,70)
And the line delay elements (67, 66, 68, 70) separated from the input terminal (62) and the other input terminal of the second circuit, respectively.
2. An OR gate having m + 1 inputs connected to the ends of and a output (C) connected to the output terminal (74) of the second circuit. apparatus. 3. The control signal is a 1-bit signal and the line signal expansion output (36) is: an output (80) and a first multiplexer (78) having first and second inputs; A one-clock delay element (84) and a reducing means (86) in series between the output (80) of the multiplexer and the first input of the multiplexer, the reducing means (86) being a reference Has a value less than equal to the value,
One clock delay element (84) and reduction means (86); an output (88) and a second multiplexer (88) having first and second inputs; and an output (90) of the second multiplexer. 1-clock delay element (94) connected in series with its first input
And an increasing means (96), the increasing means (96) having a maximum value, a one-clock delay element (94) and an increasing means (96); an output of the first multiplexer (78) To a second input of the second multiplexer (88); and means for connecting the output of the second multiplexer (88) to the second input of the first multiplexer (78). The first multiplexer (78) has means for connecting its output (80) to its first input in response to a reference value and to connecting its output to its second input in response to a control signal. Means; said second multiplexer (88) connecting its output (90) to its second input in response to a reference value and its output to its first input in response to a control signal. The device according to claim 1 or 2, further comprising: 4. The control signal is a 1-bit signal and the line signal expansion means (36) comprises: an output (80) and a first PR having first and second inputs.
An OM (110); a one pixel delay (84) coupled between an output (80) of the first PROM (110) and a first input of the first PROM; an output (90) And a second PR having first and second inputs
OM (112); a one pixel delay (94) coupled between the output (90) of the second PROM (112) and its first input; the output of the first PROM (80 ) To the second input of the second PROM; and means for connecting the output (90) of the second PROM to the second input of the first PROM; The PROM (110) reduces the value appearing at the first input in successive clocks in response to a reference value until the reference value is reached, and outputs the second input (80) in response to the control signal value. And is programmed to connect to the output (90) of the second PROM; the second PROM (110) connects the output (90) to the second input in response to a reference value to provide a control signal value. In response, the increment value of the value appearing at the first input is generated and output at each clock count until the maximum value is reached, and the maximum value is held until the reference value is generated. Apparatus according to claim 1 or 2, characterized in that it is a ram. 5. The vertical extension means (38) comprises an input terminal coupled to the line signal extension means (36), the last-mentioned input terminal and a plurality of serially coupled to the coupling means (106). A one-line delay device (98,100,102,104) and the one-line delay device (9
Device according to at least one of claims 1 to 4, characterized in that it derives a signal which is a function of the signal appearing at the ends of (8,100,102,104). 6. The control signal expansion means (32, 34) repeats each bit of the control signal for n clocks and repeats each line m times; the line signal expansion means (36) comprises n clocks. Generate a ramp of increasing value during counting, hold the maximum for the rest of the extended control signal, and generate a ramp of decreasing value for r clocks after the end of the 1-bit control signal. Device according to at least one of claims 1 to 5, characterized in that the vertical expansion means (38) derives a function of the signals generated at corresponding clock counts along m + 1 lines. .