JPH07160656A - External interruption control method - Google Patents

Abstract

PURPOSE:To completely cope with the requests of various interruption processing functions to be required without drastically expanding functions in a communication close coupling multiprocessor system. CONSTITUTION:This method is provided with all or a part of a first interruption informing (control) function for selecting one optional CPU 1 as an interruption destination, a second interruption informing (control) function for selecting one specific CPU 1 specified beforehand as the interruption destination, a third interruption informing (control) function for selecting one specific CPU 1 specified by information accompanying an interruption request as the interruption destination, a forth interruption informing (control) function for selecting all the CPUs 1 excluding the specific CPU 1 specified by the information accompanying the interruption request as the interruption destinations and a fifth interruption informing (control) function for selecting all the CPUs 1 as the interruption destinations. Then, one of them is allocated for each interruption vector and executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an external interrupt capable of completely responding to various required interrupt processing function requests in a tightly coupled multiprocessor system for communication processing using a general-purpose microprocessor as an arithmetic core. It relates to a control method.

[0002]

2. Description of the Related Art Conventionally, since a processor for a communication processing device has been required to have high reliability and high real-time processing property, a dedicated machine based on an original architecture has been used. However, in recent years, with the spread and expansion of communication services, there has been a strong demand for economicization of communication processing devices, and it has been desired to apply general-purpose machines, which are expected to have economies of scale, to processors for communication processing devices. On the other hand, it is desired to improve the processing capability of the processor with the advancement of communication services, but it is difficult to meet these demands with a single processor configuration using a single general-purpose microprocessor. In a conventional communication processing processor, a loosely coupled multiprocessor (LCM) capable of distributing loads to a plurality of processors with a relatively small overhead.
Although the P) configuration has been mainly used, there is a problem that control by complicated software dedicated to LCMP is required. On the other hand, a tightly coupled multiprocessor (T
In the CMP) configuration, the main memory is shared by a plurality of CPUs, so the overall performance is C due to the access contention overhead.
There is a problem that the number of PUs is lower than the number of PUs, and it is not often used for communication processing.

However, due to the progress of packaging technology in recent years,
By mounting multiple general-purpose microprocessors on the board and using a high-speed internal bus, it is possible to reduce overhead and become practical in terms of processing capacity.
From the viewpoint of improving software productivity, application to communication processors has become promising and practical.
By the way, in the processor for communication processing, it is necessary to control an extremely large number of input / output devices, but since the interrupt control function built into the general-purpose microprocessor is not sufficient, an independent external interrupt control unit is added. I have to do it. In order to realize a TCMP configuration using a plurality of general-purpose microprocessors, the external interrupt control unit must also have an interrupt control function compatible with TCMP. Further, in order to realize high reliability and real-time property for communication processing, various functions are provided in peripheral circuits other than the general-purpose microprocessor, but the function of external interrupt is between those system control functions. It serves as a software interface. Therefore, the external interrupt control unit must also have an interrupt control function from the viewpoint of system control.

First, an external interrupt controller corresponding to the conventional single processor will be described. The source of external interrupts, the various system resources inside and outside the processor,
The external interrupt control unit is requested to generate an interrupt to the CPU via the bus or via individual signal lines. Here, in order to clarify this, it is referred to as an "interrupt request". The interrupt generation request is managed by the external interrupt control unit by assigning an individual vector number. Hereinafter, the interrupt control processing operation in the external interrupt control unit will be described in detail. The external interrupt control unit has an interrupt display (IR) flag and an interrupt mask (IM) flag for each vector. When an interrupt request is generated in any of the vectors and the IR flag corresponding to the vector is reset, an interrupt request is sent to the CPU via the interrupt signal line, and at the same time the IR flag corresponding to the vector is requested. Set. In the same case, if the IM flag is reset, the interrupt signal to the CPU is suppressed and IR
Only set flags. Here, for simplification of description, the difference in the operation depending on the state of the IM flag will not be individually described and will be collectively referred to as an interrupt request. While the IR flag is set, the next interrupt request for the vector is not accepted, and the next interrupt request to the CPU from the vector is also suppressed. The IR flag is reset by a reset request from software. After resetting the IR flag, it is possible to accept an interrupt generation request for the vector and request an interrupt from the vector to the CPU. The IM flag is set and reset at the request of software.

Software (interrupt processing program)
Uses the IM flag in connection with the selection of two interrupt control methods, the vector method and the polling method. That is,
In the case of the vector system, the IM flag corresponding to the vector is reset. When the external interrupt control unit notifies the CPU of the interrupt request, the control is transferred to the interrupt processing program by the CPU hardware. When the interrupt processing program finishes the interrupt acceptance processing, it resets the IR flag and enables the next interrupt acceptance. In the case of the polling method, the interrupt processing program is IM
Set the flag. The interrupt processing program reads the IR flag at any time and detects an interrupt when the IR flag is set. When an interrupt is accepted, the IR flag is reset and the next interrupt can be accepted. Next, an interrupt control method in the conventional TCMP will be described. As the external interrupt control method in TCMP, a centralized method in which interrupts are concentrated on a fixed CPU and the interrupt processing by the interrupt processing program is centrally processed by the CPU, is specified for each data channel unit and input / output controller unit. Of the CPU to which the interrupt notification destination is set in advance, or the identification information of the CPU that issued the input / output command is stored in the data channel unit or the input / output controller unit, and the input / output command is issued. One of the activation source notification methods has been performed to distribute the interrupt processing load by interrupting the original CPU. A method for realizing these methods in the external interrupt control unit will be described below.

FIG. 3 is a diagram showing a configuration example of a tightly coupled multiprocessor system according to a centralized system among conventional interrupt control systems, and FIG. 4 is a diagram showing a configuration example of a tightly coupled multiprocessor system according to the fixed distribution system, FIG. 5 is a diagram showing an example of the configuration of a tightly coupled multiprocessor system according to the activation source notification method, FIG. 6 is a schematic operation flowchart of the interrupt notification operation of the external interrupt control unit according to the centralized method in FIG. 3, and FIG. 6 is an operation flowchart of the external interrupt control unit according to the fixed distribution method and the activation source notification method in FIG. First, in the centralized system, as shown in FIG. 3, the external interrupt control unit 4 is provided with only one set of interrupt request signal lines 11 to the CPU 1, and the same operation as a single processor is performed only with a specific CPU 1. It is realized by. In addition, 10 is a tightly coupled multiprocessor system, 2 is a main memory unit, 6 is an external resource (I
O, etc.), 5 is a system bus, 3 is a memory bus, 13 is an individual line interrupt signal, 12 is a bus command interrupt signal, and 14 is a bus command interrupt signal.
Is a software controlled interrupt signal. In this case,
As shown in FIG. 6, when an interrupt request is received (step 601), vector allocation is performed (step 60).
2) Interrupt a specific CPU (step 60)
3).

Next, in the fixed distribution system, as shown in FIG. 4, an interrupt signal line 11 from the external interrupt control unit 4 to each CPU 1 is individually provided. Furthermore, the data channel unit and the input / output controller unit are provided with a register for storing the interrupt notification destination CPU, and when the interrupt request is issued, the external interrupt control unit 4 is notified as attached information, and the external interrupt control unit 4 is based on the information. This is achieved by selecting the interrupt destination by In this case, as shown in FIG.
When the interrupt request is accepted (step 701), vector allocation and CPU designation information are extracted (step 7).
02), interrupt the designated CPU (step 70)
3). Next, as shown in FIG. 5, the activation source notification method is the same as the fixed distribution method, and the individual interrupt signal line 11 to each CPU 1 and the interrupt notification destination CPU to the data channel unit and the input / output controller unit A register or the like for storing is provided. Then, it stores the interrupt notification destination CPU information accompanying the input / output instruction issued from the CPU 1, notifies the external interrupt control unit 4 of the information in association with the interrupt generation request, and the external interrupt control unit 4 notifies the information. This is realized by selecting the interrupt destination based on Also in this case,
As shown in FIG. 7, when an interrupt request is received (step 701), vector allocation and CPU designation information are extracted (step 702), and the designated CPU is interrupted (step 703). Note that as a conventional document, for example, "Multiprocessor and parallel processing" Philip H Ensl
ow. Jr supervised, translated by Yoichiro Muraoka, and described in the section "Configuration of Multi-processor Operating System" (pp85-89) in Chapter 3 published by Modern Science Co., Ltd. in September, 1976.
Further, for example, it is described in the background and problems in the interrupt processing method of Japanese Patent Publication No. 5-33414.

[0008]

The interrupt control function performed by the conventional external interrupt control unit for TCMP has the following problems. First, in the centralized system, in an application such as a communication process in which the load of interrupt processing is large, one specific CPU may become a bottleneck in the processing capacity of the entire TCMP. Not suitable for (communication control processing). Next, in the fixed distribution method, since it is necessary to assume the load of the data channel unit and the input / output controller unit and allocate them to each CPU in advance, if the actual load situation is different from the expected one, effective load distribution can be performed. There is a problem that there is no. Since the load generally changes dynamically when the processor is actually operated, it is considered that the fixed distribution method cannot achieve sufficient load distribution. Next, the activation source notification method is one solution for dynamically distributing the interrupt processing load.
Regarding the CPU, it is necessary to have a function of adding CPU identification information to the input / output instruction, a function of specifying the CPU and generating an interrupt for the data channel section and the input / output controller section for recognizing the input / output instruction. That is, there is a problem that not only the external interrupt control unit but also the functions of the entire system need to be expanded. This is the first problem to be solved by the present invention.

Next, consider the system control interrupt. The system control interrupt is used for factors such as failure detection in various peripheral circuits, firmware startup and termination, inter-CPU communication, and periodic processing timer for real-time control. In the failure detection interrupt, when the detection source resource is common to the CPU such as the main storage unit, in principle, any one CPU may perform the interrupt processing. When used individually, it must be done individually by the corresponding CPU.
Further, there are two types of firmware, one for operating the CPU common resource and one for operating the CPU individual resource. The former can be run by any CPU, but the latter is designated by the CPU. Need to drive in. The inter-CPU communication provides a synchronization function between software running in parallel on different CPUs, and there are two types of communication modes, one-to-one and one-to-many. Also,
The periodic processing timer is for giving a trigger for activating software to be periodically executed at a constant cycle, and in order to perform load distribution in all CPUs in order to improve real-time performance,
It is necessary to generate an interrupt from the periodic processing timer to all CPUs at the same time. As described above, for system control in TCMP, it is necessary not only to issue an interrupt notification to one CPU as in the conventional case, but also to use various interrupt notification forms. This form cannot be dealt with by the conventional external interrupt control unit. This is the second problem to be solved by the present invention. An object of the present invention is to solve both the first and second problems of the related art, and in a tightly-coupled multiprocessor system for communication processing in which a general-purpose microprocessor is used as an arithmetic core, without expanding the function of the entire system. An object of the present invention is to provide an external interrupt control method capable of perfectly corresponding to various required interrupt processing function requests.

[0010]

In order to achieve the above object, according to the external interrupt control method of the present invention, an individual interrupt signal line is provided from the external interrupt control unit to each CPU as in the case of the activation source notification method. , Various interrupt notification means are provided in the external interrupt control unit, and a single CPU or a plurality of CPUs are provided as necessary.
Allows external interrupts to be requested. In detail, (a) In the input / output interrupt processing, in principle, the input / output instruction is not restricted by the issuer and can be executed by an unspecified CPU.
Therefore, there is no problem even if the external interrupt control unit selects an arbitrary CPU and makes an interrupt at the time of generation of an interrupt request from the data channel unit or the input / output controller unit. If the external interrupt control unit independently selects the interrupt destination CPU for each vector, load distribution can be realized. In order to solve the first problem, according to the present invention, a first interrupt notification (control) for determining an interrupt destination CPU by arbitrarily selecting from a plurality of CPUs configuring TCMP in an external interrupt control unit.
Provide a function. (B) In fault detection interrupt processing, load distribution is not necessary because it does not occur as frequently as I / O interrupts. However, since it is necessary to perform priority control of processing according to the seriousness of the failure, it is possible to set and change the interrupt destination CPU by software. For this reason, in the present invention, a register for setting an interrupt destination CPU from software and an interrupt notification to the corresponding CPU based on the setting value of this register, or a C such as a monitoring timer.
A second interrupt notification (control) function of interrupting only a predetermined ICPU is provided so that an interrupt notification is sent only to the CPU when a failure is detected for each PU.

(C) For the start interrupt of the firmware whose operation target is the CPU common resource, the above-mentioned first or second interrupt notifying means can be used. CPU
For firmware activation interrupts that operate on individual resources, the CP specified by the firmware activation request source
Since it is necessary to generate a start interrupt to U, a third interrupt notification (control) function for identifying the CPU designation information from the start request source and notifying the CPU of the interrupt is provided. (D) The conventional software control interrupt is applied to the communication between the CPUs. That is, when the software executes a specific instruction, the interrupt generation request can use the second interrupt notification means as an external interrupt. For one-to-many CPU-to-CPU communication, it is necessary to notify all other CPUs of the interrupt, except for the specific instruction execution source CPU, and the interrupt processing is executed individually by each CPU in parallel. Needs to be done. In the present invention, a fourth interrupt notification (IR interrupt and IM flag are provided for each CPU individually, the software control interrupt generation instruction executing CPU is identified, and an interrupt request is simultaneously issued to all CPUs other than the CPU ( Control) function. (E) The cycle processing timer is commonly used for all CPUs,
The periodic processing needs to be distributed and executed by each CPU.
According to the present invention, a fifth interrupt notification (control) function is provided in which a plurality of IR flags and IM flags are provided for each CPU, and an interrupt generation request from one cycle processing timer is distributed to all CPUs, and an interrupt request is made simultaneously. To provide.

[0012]

In the present invention, at the time of designing a processor or a communication processing system, factor allocation for each vector and setting of any of the first to fifth interrupt notification means are performed. The operations of the input / output interrupt processing and the periodic processing timer interrupt processing will be described below. Since the other processes are self-explanatory, the description thereof will be omitted.
First, regarding the vector to which the I / O interrupt factor corresponds,
As described above, the setting using the first interrupt notification means is performed. When the interrupt request is notified to the external interrupt control unit after the operation of the system is started, the external interrupt control unit receives a plurality of Cs.
An arbitrary CPU is selected from PU, an interrupt signal to the CPU is activated, and an interrupt request is notified. The CPU that has received the interrupt signal acquires the vector information associated with the interrupt request from the external interrupt control unit and activates the corresponding interrupt processing software. After acquiring other necessary interrupt-related information, the interrupt processing software resets the IR flag corresponding to the vector in the external interrupt control unit, and thereafter executes the main body of interrupt processing. After resetting the IR flag, the external interrupt control unit
The interrupt request can be accepted again. If necessary for interrupt processing, the interrupt processing software may set the IM flag only during a necessary period to suppress the generation of the next interrupt request from the external interrupt control unit.

Next, as to the vector corresponding to the periodic processing timer factor, the setting using the fifth interrupt notifying means is performed as described above. After the start of system operation, when an interrupt request is notified to the external interrupt controller, the external interrupt controller makes the interrupt signals to all CPUs active and notifies the interrupt request. Each CPU that receives the interrupt signal acquires the vector information associated with the interrupt request from the external interrupt control unit and activates the corresponding interrupt processing software. After acquiring other necessary interrupt-related information, the interrupt processing software resets the IR flag of the own CPU corresponding to the vector in the external interrupt control unit, and thereafter executes the main body of interrupt processing. I
After resetting the R flag, the external interrupt control unit
For U, the interrupt generation request can be accepted again.
If necessary for interrupt processing, the interrupt processing software
Set the IM flag for each CPU for the required period,
The generation of the next interrupt request to the own CPU from the external interrupt control unit may be suppressed.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block configuration diagram of a tightly coupled multiprocessor system to which the present invention is applied, and FIG. 2 is an operation flowchart of an external interrupt control unit when using the first to fifth interrupt notification means of the present invention. Yes, Figure 8
FIG. 3 is a specific configuration diagram of an external interrupt control unit showing an embodiment of the present invention. In FIG. 1, the same symbols as those in FIGS. 3 to 5 indicate the same things. Reference numeral 12 is a bus command interrupt signal, 13 is an individual line interrupt signal, and 14 is a software control interrupt signal. In FIG. 2, the external interrupt control unit 4
Receives an interrupt request (step 20)
1) Correlating vector numbers and extracting CPU designation information (step 202), selecting an interrupt notification means from the set contents for each vector (step 203), activating the first interrupt notification means and activating any CPU 1. An interrupt is made (step 204). Alternatively, the second interrupt notification means is activated to interrupt the CPU designated by the interrupt control mode register (step 205). In the same way, the third
~ The fourth interrupt notification means is activated to execute an interrupt. Then, the fifth interrupt notification means is activated,
All CPUs are interrupted (step 207).

As shown in FIG. 8, the external interrupt control unit 4
Is an interrupt generation request receiving unit 41 that receives various interrupt generation requests and allocates vectors, and an interrupt that generates an interrupt request according to the setting of the interrupt notification unit for each vector under the control of the interrupt generation request receiving unit 41. Request generation unit 40,
An interrupt control mode register 44 for setting by software which of the first to fifth interrupt notification means to be used for each vector, an IR flag 45, and an IM flag 4
6, and a memory bus interface unit 42 that processes access from the CPU and external common resources.
It has and. The control mode register 44 is
Since it is provided in the storage unit 43, it is not shown in FIG. Interrupt destination C in the second interrupt notification means
The register for setting the PU is assigned as one field of the interrupt control mode register 44. The interrupt request is a bus command interrupt 12 notified from the external resource (IO) 6 to the external interrupt control unit 4 via the system bus 5 shown in FIG. 1, and also from the CPU 1 to the external interrupt control unit 4 via the memory bus 3. Of the software control interrupt 14 and the individual line interrupt 13 by the individual signal line directly connected to the interrupt generation request receiving unit 41.

FIG. 9 is a diagram showing a detailed configuration example of the interrupt control mode register in the present invention. The interrupt control mode register 44 is provided in the storage unit 4 as described above, and includes the following fields 440 to 443. That is, FM 440 is a field for designating a flag configuration, RM 441 is a field for designating a selection method of an interrupt destination CPU, CM 442 is a field for designating a flag control method, and PI 443 is a CPU designation field. The memory bus interface unit 42 in FIG. 8 provides a function for software to access the interrupt control mode register 44. The software needs to set this register 44 according to the external interrupt event for each vector before starting the acceptance of the external interrupt. Hereinafter, the external interrupt control operation by the external interrupt control unit 4 will be described in detail. FIG. 10 is a diagram for explaining the operation for each flag configuration in the present invention. FM field 4 of the interrupt control mode register 44 corresponding to a certain vector
When the setting of 40 is a value indicated by the symbol S, each of the interrupt generation request receiving unit 41, the interrupt request generation unit 40, and the memory bus interface unit 42 has a storage unit 43.
Allocate only one set of the IM flag 46 and the IR flag 45 in the vector. As a result, the first flag configuration is realized. In exactly the same way, FM field 44
When the setting of 0 is the value indicated by the symbol H, each unit in the external interrupt control unit 4 has a plurality of sets of I corresponding to the number of CPUs.
The R flag and IM flag are assigned to the corresponding vector.
As a result, the second flag configuration is realized. Similarly, when the setting of the FM field 440 is a value indicated by the symbol M, each unit in the external interrupt control unit 4 is
Similar to the second flag configuration, a plurality of sets of IR flags and I
The M flag is assigned to one set corresponding to the CPU. As a result, the third flag configuration is realized.

11 to 14 are diagrams showing examples of various interruption notifying means in the present invention. In this embodiment, the five types of interrupt notification (control) functions of the first to fifth types are
FM field 440 of interrupt control mode register 44
Is specified by the combination of the operation specified by and the operation specified by the RM field 441. As shown in FIG.
When the RM field 441 has a value designated by the symbol A, the interrupt request generation unit 40 selects an arbitrary CPU from the plurality of CPUs and gives an interrupt notification. In FIG. 11, the FM field 440 has the set value S and the RM
The operation when the setting value A of the field 441 is set is shown. FIG. 12 shows the operation when the FM field 440 is the set value S and the RM field 441 is designated by the symbol B. In this case, the interrupt request generator 40 sends an interrupt notification to the CPU designated by the PI field 443. FIG. 13 shows the operation when the FM field 440 is the set value H and the RM field 441 is designated by the symbol C. In this case, the interrupt request generation unit 40 sends an interrupt notification to all CPUs other than the CPU that is the source of the interrupt generation request. In FIG. 14, the FM field 440 has the set value H, and the RM
The operation when the field 441 is designated by the symbol D is shown. In this case, the interrupt request generation unit 40 sends an interrupt notification to all CPUs.

As apparent from FIGS. 11 to 14, the first
The interrupt notification (control) function of is realized when the FM field 440 is S or H and the RM field 441 is A. The second interrupt notification (control) function is realized by setting the identification number of the interrupt destination CPU in the PI field 443 in advance when the FM field 440 is S or H and the RM field 441 is B. It Further, when the FM field 440 is S or H and the RM field 441 is B, the third interrupt notification means causes the interrupt generation request receiving unit 41 to determine the PI field 44 based on the CPU designation information accompanying the interrupt generation request.
It is realized by setting 3 in advance. Further, the fourth interrupt notification (control) function is that the FM field 440 is S
Alternatively, it is realized when the H and RM fields 441 are C. Further, the fifth interruption notifying means is realized when the FM field 440 is M and the RM field 441 is D. FIG. 15 shows first to fifth interrupt notifications (control)
It is a figure which shows the setting of the interrupt control mode register for implement | achieving a function.

16 to 19 are views showing an example of the flag control method according to the present invention. The flag control method is the FM field 440 of the interrupt control mode register 44,
And the CM field 442 specify the combination of operations. Here, four types of flag control methods are shown. In FIG. 16, the FM field 440 is S
And the operation of the memory bus interface section when the CM field 442 is designated by the symbol I is shown. In this case, the memory bus interface unit 42
However, only the setting and resetting of the IM flag and the resetting of the IR flag from the interrupt request destination CPU are valid. Further, FIG. 17 shows the operation of the memory bus interface unit when the FM field 440 is designated as H or M and the CM field 442 is designated by the symbol I. In this case, the memory bus interface unit 4
2 identifies the access request source CPU, and sets and resets only the flag assigned to the CPU to be valid. That is, in the figure, the access request source CPU0, IRi, IMi of the vector to which IR0, IM0 is allocated
Access request source CPUi, I of the vector to which is allocated
By identifying the access request source CPUn of the vector to which Rn and IMn are assigned, the C
The operation is valid only for the flag assigned to the PU.

Further, in FIG. 18, the FM field 440
Is S and the CM field 442 is designated by the symbol II, the operation of the memory bus interface section is shown. In this case, the memory bus interface unit 42
Enables the setting and resetting of the IM flag and the resetting of the IR flag from any CPU. In the figure, the IM flag and IR flag from the CPUi are set or reset. Further, in FIG. 19, the FM field 440 is H or M, and the CM field 442 is
The operation of the memory bus interface unit is shown when is designated by the symbol II. In this case, the memory bus interface unit 42 enables the setting and resetting of the IM flags collectively assigned to each CPU and the resetting of the IR flags collectively from any CPU. In the figure, CPU0 and IR to which IR0 and IM0 are assigned
CPUi to which i, IMi are assigned, and IRn,
The IMn and the IR flag are effectively set and reset from the CPUn to which the IMn is assigned.

In vector-based interrupt processing, the interrupt processing software uses an I
The M flag is turned on, and then the IR flag is reset so that the external interrupt control unit 4 can accept the next interrupt generation request. The IM flag is turned off when it is no longer necessary to prevent interruption by the interrupt handling software. In order to support the method of this embodiment, software needs to set the CM field to I regardless of the FM field. In the polling type interrupt processing, the IM flag is initially set to ON in advance, and the interrupt processing software refers to the IR flag,
If it is set, it accepts an interrupt so that the external interrupt controller 4 can accept the next interrupt request.
Reset the IR flag. In order to correspond to the method of this embodiment, the software sets the CM field to II and the FM field to H or M when the FM field is S.
In this case, it is necessary to set the CM field to I under the condition that each CPU turns on the individual IM flag in advance. When the FM field is H or M, each CPU is basically limited to the flag operation of its own CPU. Therefore, even if the interrupt processing software finds an inconsistency of an interrupt related to another CPU, There is no way to unlock it. FM field is H or M
So, the function of CM field II is C in such a case.
A function of collectively resetting the IM flag and IR flag of each PU is provided.

Finally, a method of designating the first to fifth interrupt notification functions will be described. Specific allocation of the interrupt factor for each vector and allocation of the first to fifth interrupt notification means are determined for each communication processing system to which the tightly coupled multiprocessor is applied at the time of designing the system.
Regarding the bus command interrupt, whether or not a certain input / output device is used in a communication processing system, which vector is allocated to be used, and which of the first to fifth interrupt notification means is applied is At the time of designing various control units of the communication processing system, all or part of the vectors are selected and wired at the time of manufacturing. Regarding interrupt factors common to all communication processing systems, at the time of manufacturing the tightly coupled multiprocessor. Then, the vector and the interrupt factor are assigned in such a manner that the interrupt factor is connected to the interrupt factor, and the individual interrupt factors for each communication processing system are connected at the time of manufacturing the communication processing system. As a result, which of the first to fifth interrupt notification functions is to be applied can be determined at the time of designing the communication processing system, like the bus command interrupt. In any case, according to the allocation of the interrupt notification means determined at the time of designing the communication processing system, the software initializes the interrupt control mode register at the time of starting the communication processing system, thereby interrupting each vector. It is possible to specify the notification means. It should be noted that the vector assignment and the assignment of the interrupt notification means can be fixedly designated by wiring at the time of manufacturing the external interrupt control unit if they are common due to the interrupt factor that is common to the communication processing systems.

[0023]

As described above, according to the present invention,
In a tightly-coupled multiprocessor system for communication processing using a general-purpose microprocessor as an arithmetic core, it is possible to completely meet the demands of various necessary interrupt processing functions without expanding the functions of the entire system.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a tightly coupled multiprocessor system to which the present invention has been applied.

FIG. 2 is an operation flowchart showing an example of an interrupt notification operation of an external interrupt control unit in FIG.

FIG. 3 is a diagram showing a configuration example of a tightly coupled multiprocessor system by a centralized method among conventional interrupt control methods.

FIG. 4 is a diagram showing a configuration example of a tightly-coupled multiprocessor system according to a fixed distribution method among conventional interrupt control methods.

FIG. 5 is a diagram showing a configuration example of a tightly coupled multiprocessor system according to a boot source notification method of the conventional interrupt control methods.

FIG. 6 is an operation flowchart of an interrupt notification operation of the external interrupt control unit by the centralized method in FIG.

FIG. 7 is a flowchart of an interrupt notification operation of the external interrupt control unit according to the fixed distribution method and the activation source notification method in FIGS. 5 and 6.

FIG. 8 is a configuration diagram of an external interrupt control unit showing an embodiment of the present invention.

FIG. 9 is a diagram showing a configuration example of an interrupt control mode register in the present invention.

FIG. 10 is an explanatory diagram showing operations according to flag configurations of the present invention.

FIG. 11 is an operation explanatory diagram in the case of a first combination of interrupt notification means according to the present invention.

FIG. 12 is likewise an operation explanatory diagram in the case of a second combination of interrupt notification means in the present invention.

FIG. 13 is an operation explanatory diagram of a third combination of interrupt notification means according to the present invention.

FIG. 14 is likewise an operation explanatory diagram in the case of a fourth combination of interrupt notification means in the present invention.

FIG. 15 is a diagram showing a method of setting an interrupt control mode register that realizes various interrupt notification means in the present invention.

FIG. 16 is an operation explanatory diagram in the case of the first combination of flag control methods in the present invention.

FIG. 17 is an operation explanatory diagram of the second combination of flag control methods.

FIG. 18 is an operation explanatory diagram of the third combination of flag control methods.

FIG. 19 is an operation explanatory diagram similarly in the case of a fourth combination of flag control methods.

[Explanation of symbols]

 1 CPU 2 Main memory unit (MM) 3 Memory bus 4 External interrupt control unit 5 System bus 6 CPU common external resource (IO etc.) 10 Tightly coupled multiprocessor system 11 Interrupt request signal line 12 Bus command interrupt signal 13 Individual line interrupt signal 14 Software Control Interrupt Signal 40 Interrupt Request Generation Unit 41 Interrupt Generation Request Reception Unit 42 Memory Bus Interface Unit 43 Storage Unit 44 Interrupt Control Mode Register 45 Interrupt Display (IR) Flag 46 Interrupt Mask (IM) Flag 440 Flag Configuration Mode (FM) Field 441 Interrupt notification mode (RM) field 442 Flag control mode (CM) field 443 CPU designation (PI) field

Claims (1)

[Claims] 1. In a tightly coupled multiprocessor system, a first external interrupt control process for selecting an arbitrary 1CPU as an interrupt destination and a second external interrupt control process for selecting a specific 1CPU designated in advance as an interrupt destination. And a third external interrupt control process for selecting a specific 1CPU designated by the information accompanying the interrupt request from the activation request source as the interrupt destination, and a specific 1C designated by the information accompanying the interrupt request.
Fourth, selecting all other CPUs except PU as interrupt destinations
Of the external interrupt control processing of No. 1 and the fifth external interrupt control processing of selecting all the CPUs as the interrupt destinations and assigning one of them to each interrupt vector, and executing the assigned external interrupt control processing. Characteristic external interrupt control method.