JPH07160219A - Device for driving planar display device - Google Patents

Abstract

PURPOSE:To provide an inexpensive planar display device with less power consumption whose beakdown strength is lower and capable of performing high speed line sequentiality scan and recovering power. CONSTITUTION:This device is a device for driving a planar display device constituted so that in a driving device for an AC type planar display device constituted of electrodes group arranged in matrix, push-pull type driver circuits 101 constituted of two transistors TR6, TR7 are provided on respective two power source line pair connected to the driver circuit driving plural display electrodes to be scanned, and a power source circuit means 70 applying a prescribed voltage to one side power source line (FVH, FLG) connected to individual driver circuits and a leakage control switch means 80 leaking the prescribed voltage applied to the power source line are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device for a flat display device and a driving method thereof, and more particularly,
The present invention relates to a driving device of a flat panel display device capable of realizing a high-speed line-sequential scanning method with low power consumption and low cost in a flat panel display device.

[0002]

2. Description of the Related Art In recent years, PRT has been replaced by CRT due to its thinness.
The demand for flat matrix display devices such as DP (plasma display), LCD (liquid crystal display), and EL (electroluminescence) is increasing, but recently, the demand for color display is increasing.

Conventionally, a flat display device, that is, a flat display device, which has been typified by a plasma display device, an electroluminescence display (EL) device, etc., has a small depth and a large display screen. Therefore, its use is expanding rapidly and the production scale is increasing. By the way, the flat display device concerned is
Generally, the electric charge accumulated between the electrodes is discharged and emitted under a predetermined voltage to display, and its general display principle is described by taking a plasma display device as an example. A brief description will be given below.

That is, a well-known plasma display device (AC type PDP) uses a two-electrode type for performing selective discharge (address discharge) and sustain discharge with two electrodes, and a third electrode. There is a three-electrode type in which the address discharge is performed. On the other hand, in a plasma display device (PDP) that performs color display, the phosphor formed in the discharge cell is excited by the ultraviolet rays generated by the discharge.
This phosphor has a drawback that it is vulnerable to the impact of ions, which are positive charges simultaneously generated by discharge. In the above-mentioned two-electrode type, since the phosphor directly hits the ions, the life of the phosphor may be shortened.

In order to avoid this, a color plasma display device generally uses a three-electrode structure utilizing surface discharge. Further, also in this three-electrode type, when the third electrode is formed on the substrate on which the first and second electrodes for sustaining the third electrode are arranged,
In some cases, the third electrode is arranged on another substrate that faces the third electrode.

Further, even when the above-mentioned three kinds of electrodes are formed on the same substrate, the third electrode is arranged on the two electrodes for sustaining discharge and the third electrode is arranged below the third electrode. There is a case. Furthermore, the visible light emitted from the phosphor is
There are cases where the light is seen through the phosphor and there are cases where the light is reflected from the phosphor.

Since the principles of the plasma display devices of the respective types described above are the same as each other, in the following, the first substrate provided with the first and second electrodes for sustaining discharge and the first substrate will be described. Separately, a specific example will be described for a flat panel display device configured by forming a third electrode on a second substrate facing the first substrate. That is, FIG. 3 is a plan view showing a configuration of an example of a conventional flat panel display device.

In the figure, a display panel 1 is a schematic plan view showing an outline of the configuration of the above-mentioned three-electrode type plasma display device (PDP), and FIG. 4 is a view showing the plasma display device of FIG. One discharge cell 1 formed
It is a schematic sectional drawing in 0. That is, the plasma display device is composed of two glass substrates 12 and 13, as can be seen from FIGS. 3 and 4. The first substrate 13 comprises a first electrode (X electrode) 14 and a second electrode (Y electrode) 15 which are arranged in parallel with each other and act as sustain electrodes, which are dielectric layers 18 It is covered with.

Further, a coating film 21 made of a MgO (magnesium oxide) film or the like is formed as a protective film on the discharge surface composed of the dielectric layer 18. On the other hand, on the surface of the second substrate 12 facing the first glass substrate 13,
Electrode 16 acting as third electrode or address electrode
Are formed so as to be orthogonal to the sustain electrodes 14 and 15.

On the address electrode 16, red, green,
The discharge space 2 in which the phosphor 19 having one of the blue emission characteristics is defined by the wall portion 17 formed on the same surface as the surface of the second substrate 12 on which the address electrode is arranged
It is located within 0. That is, each discharge cell 10 in the plasma display device is partitioned by the wall (barrier).

Further, in the plasma display device in the above specific example, the first electrode (X electrode) 14 and the second electrode (Y electrode) 15 are arranged in parallel with each other. The second electrodes (Y electrodes) 15 that form a pair are individually driven by individual Y electrode drive circuits 41 to 4n connected to the Y electrode drive common driver circuit 3, The first electrode (X electrode) 14
Form a common electrode and are driven by one driver circuit 5.

Address electrodes 16-1 to 16-m are arranged orthogonally to the X electrode 14 and the Y electrode 15,
The electrodes 16-1 to 16-m at the address are connected to an appropriate address driver circuit 6. In such a conventional flat display device, the address electrodes 16 are connected to the address driver 6 one by one, and the address pulse at the time of address discharge is applied to each address electrode by the address driver 6.

The Y electrodes 15 are individually connected to the Y scan drivers 41 to 4n. The scan drivers 41 to 4n are further connected to the Y-side common driver 3, and the pulse at the time of address discharge is the scan driver 41.
4n, the sustain discharge pulse and the like are generated in the Y side common driver 33, and the Y scan drivers 41 to 4n are generated.
Is applied to the Y electrode 15 via.

On the other hand, the X electrodes 14 are commonly connected and driven over all display lines of the panel in the flat display device. That is, the common driver 5 on the X electrode side generates a write pulse, a sustain pulse, and the like, and simultaneously applies these to each Y electrode 15. These driver circuits are controlled by a control circuit (not shown), and the control circuit is controlled by a synchronizing signal and a display data signal input from the outside of the device.

On the other hand, the common driver 5 on the X electrode side and the common driver 3 on the Y electrode side in this example are connected to an appropriate control circuit (not shown), and the X electrode 14 and the Y electrode 15 are connected to each other. The sustain discharge described above is executed by driving all at once while inverting the polarities of the voltages applied alternately. As described above, the display panel 1 in the conventional flat display device has the above-mentioned sustain discharge cell unit 10
Are arranged in a matrix in the horizontal direction and m in the vertical direction, and the Y-side scan driver circuit 4
Reference numeral 1 is for driving the Y electrodes connected to the sustain discharge cell portions 10 arranged at the top in the vertical direction and m in the horizontal direction. Similarly, from each Y-side scan driver circuit 42, 4n individually drives the Y electrodes which are the corresponding scan display lines.

On the other hand, the drive circuit 5 on the X electrode side is arranged in parallel with all the Y electrodes, but since it constitutes a common electrode, one X electrode driver circuit 5 is therefore provided. The X electrode is driven by only.
A method of driving the above-described conventional flat panel display device will be described with reference to FIGS.

That is, the display operation is executed by dividing the display period S of one frame into the scan address period S-1 and the sustain discharge period S-2. In the scan address period, the Y electrode side scan driver circuit 41 outputs Y
While supplying a scanning signal to the electrode 15-1, the address driver circuit 6 causes the address electrodes 16-1 to 16-m.
A signal corresponding to the display data of the first line formed by the Y electrode 15-1 is supplied using the address pulse AP, the cell portion 10 to be displayed is temporarily discharged, and a predetermined wall charge is generated. It is deposited in the cell portion and exhibits a memory function.

In the same manner, the Y electrode side scan driver 4
Each of the Y electrodes 15-2 to
Data to be displayed is written in a predetermined cell portion by sequentially scanning up to 15-n. When the scan address period S-1 is completed, the sustain discharge period S-2 is started, and the Y electrode side common driver circuit 3 and the common electrode driver circuit 3 are provided for all the cell parts 10 constituting the display panel. X
By the common driver circuit 5 on the electrode side, the Y electrode 15-1
15-n and the electrode of the cell portion 10 formed at the portion where the Y electrode 14 intersects, a predetermined voltage Ysus is applied at the same time.
Then, the polarity of the voltage is reversed and the same voltage application operation Xsus is performed to alternately apply the voltage between the electrodes of the cell portion 10.

At this time, the display data is applied in the scan address period, and the cell portion 1 having a predetermined wall charge.
Only 0 will be repeatedly emitted a predetermined number of times to emit and discharge. In the conventional flat-panel display device, the Y-electrode side common driver circuit 3 and the X-electrode side common driver circuit 5 are used for the discharge emission during the immediately preceding sustain discharge period in contrast to the entire cell portion 10. It is also possible to provide an initial operation period for erasing the wall charges that have been generated and remained in the cell portion.

In this case, in the initializing period, a method of sequentially erasing each display line may be used, or a method of collectively erasing all the display lines may be used. is there. Further, FIG. 7 shows an example of the configuration of a conventional scan driver and sustain discharge circuit of a flat panel display device. The Y electrodes 15-1 to 15- constituting the display line are shown.
At the same time as the n driver circuits 41 to 4n having the push-pull type driver circuit 51 for driving each n are provided, the push-pull type driver circuit 5 is also provided.
One end O of 1 is connected to Vs which is a first voltage power source through an appropriate switch means SW1, and the other end P of the other
Is connected to GND, which is a second voltage power supply, via an appropriate switch means SW2.

On the other hand, at the output end of the push-pull type driver circuit 51, a diode D having a function of raising the voltage of the display line for each display line.
U1 to DUn are provided with diodes DD1 to DDn having a function of holding down the voltage of the display line, and the common X electrode drive driver 5 includes a transistor TR3 and a transistor TR4. Of the output stage.

The conventional driving method in the flat panel display having the above structure is a scan address period in which the scan pulse is sequentially applied to the Y electrodes by the push-pull type driver circuit 51 in the scan driver circuit on the Y electrode side. The output of the push-pull type driver circuit is set to a high impedance state, and the diode DU is connected from the Y side common driver circuit 3.
A sustain discharge waveform is generated on the Y electrode via the diodes 1 to DUn and DD1 to DDn.

Further, by the driver circuit 5 on the X electrode side,
A sustain discharge waveform is generated on the X electrode. Next, another configuration example of the conventional flat panel display device will be described with reference to FIG. That is, the flat panel display device shown in FIG. 8 is generally called a floating system, and in the flat panel display device, a power recovery circuit 60 is further added to the scanning driver circuit 3. It is a thing.

That is, as understood from the block diagram of FIG. 8, in the conventional flat display device, each of the scanning driver circuits 41 to 4n on the Y electrode side is connected to a predetermined writing voltage Vsc via a resistor. And a diode DO30 connected in parallel with the transistor TR5, and a power recovery circuit 60 is added to one end of the transistor TR5. .

The X electrode drive circuit 5 has not only a conventionally known output stage but also a power recovery circuit 60 connected to the output stage. Further, the connection between the scanning driver circuits 41 to 4n on the Y electrode side and the power recovery circuit 60 is such that each of the scanning driver circuits 41 to 4n is connected as an open drain.

Since the display panel is a capacitive load, the power recovery circuit 60 has a function of recovering charges transferred to the outside when the voltage necessary for gas discharge is generated in the panel. The panel capacitance Cp and the coil 61 cause a series resonance. The operation of the conventional flat display device shown in FIG. 8 will be described. The fall of the scanning pulse is performed by turning on the transistor TR5 of the push-pull type driver circuit 51, and the rise thereof is performed by the transistor TR5. By turning off the transistor TR5, there may be a method of executing the charging current from the resistor R1 to the panel capacitance, or from the sustain discharge circuit side provided in the common driver circuit 3 on the Y electrode side. Diode DO
On the other hand, the sustain discharge waveform is generated from the driver circuit 5 on the X electrode side and the common driver circuit on the X electrode side through the transistor TR5 including the diode D01 or the FET.

[0027]

However, in the above-mentioned conventional flat panel display device of the system shown in FIG. 7, the withstand voltage of the scanning driver circuit on the Y electrode side is The voltage (Vsc) of about 80V,
Since it is determined by the maximum voltage (Vs) of the sustaining discharge waveform, which is about 200 V, it is necessary to use a large LSI, which complicates the circuit configuration and significantly increases the manufacturing cost.

Further, in the flat panel display device of FIG. 8, it is necessary to raise or lower the voltage only by the resistance. Therefore, it is necessary to increase the resistance, but it takes time to obtain a predetermined voltage, and this cannot be applied to high-speed line sequential scanning. Therefore, it is necessary to reduce the resistance, but on the contrary, if the resistance is reduced, an extra current will flow from the power supply when the voltage drops.
Therefore, it becomes necessary to increase the ON voltage of the scanning driver circuit, and hence the capacity.

If no resistor is used, there is also a method of raising the potential from the common driver circuit on the Y electrode side.
In that case, since the scan driver circuit is used in both the scan address period and the sustain discharge period, there is a problem that the current loss increases. Therefore, an object of the present invention is to improve the above-mentioned drawbacks of the prior art, to have low withstand voltage, to enable high-speed line-sequential scanning, to recover electric power,
The present invention provides a low power consumption and low cost flat panel display device.

[0030]

In order to achieve the above-mentioned object, the present invention basically adopts the technical constitution as described below. That is, as a first aspect of the flat panel display device according to the present invention, at least two substrates on which electrodes are arranged are arranged adjacent to each other so that the electrode portions face each other at right angles. Further, a plurality of orthogonal portions formed between the electrodes each form a cell portion forming a pixel, and the cell portions form a display panel arranged in a matrix, and The cell portion is a flat display device having a memory function capable of accumulating a predetermined amount of electric charge and a discharge light emitting function in accordance with an appropriate voltage applied to the electrode, and constitutes a cell to discharge electric discharge. A push-pull type driver circuit is provided on one of the pair of electrodes to be performed, and a power supply circuit means for applying a predetermined voltage to the individual driver circuit, and a predetermined voltage applied to the individual driver circuit. Electric power Is a drive device of a flat panel display device provided with a leak control switch means for leaking the liquid crystal. Further, a second aspect of the flat panel display device according to the present invention basically includes the above-mentioned configuration. A driving device for a flat panel display device in which a power recovery circuit is connected to the electrodes forming the display lines in the flat panel display device.

[0031]

In the flat panel display device according to the present invention, the technical structure as described above is adopted in order to solve the above-mentioned problems in the prior art. Each of the electrode groups is for applying a signal voltage for scanning in a period for writing display data to the cell portion, for example, a scan address period, and for discharging the cell portion in which the display data is written for a predetermined period. In the period, for example, the sustain discharge period, the sustain discharge voltage is applied, and the Y electrodes of one display line are configured to apply different voltages in different display operation periods, thereby simplifying the circuit configuration. Since it is possible to completely eliminate the influence of the voltage applied at other times even when applying different voltages to the same electrode at different times while forming it in a shape,
Since the voltage during use does not become higher than the specified value, the withstand voltage of each circuit can be reduced.

The driver circuit for driving the Y electrode is composed of two power source lines (FVH and FLG), and two series of power recovery circuits are connected to the two power source lines connected to each driver circuit. Since 60 is provided, a part of the electric power generated inside the flat panel display device circuit can be effectively used, so that a power-saving flat panel display device can be configured.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific examples of a flat panel display device according to the present invention will be described in detail below with reference to the drawings. That is, FIG. 1 is a block diagram showing a configuration of a specific example of a driving device of a flat panel display device according to the present invention, in which at least two substrates 12 and 13 on which electrodes 14 and 15 are arranged are provided. , The electrode portions are arranged adjacent to each other so as to be orthogonal to each other and face each other, and between the substrates 12, 1.
3 has, for example, an appropriate phosphor 19 inserted therein, and a plurality of orthogonal portions formed between the electrodes further form cell portions 10 forming pixels, respectively.
0 constitutes the display panel 1 arranged in a matrix, and the cell portion 10 has a memory function capable of accumulating a predetermined amount of electric charge and discharge according to an appropriate voltage applied to the electrodes 14 and 15. A flat panel display device having a light emitting function, and during a series of display operations displayed on the display device, a plurality of cell units 10 are selected to perform an appropriate write operation of display data. In order to execute the display data, the display data is written in a period in which the display data is written in the cell portion for performing scanning for selecting a plurality of display lines in a line sequential manner, for example, in the address period S-1 and the address period S-1. In a flat panel display device configured to be configured such that the cell section 10 is configured to emit light for multiple discharges for a predetermined period, for example, a sustain discharge period S-2, a plurality of display lines to be scanned. For example, a push-pull type driver circuit 51 including, for example, two transistors TR6 and TR7 is provided in each of two power supply lines FVH and FLG connected to a driver circuit that drives one of the electrodes, for example, the Y electrode 15. And a power supply circuit means 70 for applying a predetermined voltage to at least one of the power supply lines connected to the driver circuit, that is, the first power supply line, and the individual power supply lines connected to the driver circuit. Switch means 80 for leaking a predetermined voltage applied to the
The driving device of the flat panel display device in which the and are provided is shown.

The display panel 1 in the flat-panel display driving device according to the present invention uses three electrodes, that is, an X electrode 14, a Y electrode 15, and an address electrode 16, to perform image display driving. It is desirable that the display panel 1 in the flat display drive device has a display mode.
Is preferably one selected from a plasma display (PDP) device and an electroluminescence (EL) device.

That is, in the driving apparatus for the flat panel display device according to the present invention, the ON voltage (for example, GND) and the OFF voltage required for executing the scan on the scan electrode 15 are turned off.
Y electrode scan driver circuit groups 101, 102, ..., 10n configured by a push-pull type driver circuit 51 that applies a voltage (for example, Vsc) to one power supply line (first power supply line) connecting to the driver circuit, Supply or cut off the voltage of the first power supply means (for example, Vsc which is an OFF voltage during scanning), which is a scanning voltage, to a power supply line common to the scan driver circuit groups 101, 102, ... 10n. Power supply circuit means 70 installed for
And the scan driver circuit groups 101, 102 ... 1
Switch means 80 is provided for leaking the scanning voltage applied to each power source line of 0n so that the voltage of the power source line becomes 0V or GND.

Further, the power supply circuit means 70 according to the present invention.
Is at least one of the two power supply lines FVH and FLG connected to the driver circuit in the scan address period S-1, which is a period for writing display data in the cell portion, for example, FVH1 to FVHn (first First power supply means 7 for applying a predetermined voltage, for example, Vsc to the power supply line)
1 and a second power supply means 90 for applying a predetermined voltage to the FVH1 to FVHn in a sustain discharge period S-2, which is a period for discharging the cell portion in which the display data is written for a predetermined period. It is desirable to configure with.

Further, the first power source means 71 used in the present invention includes a first voltage generating means 72 for generating a high voltage power source, eg, Vsc, and a low voltage power source, eg, GN.
And a second voltage generating means 73 for generating D. The first voltage generating means 72 includes two power source lines (FVH, FL) connected to the driver circuit.
G) is connected to one power supply line, for example, the wiring FVH (first power supply line), and the second voltage generating means 7 is connected.
3 is the other power supply line of the two power supply lines (FVH, FLG) connected to the driver circuit, for example,
It is desirable to be connected to the wiring FLG (second power supply line).

The above-mentioned power source means 72, 73 used in the present invention are provided with switch means 74, 75, respectively.
Are provided, and two power supply lines (FVH1 to FVHn and FLG1 to FLG) that connect a predetermined voltage to the driver circuit according to a predetermined control signal input from the outside.
It is desirable that the wiring is supplied to any one of the wirings (n) (for example, FVH1 to FVHn).

Further, the above-mentioned switch means 74, 75 are
It is preferably composed of MOSFETs (TR8, TR9). Further, the first power source means 71 used in the drive device for the flat panel display device according to the present invention is provided with the first power source means 71.
Between the voltage generating means 72 and one of the two power source lines connected to the driver circuit, for example, FVH (first power source line), the diode DO4 or the resistor R
Or it is desirable that both are connected.

On the other hand, the second power supply means 90 constituting the power supply circuit 70 used in the driving device for the flat panel display according to the present invention is a voltage generation means for generating two different potentials. It is desirable that each of the voltage generators 91 and 92 is individually connected to each of the power supply line display lines (FVH, FLG) connected to the driver circuit.

In this example, the first voltage generating means 91 for supplying the GND potential is connected to, for example, the power supply line FVH among the two power supply lines connected to the driver circuit, and A second voltage generating means 92 for supplying a high voltage Vs is connected to another power supply line FLG (second power supply line) of the two power supply lines connected to the driver circuit. Is.

Further, the voltage generating means 91, 92 constituting the second power supply circuit 90 in the present invention are provided with switch means 93, 94, respectively, and a predetermined control signal inputted from the outside is provided. A power supply line that connects a predetermined voltage to the driver circuit (for example, FVH or FL
It is desirable to be configured to supply to any of G).

Furthermore, the switch means 93, 94 are
It is preferably composed of MOSFETs (TR11, TR12). The MOSFET (TR11, TR11, which is the switch means 93, 94 provided in the voltage generating means 91, 92 of the second power source means 90 described above.
Diodes DO21 and DO22 may be connected in parallel to TR12). On the other hand, the transistors TR6 and TR7 of the driver circuit 101 of the push-pull type 55 used in the scan driver circuit 101 on the Y electrode side used in the driving device of the flat display device according to the present invention have , It is desirable that the diodes DO2 and DO3 are connected in parallel.

The power supply line connected to the driver circuit on each Y electrode side used in the present invention is composed of two power supply lines (FVH, FLG), and the driver circuit of the push-pull type 55. 101 is connected and inserted in parallel between the two power supply lines (FVH, FLG). As described above, the other electrode in the flat panel display, that is, the X electrode is a common electrode.

The leak control switch means 80 used in the present invention is, for example, a MOSFET.
The first voltage generating means 7 may include the switch means 81 composed of (TR10).
2 is connected to the power supply line (FVH) on the side to which 2 is connected. Next, in the flat panel display device according to the present invention, the power recovery circuit 60 is connected to each of the power supply lines (FVH, FLG) forming the two power supply lines connected to the driver circuit. Is preferred.

The power recovery circuit 60 is preferably composed of a series resonance circuit composed of the capacitance of the display panel 1 and the coils 62 and 63 through the diodes, for example, DO2 and DO3. In the present invention, it is also possible to set the inductance values of the coils 62 and 63 in the series resonance circuit 60 by the panel capacitance and the coil via the diode which are configured in the two series so as to be different from each other. is there.

That is, the power recovery circuit 60 according to the present invention.
Is a diode or MOSFET connected to this
The power recovery circuit is capable of clamping a predetermined voltage (Vs or GND) from the peak voltage generated at the resonance, A part of the electric power is stored in a capacitor described later, and the electric power is used in the next scanning period.

The above-mentioned second power supply circuit 90 has a switch function for supplying a current during the sustain discharge period in which display light emission is repeated. The power recovery circuit 6
The detailed circuit configuration of 0 is not particularly limited,
It is possible to use a conventionally known power recovery circuit,
In the specific example of FIG. 1, in addition to the coils 62 and 63, diodes DO13, DO14, DO15, DO16, D
O17, DO18, DO19, DO20, and MOSF
An ET (TR13, TR14) and a capacitor C2 which are arranged in the arrangement as shown are used.

Each of the diodes used in the power recovery circuit 60 has a function of removing a parasitic inductance component generated in the circuit in association with the coils 62 and 63. As the common drive circuit on the X electrode side, it is possible to use the driver circuit used in the conventional flat display device shown in FIG.

Further, in the above-mentioned drive device for the flat panel display device according to the present invention, when the switch means 80 is used, the first voltage generating means 91 in the second power supply circuit 90 is used. Can be omitted. As another specific example of the present invention, an appropriate resistor is inserted between the leak control switch circuit 80 and one of the two power supply lines connected to the driver circuit, for example, FVH. The rising waveform of the scanning voltage may be blunted.

In the above-described drive device for a flat panel display device according to the present invention, an appropriate drive operation is performed on the premise of the above-mentioned configuration. The basic configuration of the drive method is as described above. In a flat-panel display device having a configuration, a push-pull driver circuit composed of two transistors is provided on each of one electrode of a pair of electrodes that constitute the cell and discharge, First power supply means for applying a predetermined voltage to the individual electrodes in a period for writing display data in the cell portion, and a period for discharging the cell portion in which the display data is written for a predetermined period. In the flat display device, there are provided second power supply means for applying a predetermined voltage to the individual electrodes and leak control switch means for leaking the predetermined voltage applied to the individual electrodes. In the step of activating the first power supply means to apply a predetermined voltage to the electrode immediately before writing the display data in the cell portion, immediately before the end of the period for writing the display data in the cell portion. Stopping the operation of the first power supply means and operating the leak control switch means to eliminate the potential difference between the wirings of the electrodes,
And a step of applying the alternating voltage to the electrodes by operating the second power supply means in a period for discharging the cell portion for a predetermined period.

As another aspect of the driving method of the flat panel display device according to the present invention, a period for discharging the cell portion in which the display data is written for a predetermined period, that is, a sustain discharge period S-2. The push-pull type driver circuit 10 in
It is also possible to perform the display processing while maintaining the potential difference between both ends of 1 at 0. Further, diodes DO2 and DO3 are connected in parallel to the transistors TR6 and TR7 of the push-pull type driver circuit 101, respectively, and the sustain discharge voltage in the sustain discharge period S-2 is the first 2 from the power supply means 90
2 and DO3 may be applied to the display panel only.

A specific example of the driving method of the driving device for a flat panel display device according to the present invention will be described below with reference to FIG. It should be noted that the address electrodes are omitted in FIG. That is, in the conventional driving method of the flat panel display device, a scanning pulse is output to the Y electrode side to select each Y electrode one by one in a line-sequential manner. Vsc is output to the wiring of the other wiring and GND is set to the other wiring, and scanning is performed while applying the voltage of Vsc between the wirings.

In contrast to such a conventional scanning method, in the present invention, a voltage of 0 V is applied to each electrode to be scanned as an OFF voltage for scanning. This method is adopted in the flat panel display device of the present invention, in which the two power supply lines FVH and FLG connected to the driver circuit for driving the Y electrodes which are the scanning electrodes are connected to the cell portion. Scanning voltage waveform Vsc (about 80V) used in the scan address period S-1 which is the period for writing the display data
And the sustain discharge voltage waveform (for example, about 200V) used in the sustain discharge period S-2, which is a period for discharging the cell portion in which the display data is written, is applied for a predetermined period. If the voltage used in the scan address period remains in the power supply lines FVH and FLG, the sustain discharge voltage used in the sustain discharge period is added, and a high voltage such as 280V is added. However, since it is applied, it is necessary to increase the breakdown voltage of each circuit.

Therefore, in the present invention, each of the power supply lines connected to the driver circuit for driving the above-mentioned scan electrodes is connected to the scan address period S-1 and the sustain discharge period S-2.
In order to avoid the above-mentioned problem of withstand voltage, the voltage applied to the power supply line is once erased and the power supply is After the line voltage is returned to 0V, a predetermined voltage used in another operation period is newly applied.

That is, in FIG. 2, immediately before the Y electrode 15 enters the scan address period S-1, as shown in S-1 of FIG. 2, the scan driver circuit 101 which is the scan driver circuit of the Y electrode. Transistor TR that composes
6 is turned on, and at the same time, the second power source means 71
Constituting the first voltage generating means 72 in the
The T-transistor TR8 is turned on, and the MOSFET transistor TR9 forming the second voltage generating means 73 is also turned on.
And During this time, the MOSFET transistor A forming the common driver 5 for the X electrodes is in the ON state,
Therefore, the voltage between the power supply lines FVH and FLG connected to the driver circuit for driving the Y electrode 15 becomes Vsc, and at the same time, the voltage Vs is applied to the X electrode.

As a result, each of the Y electrodes is (15-1
~ 15n) is a period (T
Through 1), the predetermined voltage Vsc is maintained until the end of the scan address period S-1. On the other hand, each of the Y electrodes (15-1 to 15n) is charged to the voltage Vsc as described above, but first connected to the driver circuit 101 that drives the first Y electrode 15-1. Of the pull (PUL connected to the power line FLG1 of
By turning on the transistor TR7 on the L) side and turning off the transistor TR6 on the push (PUSH) side, the potential of the Y electrode is lowered to GND, and at the time t1 during that time, the Y electrode 15 is turned off. The data is written by applying an address output corresponding to the display data corresponding to the power supply line FVH connected to the driver circuit for driving -1 and the Y electrode 15-1 from an appropriate address driver 6.

In the data write operation, the cell portion 10 on the Y electrode 15-1 selected by the address data discharges and a predetermined wall charge is generated in the cell portion 10. , Then the cell portion 10 in which the discharge has occurred
The discharge ends due to the wall charges of the cell portion 10 itself, and the address data write operation ends. During this period, in the driver circuit 101 that drives the other electrodes of the Y electrodes 15-2 to 15-n, the transistor TR6 on the push (PUSH) side is in the ON state.

Such scanning is executed for each of the Y electrodes 15-2 to 15-n, and the scanning address period S-1
At time T2, which is about to end, the first voltage generation means 7
2 turns off the MOSFET transistor TR8.
Then, at time T3 when a predetermined time has elapsed,
The MOSFET transistor TR10 of the leak control switch means 80 is turned on.

In such a state, the MOSFET transistor TR9 forming the second voltage generating means 73 is turned off.
Since it is N, at time T4, the power supply lines FVH and FL connected to the driver circuit for driving the Y electrode are connected.
The high voltage Vsc charged to G is the MOS
Since it escapes from the FET transistor TR10 to GND,
The voltage between the power supply lines FVH and FLG becomes 0V.

Incidentally, M which constitutes the second voltage generating means 73
The OSFET transistor TR9 is also OF at the time T4.
It becomes F. At the same time, the MOSFET transistor A forming the common driver 5 for the X electrodes is also turned off at the time T4, and the scan address period S-1 ends.

That is, the potential on the X electrode side is set to 0, and at the same time, the diode DO2 of the scan driver 101 for scanning is set.
By setting the voltage of all the Y electrodes to 0 through and the potential between the power supply lines FVH and FLG to 0V,
A series of scanning periods ends. At this time, the voltage Vs is applied to the X electrode side so that the discharge does not extend in the vertical direction.

Next, in the sustain discharge period S-2, the cell portion 10 discharged in the scan address period is
Since the wall charge remains in the cell portion 10 to be displayed, the wall charge is utilized to alternately apply the alternating voltage to only the cell portion in which the wall charge remains to perform the discharge. The display is performed by repeating. When sustaining discharge, the same alternating voltage is applied to all Y electrodes at the same time.

First, at the beginning of the sustain discharge period in the present invention, a predetermined voltage Vs is applied to the Y electrode, and at time T5, the driver circuit on the X electrode side. The transistor B in 5 is turned on, and the X electrode is maintained at 0V. Then, at time T6,
The transistor TR14 provided in the power recovery circuit 60 is turned off.
One of the power supply lines FL connected to the driver circuit that drives the Y electrode by charging the power supply line FLG with a part of the power stored in the capacitor C2.
The potential of G rises.

If the charge of the capacitor C2 is sufficient,
The voltage of the one power supply line FLG connected to the driver circuit for driving the Y electrode rises to a predetermined voltage Vs, but it is generally impossible to rise to Vs. At T7, the transistor TR14 becomes O
At the same time as the FF, the switch means 9 provided in the second voltage generating means 92 provided in the second power supply circuit 90.
The MOSFET (TR12) which is 4 is turned on,
The voltage of the power supply line FLG is raised to Vs.

Of course, in the present invention, the power recovery circuit 6
When 0 is not used, the voltage of the wiring FLG is raised to Vs by the second voltage generating means 92 provided in the second power supply circuit 90. This voltage is applied to the cell portion 10 of the display panel section via the diode DO3.

At time T8, the second power supply circuit 9 concerned
At the same time that the second voltage generating means 92 provided at 0 is turned off, the transistor B in the driver circuit 5 on the X electrode side is turned off. Then, at time T9,
The transistor TR13 provided in the power recovery circuit 60 is turned off.
N, and part of the voltage Vs charged in the wiring portion FVH is drawn into the capacitor C2 and accumulated therein, and the charge is used for discharging the next Y electrode.

By such scanning, the voltage of the power supply line FVH rapidly drops, and at time 10, the transistor TR13 is turned off, and at the same time, the first voltage generating means provided in the second power supply circuit 90 is provided. The MOSFET (TR11) which is the switch means 93 provided in 91 is turned off.
In the N state, the voltage of the wiring FVH is dropped to a complete 0V state.

By this operation, the first sustaining discharge operation of the Y electrode is completed, and then the sustaining discharge operation of the X electrode side is performed. On the X electrode side, the MOSFET (TR1
At time T11 while 1) is in the ON state, the transistor C is turned on to raise the potential of the X electrode via the coil 61, and at time T12, the transistor C is turned on.
When the transistor A is turned on at the same time as FF, the potential of the X electrode is raised to Vs which is a predetermined voltage.

During this period, the voltage on the Y electrode side of the cell portion 10 is maintained at 0V by being supplied with the GND potential via the diodes DO20 and DO3. Next, at time T13, the MOSFET (TR11) and the transistor A are turned off at the same time, and the transistor D and the transistor B are turned on at time T14, whereby the potential of the X electrode falls to 0V and Part of the electric charge accumulated in the cell portion 10 is charged in the capacitor C3, and the first sustaining discharge operation on the X electrode side is completed.

After that, the discharge operation on the Y electrode side and the discharge operation on the X electrode side as described above are alternately repeated a predetermined number of times, and a predetermined cell portion 10 of the display panel emits light with a predetermined brightness. To do. The brightness level in the cell portion 10 is determined by the number of times the alternating voltage is applied during the sustain discharge period.

The operation of the power recovery circuit 60 according to the present invention will be described. For example, in the sustain discharge operation on the Y electrode side, when the voltage of Vs is applied to the Y electrode, that is, the panel. When transferring charge to the capacitance,
For example, all the Y electrodes are directed in the Vs direction by the series LC resonance path in the path of the transistor TR14, the diode DO16, the coil 63, and the diode DO3 from the external voltage power supply Vp set to an intermediate voltage between the voltage Vs and GND. Charging is performed, the transistor TR11 is turned on near the peak voltage of the LC resonance voltage, and the Vs voltage is applied.

At this time, as described above, the voltage Vs applied to the cell portion 10 in which the wall charges of a certain level or more remain, and the transmission of the residual wall charge amount is sealed in the discharge cell. Since the voltage becomes equal to or higher than the discharge starting voltage of the rare gas, the sustain discharge is performed. After the discharge is terminated by the movement of the wall charges of itself, the Y electrode is set to GND. At that time,
The electric charge Cp charged in the display panel is transferred to the external power source Vp.

At this time, all the Y electrodes are discharged in the GND direction in the series LC resonance path of the path of the diode DO2, the coil 62, the diode DO15, and the transistor TR13 from the display panel capacitance Cp, and the charge is discharged. Is charged to the capacitor C2 and reused in the next sustain discharge operation, and at the same time, the transistor TR11 is turned on near the peak voltage of the LC resonance voltage to turn on the potential of the Y electrode. To the GND state, and the generation of the sustain discharge waveform is completed.

Similarly, a sustain discharge waveform on the X electrode side is generated in the next cycle, and by repeating these,
A series of sustain discharge periods is constructed. When the above display operation is completed, the wall charges of all the cell portions 10 are erased by the initialization operation, and the operation of the next frame is performed.

[0076]

Since the driving device of the flat display device according to the present invention has the above-mentioned structure,
The withstand voltage of the scan side driver circuit is equal to the voltage Vs of the sustain discharge waveform.
Since the circuit configuration and driving method do not depend on
It is possible to keep it at a low level.

That is, the withstand voltage of the driving device of the flat panel display device according to the present invention is Y of the sustain discharge waveform in the sustain discharge period.
Since the output potential difference between the two power supply lines FVH and FLG connected to the driver circuit that drives the electrodes is 0, V
It can be determined by sc. Further, in the driving device of the flat panel display device according to the present invention, a push-pull type driver circuit capable of high-speed line-sequential scanning can be used at the time of scanning, and further two series LC resonant circuits. Since it becomes possible to recover electric power by connecting to, a drive device for a power-saving flat display device is configured, and the circuit configuration is particularly simplified by making the driver circuit into an LSI. It is possible to provide an economical flat display device driving device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration in a specific example of a drive device for a flat panel display device according to the present invention.

FIG. 2 is a diagram showing a specific example of a drive voltage waveform when operating the drive device of the flat panel display device shown in FIG.

FIG. 3 is a plan view illustrating the outline of the configuration of a conventional flat panel display device.

FIG. 4 is a cross-sectional view showing an example of the configuration of a cell portion used in a conventional flat panel display device.

FIG. 5 is a diagram illustrating an example of a conventional method for driving a flat panel display device.

FIG. 6 is a diagram showing a specific example of drive voltage waveforms when operating a conventional flat panel display device.

FIG. 7 is a block diagram showing an example of a driving device in a conventional flat panel display device.

FIG. 8 is a block diagram showing another example of a driving device in a conventional flat panel display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Display panel 3 ... Y electrode side common driver circuit 4, 41-4n ... Y electrode scan driver circuit 5 ... X electrode side common driver circuit 6 ... Address driver circuit 10 ... Cell part 12, 13 ... Substrate 14 ... X electrode 15 ... Y electrode 16 ... Address electrode 17 ... Wall part 18 ... Dielectric layer 19 ... Phosphor 20 ... Discharge space 21 ... MgO film 55 ... Push-pull type driver circuit 60 ... Power recovery circuit 70 ... Power supply means 71 ... First Power supply means 80 ... Leakage control switch means 90 ... Second power supply means 101, 102 ... Y electrode scan driver circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Akira Otsuka Akira Otsuka 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited (72) Inventor Tadatsugu Hirose 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited

Claims (24)

[Claims] 1. A plurality of substrates, at least two substrates having electrodes arranged on the surface thereof, are arranged adjacent to each other so that the electrode portions face each other at right angles, and further are arranged between the electrodes. The orthogonal portions of each form a cell portion that constitutes each pixel, the cell portion constitutes a display panel arranged in a matrix, and the cell portion is an appropriate voltage applied to the electrode. A flat display device having a memory function capable of accumulating a predetermined amount of electric charge in accordance with a voltage and a discharge light emitting function, each of which is one of a pair of electrodes which constitute the cell and discharge. A push-pull type driver circuit, a power supply circuit means for applying a predetermined voltage to the individual driver circuits, and a leak control switch means for leaking the predetermined voltage applied to the individual driver circuits. A drive device for a flat display device, which is characterized by being provided. 2. The power supply circuit means defines a first power supply means for applying a predetermined voltage to the driver circuit in order to write display data in the cell portion, and a predetermined cell portion in which the display data is written. 2. The drive device for a flat panel display device according to claim 1, further comprising a second power supply means for applying a predetermined voltage to the driver circuit for discharging during the period. 3. The push-pull type driver circuit comprises:
It consists of two transistors, and each transistor has
2. The driving device for a flat panel display device according to claim 1, wherein the diodes are connected in parallel. 4. The cell portion is composed of an electrode formed on one of the two substrates and the pair of electrodes formed on the other of the two substrates, and the push-pull type driver circuit comprises: The driving device for the flat display device according to claim 1, wherein the driving device is connected and inserted into one of the pair of electrodes. 5. The other electrode of the pair of electrodes is:
The drive device for a flat panel display device according to claim 1, wherein the drive devices are commonly connected. 6. The first power supply means comprises first voltage generation means for generating a high potential power supply and second voltage generation means for generating a low potential power supply, and the first voltage generation means comprises: The first voltage generation means is connected to a first power supply line connected to the driver circuit, and the second voltage generation means is connected to a second power supply line connected to the driver circuit. The drive device for the flat panel display device according to claim 2. 7. The leak control switch means comprises the first
7. It is connected to the power supply line of
A driving device of the flat display device described. 8. The second power supply means is composed of voltage generation means for generating two different potentials, and each voltage generation means is a first and second power supply line connected to the driver circuit. 3. The driving device for a flat panel display device according to claim 2, wherein the driving device is connected to each of the above. 9. The driving device for a flat display device according to claim 1, wherein a power recovery circuit is connected to the driver circuit. 10. The drive device for a flat panel display device according to claim 9, wherein the power recovery circuit is a series resonance circuit including a panel capacitance and a coil via a diode. 11. The power source means is provided with a switch means respectively, and is configured to supply a predetermined voltage to the driver circuit by a predetermined control signal. A driving device of the flat display device described. 12. The drive device for a flat panel display device according to claim 11, wherein the switch means is composed of a MOSFET. 13. The driving device for a flat panel display device according to claim 12, wherein a diode is connected in parallel to the switch means in the second power supply means. 14. The flat display device according to claim 6, wherein a diode is connected between the first voltage generating means and the first power supply line of the first power supply means. Drive. 15. The plane according to claim 7, wherein a resistor is connected between the leak control switch circuit and the first power supply line to blunt the rising waveform of the first power supply means. Driving device for display device. 16. The driving device for a flat panel display device according to claim 8, wherein the second power supply means connected to the first power supply line also serves as the leak control switch means. 17. A series resonance circuit including the panel capacitance and a coil via a diode in the power recovery circuit is provided for each of the first and second power supply lines. The drive device for a flat display device according to claim 10. 18. The inductance value of each coil in a series resonance circuit formed by the panel capacitance and the coil via a diode configured in the two series is set to be different from each other. The drive device for a flat panel display device according to claim 17. 19. The display panel in the flat display driving device is one selected from a plasma display (PDP) device and an electroluminescence (EL) device. A drive device for a flat display device according to any one of claims. 20. A resistor is connected between the switch means of the first voltage generating means and the diode connected to the first power supply line in the first power supply means. 15. The drive device for a flat panel display device according to claim 14, wherein the drive device is a flat display device. 21. The driving device for a flat panel display device according to claim 1, wherein a plurality of the driver circuits are connected and inserted in parallel to the power supply circuit means. 22. A plurality of substrates, at least two substrates having electrodes arranged on the surface thereof, are arranged adjacent to each other so that the electrode portions are orthogonal to each other, and are arranged between the electrodes. The orthogonal portions of each form a cell portion that constitutes a pixel, the cell portions are arranged in a matrix, and the cell portions are charged with a predetermined amount of charge according to an appropriate voltage applied to the electrode. The cell has a memory function capable of accumulating and a discharge light emitting function, and a push-pull type driver circuit is provided on each of one electrode of a pair of electrodes which configures the cell and discharges the cell. In the period for writing the display data in the display section, the first power supply means for applying a predetermined voltage to the driver circuit and the period for discharging the cell section in which the display data is written for the predetermined period. The dora A flat display device provided with a second power supply means for applying a predetermined voltage to an inverter circuit and a leak control switch means for leaking a predetermined voltage applied to each of the electrodes, the cell comprising: Immediately before writing the display data to the section, the first power supply means is activated,
The step of applying a predetermined voltage to the driver circuit, immediately before the end of the period for writing the display data in the cell portion, the operation of the first power supply means is stopped, the leak control switch means is operated, and the driver is operated. A step of eliminating a potential difference between power supply lines of the circuit, and a step of operating the second power supply means in a period for discharging the cell portion for a predetermined period and applying an alternating voltage to the driver circuit. A method for driving a flat panel display device characterized by the above. 23. The display process is performed while maintaining a potential difference between both ends of the push-pull driver circuit at 0 during a period for discharging the cell portion for a predetermined period. Driving method of flat display device. 24. The push-pull type driver circuit is composed of two transistors, and a diode is connected in parallel to each transistor, and a diode is connected in parallel to each transistor in a period for discharging the cell portion for a predetermined period. 23. The driving method for a flat panel display device according to claim 22, wherein the discharge voltage is applied from the second power supply means to the display panel via the diode.