JPH0715938B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an element isolation structure of a semiconductor integrated circuit, and more specifically, it relates to an element isolation structure having excellent isolation characteristics, small parasitic capacitance, and large withstand voltage. It concerns a separation structure.

[Conventional technology]

FIG. 10 is a sectional view showing an example of a conventional element isolation structure used in a MOS integrated circuit. In the figure, a thick silicon oxide film 2 is provided in a region on a p-type silicon substrate 1. A gate oxide film 3 is formed in a region which is not covered with the silicon oxide film 2, and a polycrystalline silicon gate 4 is provided on the gate oxide film 3 in regions. In connection with the polycrystalline silicon gate 4, the source,
An n ⁺ diffusion layer 5 for drain is formed. An Al wiring layer 7 is provided on the silicon oxide film 6 formed by the CVD method. Silicon substrate 1 in contact with silicon oxide film 2
A p-type diffusion layer 2a for preventing inversion may be provided on the surface of the. The thick silicon oxide film 2 and the p-type diffusion layer 2a are
It has a so-called element isolation function of suppressing electrical mutual interference between two MOS type transistors, that is, Tr.1 and Tr.2.

FIG. 11 is a sectional view showing an example of a conventional element isolation structure. The feature of this structure is that the silicon oxide layer 8 is embedded on the silicon substrate 1, and the surface step difference is reduced accordingly. Also in this structure, the p-type diffusion layer 8a for preventing inversion is often provided in the surface region of the silicon substrate 1 which is in contact with the silicon oxide layer 8. The silicon oxide layer 8 and the p-type diffusion layer 8a suppress electric mutual interference between the two MOS transistors, that is, Tr.1 and Tr.2, and act as an element isolation structure.

In FIGS. 10 and 11, the thick silicon oxide film 2 and the silicon oxide layer 8 are provided and the p-type diffusion layers 2a and 8a are provided for the following reason. The threshold voltage of the element isolation region, that is, the threshold voltage V _th of the parasitic MOS transistor is V _th = φ _MS + 2φ _F + A (1) Here, φ _MS is the work function difference between the Al wiring and the surface of the silicon substrate, φ _F is the Fermi level, t _I is the thickness of the insulating film, ε _I is the relative permittivity of the insulating film, and ε _O is the vacuum dielectric. rate, Q _SS is an acceptor concentration of surface charge, epsilon _Si is the dielectric constant of the silicon substrate, q is the elementary charge, N _a is the silicon substrate surface at the interface between the insulating film and the silicon substrate. To increase the threshold voltage V _th , it is effective to increase the thickness t _I of the insulating film and increase the acceptor concentration N _A. This is the reason why the thick silicon oxide films 2 and 8 are provided and the p-type diffusion layers 2a and 8a are provided.

[Problems to be solved by the invention]

If the thickness of the silicon oxide films 2 and 8 is increased in order to increase the above-mentioned threshold voltage V _th , the surface step difference is increased in the structure of FIG. 10 and the silicon oxide film is increased in the structure of FIG. There is a problem that the groove for burying must be dug deeply. For this reason, it has been strongly desired to realize a structure or means in which the threshold voltage V _th is sufficiently high without increasing the thickness of the insulating film.

[Means for solving problems]

In order to solve such a problem, the present invention provides, in a semiconductor device, an element isolation structure, part or all of which has a structure in which holes are concentrated inside and the surface has a smooth dielectric constant. Is a porous silicon oxide film smaller than the silicon oxide film formed by thermal oxidation.

Further, the method of manufacturing a semiconductor device is provided with a step of forming a silicon oxide film containing phosphorus, arsenic or boron in a desired region and a step of performing heat treatment in an atmosphere containing hydrogen gas. .

[Action]

In the present invention, the porous silicon oxide film can provide an element isolation structure having a high threshold voltage and a small parasitic capacitance.

〔Example〕

FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention. In FIG. 1, 9 is a porous silicon oxide film as an insulating film, and 9a is a p-type diffusion layer for preventing inversion. In FIG. 1, the same or corresponding parts as those in FIG. 10 are designated by the same reference numerals. This porous silicon oxide film 9
The relative permittivity of is much smaller than the relative permittivity of 3.9 of a normal silicon oxide film, for example, 1.3 to 3. If the relative permittivity of the porous silicon oxide film 9 is 2.5,
From the equations (1) and (2), the threshold voltage V _th is approximately 3.9 / _2.5≈1 compared with the relative dielectric constant of 3.9 of a normal silicon oxide film.
You can see that it is 6 times larger. However, since φ _MS and 2φ _F are small, they can be ignored. If the threshold value is improved by this amount, it can be said that the thickness of the insulating film can be reduced correspondingly.

FIG. 2 is a sectional view showing a second embodiment of the semiconductor device according to the present invention. In FIG. 2, 10 is a porous silicon oxide layer as an insulating film, and 10a is a p-type diffusion layer for preventing inversion. In FIG. 2, the same or corresponding parts as in FIG. 11 are designated by the same reference numerals. In this structure, a porous silicon oxide layer 10 is embedded in the silicon substrate 1.
Even in this structure, the fact that the relative dielectric constant of the porous silicon oxide layer 10 is much smaller than the relative dielectric constant of 3.9 of the ordinary silicon oxide film is used, and as a result, the threshold voltage V
_th is significantly higher.

FIG. 3 is a sectional view showing a third embodiment of the semiconductor device according to the present invention. In FIG. 3, 11 is a porous silicon oxide film as an insulating film, and 11a is a p-type diffusion layer for preventing inversion. In FIG. 3, the same or corresponding parts as those in FIG. 10 are designated by the same reference numerals. In this structure, the silicon nitride film 12 is provided between the porous silicon oxide film 11 and the silicon substrate 1. The silicon nitride film 12 acts as a barrier that suppresses the diffusion of phosphorus contained in the porous silicon oxide film 11 into the silicon substrate 1.

FIG. 4 is a sectional view showing a fourth embodiment of the semiconductor device according to the present invention. In FIG. 4, 13 is a porous silicon oxide layer as an insulating film, and 13a is a p-type diffusion layer for preventing inversion. In FIG. 4, the same or corresponding parts as in FIG. 11 are designated by the same reference numerals. In this structure, a silicon nitride film 14 is provided between the porous silicon oxide layer 13 and the silicon substrate 1. This silicon nitride film 14 acts as a barrier that suppresses the diffusion of phosphorus contained in the porous silicon oxide layer 13 into the silicon substrate 1.

3 and 4, the silicon nitride films 12 and 14 having a large relative dielectric constant (about 7) are provided, but since the thickness is small, the porous silicon oxide film 11 and the silicon oxide layer 13 as a whole are formed.
The effect on the merit of low dielectric constant is negligible. Therefore, both FIG. 3 and FIG. 4 have the advantage that the threshold voltage V _th of the parasitic transistor is much higher than that of the conventional structure.

Next, an example of the structure of porous silicon oxide and its manufacturing method will be described. FIG. 5 is a cross-sectional photograph showing an example of a porous silicon oxide film after being cleaved. This photo is published by H. Takeuchi and J. Murota, J. Electroc
hem.Soc., 127, p.752). In FIG. 5, 21 is a silicon substrate, 22 is a normal silicon oxide film, and 23.
Is a porous silicon oxide film. In this example, the diameter is 0.
Many pores of 1 μm to 0.5 μm are seen. The relative permittivity of the porous silicon oxide film 23 is about 1.4, which is smaller than the relative permittivity of a normal silicon oxide film of 3.9 by almost 1/3. This has the advantage of reducing the stray capacitance between the Al wiring and the silicon substrate to about 1/3, in addition to the effect of improving the threshold value as described above. Further, since the pores of the porous silicon oxide film are hollow (gas) and have a high withstand voltage, the withstand voltage of the porous silicon oxide film also becomes large as a whole. The breakdown voltage of the hole is large for the following reason. The barrier height between the conduction band edge of the silicon substrate and the vacuum level is about 4.0 eV, and the barrier height between the conduction band edge of a normal silicon oxide film and the conduction band edge of the silicon substrate is about
About 30% higher than 3.1eV. For this reason, the vacuum level has been described, but the air level is almost the same.

Next, a method of manufacturing this porous silicon oxide film will be described. First, when a silicon oxide film containing phosphorus is formed and then heat treatment is performed in an atmosphere containing hydrogen, a porous silicon oxide film as shown in FIG. 5 is obtained. The phosphorus concentration in the silicon oxide film before being made porous is preferably 7 Wt.% Or more.
The PSG (Phospho Silicate Glas) layer can be used to emphasize the high phosphorus concentration.
s) is also called.

FIG. 6 shows the effect of heat treatment. The horizontal axis shows the heat treatment temperature, and the vertical axis shows the thickness of the silicon oxide film containing phosphorus. This data shows that after a silicon oxide film with a phosphorus concentration of 9 Wt.% Was formed to 0.63 μm, heat treatment was performed for 20 minutes in a hydrogen atmosphere (indicated by white circles in the figure) or a nitrogen atmosphere (indicated by black circles in the figure). The film thickness is shown. A rapid increase in film thickness is observed when heat treatment is performed at 1000 ° C or higher in a hydrogen atmosphere. This increase in film thickness is achieved by making the silicon oxide film containing phosphorus porous. It can be seen from the characteristic curve 24 in the figure that the 0.63 μm thick silicon oxide film is actually 2.4 times thicker to 1.52 μm thick. As can be seen from FIG. 5, in this porous silicon oxide film, the porous portion is concentrated inside (in the bulk), and the surface layer is smooth and uneven with almost no effect of the porous pores. You can see that there is no. Therefore, this silicon oxide film is convenient for forming an Al wiring layer thereon.

A characteristic curve 25 in FIG. 7 shows what happens when the silicon oxide film containing phosphorus is once subjected to a heat treatment in a hydrogen atmosphere and then again subjected to a heat treatment in nitrogen. 0 including phosphorus.
900 for a 55 μm thick silicon oxide film (phosphorus concentration 9.5 Wt.%)
A sample that has been heat treated in H ₂ at ℃ is used as the starting sample. When this sample is heat-treated in nitrogen at 900 ° C to 1100 ° C, an increase in film thickness is observed. The film thickness at 1100 ° C is 1.75 μm, and
It is 3.2 times larger than 55 μm. As a reference, the characteristic curve 26 in FIG. 4 shows the case where a material that has been heat treated in nitrogen at 900 ° C. is used as the starting material. In this case, no increase in film thickness is observed even by heat treatment in nitrogen at 1100 ° C.

The change when the heat treatment in the oxidizing atmosphere is performed on the porous silicon oxide film instead of the heat treatment in the nitrogen atmosphere will be described. When the heat treatment is performed in an oxidizing heat atmosphere, the porous silicon oxide film shrinks and the pores are lost. It is speculated that this change results from the inability to maintain the pores because the hydrogen involved in the formation of the pores is consumed by the reaction with oxygen. Attention should be paid to the reduction of the film thickness in the oxidizing atmosphere in the manufacturing process described later. That is,
It is necessary to avoid heat treatment in an oxidizing atmosphere with the surface of the porous silicon oxide film exposed. When it is absolutely necessary to perform heat treatment in an oxidizing atmosphere, it is desirable to coat the surface of the porous silicon oxide film with another material, for example, a silicon nitride film.

Characteristic curves 27 and 28 in FIG. 8 show how the average radius r of the pores and the number Nv per unit area of the porous silicon oxide film change with the heat treatment time. In this case, as a condition, the nitrogen atmosphere is 950 ° C.,
The silicon oxide film porous is in H ₂ atmosphere at 900 ° C. 240
The film thickness is 0.55 μm. From the characteristic curve 27, it can be seen that the average radius r of the pores increases and saturates as the heat treatment time in the N ₂ atmosphere increases. Further, from the characteristic curve 28, it can be seen that the number Nv per unit area is opposite to the average radius r of the holes and decreases with the increase of the heat treatment time in the N ₂ atmosphere and then converges to a constant value.

Next, the manufacturing process of the structure shown in FIG. 4 will be described with reference to FIG. 0.7 on the desired area of the surface of the silicon substrate 1.
An etching groove 15 having a depth of μm is provided, boron ions are implanted on the surface of the silicon substrate at the bottom of the etching groove, and a p-type diffusion layer 13a is formed, whereby the structure of FIG. 9A is obtained.

Then, a 100 Å silicon oxide film 16 is formed by a thermal oxidation method, and a 400 Å silicon nitride film 14 is formed on the silicon oxide film 16 by a CVD method to obtain the structure shown in FIG. 9B.

Then, a silicon oxide layer 17 having a phosphorus concentration of 9 Wt.% Is embedded in the etching groove 15 by 0.3 μm to obtain the structure shown in FIG. 9C.

Then, heat treatment at 1050 ° C for 20 minutes in a hydrogen atmosphere
As shown in FIG. 9 (d), the volume of the silicon oxide layer 17 expands and changes into a porous silicon oxide layer 13. Here, the silicon nitride film 14 acts as a mask that suppresses the diffusion of phosphorus into the silicon substrate 1 during the heat treatment. The surface of the porous silicon oxide layer 13 and the surface of the silicon substrate 1 are substantially flattened as shown in FIG.

Then, the 400 Å silicon nitride film 14 is etched with hot phosphoric acid to obtain the structure shown in FIG. 9 (e).

Then, a polycrystalline silicon layer 4 serving as a polycrystalline silicon gate is locally provided on the gate oxide film 3. By performing arsenic ion implantation in a self-aligned manner using this polycrystalline silicon layer 4 as a mask, an n ⁺ diffusion layer 5 is obtained as shown in FIG. 9 (f). The n ⁺ diffusion layer 5 acts as a source and a drain.

Then, the silicon oxide film 6 and the Al wiring layer 7 are provided by using the usual manufacturing process, and the structure of FIG. 9 (g) is obtained.

In the above description, the example of the integrated circuit of the n-channel MOS transistor has been described, but the present invention is also effective in the case of the integrated circuit of the p-channel MOS transistor, and is also effective in the integrated circuit of the CMOS transistor having both of them. Needless to say.

Further, in the manufacturing method, the case where phosphorus is used as an impurity mixed into the silicon oxide film to form the porous silicon oxide film has been described, but other impurities such as arsenic, boron, sodium or lead are used. It goes without saying that it is okay.

It is needless to say that the silicon nitride film 12 in FIG. 3 or the silicon nitride film 14 in FIG. 4 may use another insulating film, for example, a silicon oxide film. From the viewpoint of suppressing the diffusion of phosphorus, the silicon oxide film is not as effective as the silicon nitride film, but depending on the heat treatment conditions, the silicon oxide film is sufficiently effective.

〔The invention's effect〕

As described above, the present invention provides a semiconductor device having an inter-element isolation structure, a part or all of which has a structure in which holes are concentrated inside and the surface is smooth, and the dielectric constant is formed by thermal oxidation. A porous oxide film smaller than a silicon oxide film, and in the method of manufacturing a semiconductor device, a step of forming a silicon oxide film containing phosphorus, arsenic or boron in a desired region, and an atmosphere containing hydrogen gas. By providing the step of performing the heat treatment inside, there is an effect that it is possible to realize an element isolation structure having excellent isolation characteristics such that the parasitic capacitance is halved and the withstand voltage is large. Therefore, when the present invention is applied to the logic circuit, the parasitic capacitance is halved, and the operation speed can be improved. When the present invention is applied to a memory circuit, the operating speed can be improved in the same manner, and further, there is an advantage that the leakage of accumulated charges is small and the number of times of refreshing can be made smaller than before.

Further, since the element isolation structure according to the present invention has the excellent isolation characteristics described above, it is possible to make the area occupied by the element isolation region smaller than that of the conventional one. This is a great advantage for miniaturization and high integration of semiconductor integrated circuits.

[Brief description of drawings]

1, 2, 3, and 4 are sectional views showing the first, second, third, and fourth embodiments of the semiconductor device according to the present invention, and FIG.
FIG. 6 is a cross-sectional photograph showing an example of a porous silicon oxide film after cleavage, FIG. 6 is a graph showing the effect of heat treatment temperature on the thickness of a silicon oxide film containing phosphorus, and FIG. 7 is an atmosphere of hydrogen or nitrogen. Fig. 8 is a graph showing the temperature dependence of heat treatment in nitrogen for a silicon oxide film containing phosphorus heat-treated in Fig. 8, and Fig. 8 is a graph showing the effect of heat treatment time on the radius of a hole and the number of holes per unit area. FIG. 9 is a sectional view showing a process when the planarizing method is applied to an actual device manufacturing process, and FIGS. 10 and 11 are sectional views showing a conventional semiconductor device. 1 ... Silicon substrate, 3 ... Gate oxide film, 4 ... Polycrystalline silicon gate, 5 ... N ⁺ diffusion layer, 6,9,11,16 ... Silicon oxide film, 7 ... Molybdenum wiring layer, 9a , 10a, 11a, 1
3a …… p-type diffusion layer, 10,13,17 …… silicon oxide layer, 12,1
4 ... Silicon nitride film, 15 ... Etching groove.

Claims (2)

[Claims] 1. An element isolation structure comprising an insulating film provided in a predetermined region on a silicon substrate or an insulating layer provided in a predetermined region on a silicon substrate, and a region other than the predetermined region. In a semiconductor device having a MOS transistor provided in, a part or all of the element isolation structure is made of a porous silicon oxide film, and the porous silicon oxide film has a smooth surface and pores. A semiconductor device having a structure concentrated inside and having a dielectric constant smaller than that of a silicon oxide film formed by thermal oxidation. 2. An element isolation structure comprising an insulating film provided in a predetermined region on a silicon substrate or an insulating layer provided in a predetermined region on a silicon substrate, and a region other than the predetermined region. A method for manufacturing a semiconductor device having a MOS transistor provided in, wherein a step of forming a silicon oxide film containing phosphorus, arsenic or boron in a desired region and a heat treatment in an atmosphere containing hydrogen gas are performed. A method of manufacturing a semiconductor device, comprising: