JPH07154444A - Frame synchronizing detection circuit - Google Patents

Abstract

PURPOSE:To perform synchronizing detection free from erroneous detection by synchronously adding envelope components of a reception signal after averaging them in plural channels and discriminating the symbol, whose correlation value obtained by the pattern of a one-slot portion is maximum, to detect a synchronizing pattern. CONSTITUTION:Transmission is performed by multiplexing of two channels, and two channels have the same pattern of the synchronizing symbol. Square vector values of I and Q signals of channels 1 and 2 demodulated by a receiver are calculated by individual square vector calculators 1 and are inputted to an average value calculating circuit 2. This circuit 2 obtains an average value of channels 1 and 2, and it is successively inputted to a memory 6 having the 60-symbol capacity. A data pattern correlation value calculator 7 calculates pattern correlations of 60 symbols, and the timing when the addition value of three symbols is maximum is outputted as a frame synchronizing detection signal from a correlation value discriminating circuit 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame sync detecting circuit for detecting a frame sync symbol in a receiver of a multi-channel transmission system.

[0002]

2. Description of the Related Art As a conventional frame synchronization detecting circuit, there is a circuit as shown in FIG. An example of signal arrangement of data symbols and synchronization symbols is shown in FIG. 3, and an example of transmission data slot configuration is shown in FIG. The sync symbol is set to have the maximum amplitude as shown in FIG. 3, and one slot is composed of 60 symbols as shown in FIG. 4, and the sync symbol is inserted in the first three symbols of the slot.

In FIG. 2, the square vector value is obtained from the demodulated in-phase (I) and quadrature (Q) signals by the square vector calculator 1, and the contents of the previous slot are synchronized with the memory 6 equal to the number of symbols for one slot. Accumulate by adding and shifting sequentially. At this time, the data in the memory 6 is multiplied by the forgetting factor and added so that the added memory contents do not overflow. As shown in FIGS. 3 and 4, the timing at which three consecutive symbols in the slot are maximum is calculated by the data of the memory 6 that is added and stored, and the pattern correlation value for 60 symbols calculated by the correlation value calculator 7 is calculated. The correlation judgment circuit 8 judges and detects, and outputs a frame synchronization signal at that timing.

[0004]

In the above-described conventional frame synchronization detection circuit, since the frame synchronization detection is performed on only one channel, the maximum value continues in the data symbol, or the frame is affected by interference due to fading, noise addition, etc. There is a drawback that the probability of erroneous detection of erroneously detecting a sync symbol increases.

In order to eliminate this drawback, the present invention provides a frame synchronization detection circuit which is configured to detect frame synchronization symbols using envelopes of frequency-multiplexed channels and which can detect synchronization without erroneous detection. With the goal.

[0006]

In order to achieve the above object, the present invention averages envelope components of a received signal in a plurality of channels and then synchronously adds them to obtain a correlation value in a pattern for one slot. The synchronization pattern is detected by determining the symbol with the maximum value, and the frame synchronization signal is output.

[0007]

As a result, when the average of a plurality of channels is taken, the signal power to noise power ratio of the received signal is N (where N is 2).
An integer greater than one), the voltage of each channel e _{n (n} = 1,2,
3, ... N) and the noise power is no, the following (1)
It is represented by a formula.

[0008]

[Number 1] _{(e 1 + e 2 + e} 3 + ··· e n) 2 / N · no = (N · E) 2 / N · no = N (E 2 / no) = N · (S / no)・ ・ ・ ・ ・ ・ (1)

That is, the signal power to noise power ratio is equivalently improved in proportion to the number of channels, and the probability of frame synchronization detection is increased.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A block diagram of FIG.
Description will be given using the signal arrangement example of the data symbols and the synchronization symbols of FIG. 3 and the transmission data slot configuration example of FIG. The signal arrangement of data symbols and synchronization symbols and the transmission data slot configuration are the same as those of the conventional example shown in FIGS. 3 and 4. One slot has 60 symbols, and the synchronization symbol with the maximum amplitude is inserted into the first 3 symbols of the slot. . Also, send 2
It is assumed that transmission is performed by channel multiplexing, and the sync symbol pattern is the same for both channels.

An average value calculation circuit 2 calculates the square vector values of the I and Q signals of 1 channel and 2 channels demodulated by the receiver by separate square vector calculators 1, respectively.
Entered in. In the average value calculation circuit 2, the average value of 1 channel and 2 channels is calculated and sequentially input to the memory 6 having 60 symbols. The data pattern correlation value calculator 7 uses 60
The correlation value determination circuit 8 outputs the timing at which the pattern correlation for the symbols is calculated and the added value of consecutive 3 symbols becomes maximum as a frame synchronization detection signal.

[0012]

According to the present invention, it is possible to detect frame synchronization without erroneous detection, and to improve the received data error rate in a semi-fixed or fixed communication terminal such as a mobile body that receives interference such as fading and noise. Is effective for.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional frame detection circuit.

FIG. 3 shows an example of signal arrangement of data symbols and synchronization symbols.

FIG. 4 shows a configuration example of a data slot for transmission.

[Explanation of symbols]

 1 Square Vector Calculator 2 Average Value Calculation Circuit 3 Adder 4 Multiplier 5 Forgetting Factor Memory 6 Memory 7 Data Pattern Correlation Value Calculator 8 Correlation Value Judgment Circuit

Claims (1)

[Claims] 1. A transmission system in which signals of a plurality of channels are frequency-multiplexed and simultaneously transmitted, in which a transmitting unit inserts and transmits a continuous specific frame synchronization symbol in each frame to be transmitted, and a receiving unit receives the above-mentioned frames from the received signals. In a frame synchronization detection circuit that detects synchronization symbols, the envelope components of a plurality of channels are added and averaged, and then synchronous addition is performed, and the added value of the number of symbols equal to the number of frame synchronization symbols in the frame is calculated from the synchronized addition value. A frame sync detection circuit configured to detect the maximum symbol as a frame sync symbol.