JPH07153920A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH07153920A JPH07153920A JP5326146A JP32614693A JPH07153920A JP H07153920 A JPH07153920 A JP H07153920A JP 5326146 A JP5326146 A JP 5326146A JP 32614693 A JP32614693 A JP 32614693A JP H07153920 A JPH07153920 A JP H07153920A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- polysilicon
- electrode
- semiconductor device
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 57
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 58
- 229920005591 polysilicon Polymers 0.000 claims abstract description 55
- 238000009792 diffusion process Methods 0.000 claims description 11
- 230000005669 field effect Effects 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 4
- 239000011521 glass Substances 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 3
- 239000011574 phosphorus Substances 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 66
- 238000010586 diagram Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000004043 responsiveness Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
に半導体素子の温度を検出することができる半導体装置
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of detecting the temperature of a semiconductor element.
【０００２】[0002]
【従来の技術】従来の温度検出機能付き半導体装置は、
半導体素子のチップを金属基板上にろう付けし、このチ
ップのわきに熱電対などの温度センサ−を取り付け、そ
の信号を素子の制御回路に送り、温度検出するものが主
流であった。2. Description of the Related Art A conventional semiconductor device with a temperature detecting function is
The mainstream method is to braze a semiconductor element chip on a metal substrate, attach a temperature sensor such as a thermocouple to the side of the chip, and send the signal to the element control circuit to detect the temperature.
【０００３】上記従来の温度検出機能付き半導体装置で
は、温度センサ−と半導体素子との間に熱抵抗が存在
し、温度上昇に対する応答遅れが避けられず、半導体素
子の保護が十分行われないという欠点を有している。こ
の欠点を解決するものとして、半導体素体の表面上に絶
縁膜を介して温度センサ−を構成する層を備えた半導体
装置が提案されている(特開昭63−299264号公報参照)。
この半導体装置を図９に基づいて説明する。In the conventional semiconductor device with a temperature detecting function, there is a thermal resistance between the temperature sensor and the semiconductor element, a delay in response to a temperature rise cannot be avoided, and the semiconductor element is not sufficiently protected. It has drawbacks. As a solution to this drawback, there has been proposed a semiconductor device having a layer forming a temperature sensor on the surface of a semiconductor element via an insulating film (see JP-A-63-299264).
This semiconductor device will be described with reference to FIG.
【０００４】図９は、上記従来の半導体装置の要部断面
図であって、電力用ＭＯＳＦＥＴは、シリコン基板(ｎ+
基板１)とその上に形成されたｎ-エピタキシャル層(ｎ-
層２)からなり、このｎ-層２にｐ-層31及びｐ+層32が設
けられ、さらにその中に二つのｎ+層４が設けられてい
る。また、ｎ-層２の表面には、ゲ−ト酸化膜(酸化膜
５)を介して多結晶シリコンからなるゲ−ト層(ポリシリ
コン６)が設けられ、その上を酸化膜７及びリンガラス
８が被覆している。そして、ｐ+層32及びｎ+層４にはソ
−ス電極91、ｎ+基板１にはドレイン電極92、ゲ−ト層
(ポリシリコン６)にはゲ−ト電極93が接触している。FIG. 9 is a cross-sectional view of a main part of the conventional semiconductor device described above. The power MOSFET is a silicon substrate (n +
Substrate 1) and n formed thereon - epitaxial layer (n -
Layer 2), in which the n − layer 2 is provided with a p − layer 31 and a p + layer 32, in which two n + layers 4 are provided. A gate layer (polysilicon 6) made of polycrystalline silicon is provided on the surface of the n − layer 2 via a gate oxide film (oxide film 5), and an oxide film 7 and a phosphorus layer are formed on the gate layer. It is covered with glass 8. The p + layer 32 and the n + layer 4 have a source electrode 91, the n + substrate 1 has a drain electrode 92, and a gate layer.
The gate electrode 93 is in contact with (polysilicon 6).
【０００５】一方、温度センサ−は、不活性領域のｐ+
層３の上に厚さ１μｍの酸化膜５、厚さ１μｍの多結晶
Ｓｉ膜(ポリシリコン６)、厚さ0.5μｍの酸化膜７を形
成し、この酸化膜７上に２層目のｎ-多結晶Ｓｉ膜(ポリ
シリコン11)を成長させ、その中にｐ+層12、ｎ+層13を
設けてｐｎ接合ダイオ−ド10を有している。なお、14、
15は電極である。On the other hand, the temperature sensor has p + of the inactive region.
An oxide film 5 having a thickness of 1 μm, a polycrystalline Si film (polysilicon 6) having a thickness of 1 μm, and an oxide film 7 having a thickness of 0.5 μm are formed on the layer 3, and an oxide film 7 of a second layer is formed on the oxide film 7. - growing the polycrystalline Si film (polysilicon 11), pn junction diode with the p + layer 12, n + layer 13 provided therein - has a de 10. In addition, 14,
15 is an electrode.
【０００６】そして、このダイオ−ド10の低電流におけ
る順電圧降下は、温度依存性を有するので、順電圧降下
をｐ+層12に接触する電極14とｎ+層13に接触する電極15
から取り出すことによりその温度を検出でき、前記した
電力用ＭＯＳＦＥＴのｎ-層２とｐ+層32の間の接合温度
を２層のポリシリコン膜を介して検出でき、ゲ−ト電圧
の制御回路へ送ることができるものとなっていた。Since the forward voltage drop of the diode 10 at a low current has temperature dependence, the forward voltage drop is in contact with the p + layer 12 at the electrode 14 and the n + layer 13 at the electrode 15.
The temperature can be detected by taking it out from the device, and the junction temperature between the n − layer 2 and the p + layer 32 of the power MOSFET can be detected through the two-layer polysilicon film, and the gate voltage control circuit can be detected. It could be sent to.
【０００７】[0007]
【発明が解決しようとする課題】ところで、上記従来の
半導体装置では、半導体素子を形成するためのポリシリ
コン６と、温度検出用ポリシリコンダイオ−ドを形成す
るためのポリシリコン11の２層ポリシリコン構造となっ
ているので、ポリシリコン成長及びポリシリコンパタ−
ニング、ポリシリコンエッチング等が２回必要となり、
製造工程が多くなるという問題点があった。By the way, in the above-mentioned conventional semiconductor device, a two-layer polysilicon of polysilicon 6 for forming a semiconductor element and polysilicon 11 for forming a temperature detecting polysilicon diode is used. As it has a silicon structure, it can be used for polysilicon growth and polysilicon pattern.
And polysilicon etching are required twice,
There is a problem that the number of manufacturing processes increases.
【０００８】また、上記従来の半導体装置では、温度検
出用ポリシリコンダイオ−ドを形成する時に拡散層の押
し込みが浅い構造となっているため、アルミスパイクに
よる特性変動や順方向電圧(ＶF)、耐圧(ＶZ)等のバラツ
キが発生するという問題点があった。Further, the above-described conventional semiconductor device, the temperature detecting polysilicon diode - for pushing the diffusion layer when forming the de is a shallow structure, characteristic variation and the forward voltage due to the aluminum spike (V F) However, there is a problem in that variations in withstand voltage (V Z ) occur.
【０００９】本発明は、上記従来の半導体装置の問題点
に鑑み成されたものであって、その目的は、製造工程が
短縮でき、上記したバラツキが発生しないものであり、
半導体素子の接合部の温度上昇を応答性よく正確に検出
して該素子の破壊を防止できる半導体装置を提供するこ
とにある。The present invention has been made in view of the problems of the conventional semiconductor device described above, and an object thereof is to shorten the manufacturing process and to prevent the above-mentioned variations.
It is an object of the present invention to provide a semiconductor device capable of accurately detecting a temperature rise of a junction portion of a semiconductor element with high responsiveness and preventing the element from being broken.
【００１０】[0010]
【課題を解決するための手段】本発明の半導体装置は、
ＭＯＳＦＥＴとほぼ同一工程フロ−で温度検出用ポリシ
リコンダイオ−ドを形成する層を備え、かつ、ポリシリ
コン層を一層のみで形成する層を備えたものであり、ま
た、温度検出用ポリシリコンダイオ−ドのポリシリコン
層にポリシリコン層を垂直に突き抜けた拡散層を備えた
ものであり、これにより前記した目的とする半導体装置
を提供するものである。The semiconductor device of the present invention comprises:
A polysilicon layer for forming a temperature detecting polysilicon diode and a layer for forming a single polysilicon layer are formed in almost the same process flow as that of the MOSFET. And a diffusion layer vertically penetrating the polysilicon layer is provided in the negative polysilicon layer to provide the above-described semiconductor device of interest.
【００１１】即ち、本発明は、「ポリシリコンを主体と
したゲ−ト電極を有するＭＯＳ型電界効果トランジスタ
を含む半導体素子において、その温度を検出できるポリ
シリコンダイオ−ド又は抵抗を同一チップ上にポリシリ
コン一層で形成してなることを特徴とする半導体装
置。」を要旨とする。That is, according to the present invention, in a semiconductor device including a MOS field effect transistor having a gate electrode mainly composed of polysilicon, a polysilicon diode or a resistor capable of detecting the temperature is provided on the same chip. A semiconductor device characterized by being formed of a single layer of polysilicon. "
【００１２】また、本発明は、「前記半導体素子とその
温度を検出できるポリシリコンダイオ−ド又は抵抗を同
一チップ上に形成してなり、ゲ−ト電極、ソ−ス電極、
ドレイン電極、アノ−ド電極、カソ−ド電極の５電極を
独立に有する、又は、ゲ−ト電極、ドレイン電極、カソ
−ド電極の独立した３電極と、ソ−ス電極とアノ−ド電
極とを接続した電極端子の４電極を有する半導体装
置。」及び「前記半導体素子と同一チップ上に形成した
温度検出用ポリシリコンダイオ−ドを形成する拡散層
が、ポリシリコン層を垂直に突き抜けているポリシリコ
ン層を有する半導体装置。」を要旨とする。According to the present invention, "the semiconductor element and a polysilicon diode or resistor capable of detecting the temperature thereof are formed on the same chip, and a gate electrode, a source electrode,
Drain electrode, anode electrode, cathode electrode having 5 electrodes independently, or gate electrode, drain electrode, cathode electrode having 3 independent electrodes, source electrode and anode electrode A semiconductor device having four electrodes of electrode terminals connected to and. And "a semiconductor device in which a diffusion layer forming a temperature detecting polysilicon diode formed on the same chip as the semiconductor element has a polysilicon layer vertically penetrating the polysilicon layer." .
【００１３】[0013]
【実施例】次に、本発明について図１〜図８を参照して
説明する。なお、図１〜図５は、本発明の一実施例(実
施例１)を説明するための図であり、図６及び図７は、
本発明の他の実施例( 実施例２)を説明するための図で
ある。また、図８は、本発明の半導体装置における温度
特性(温度−ＶF)を示すグラフである。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to FIGS. 1 to 5 are views for explaining one embodiment (Example 1) of the present invention, and FIGS. 6 and 7 are
It is a figure for demonstrating other Example (Example 2) of this invention. 8 is a graph showing the temperature characteristic of the semiconductor device of the present invention (temperature -V F).
【００１４】（実施例１）図１は、本発明の一実施例
(実施例１)の半導体装置の要部断面図であり、図２は、
本発明の実施例１の半導体装置の平面図である。本実施
例１における半導体装置の製造に当っては、図１に示す
ように、まずシリコン基板(ｎ+基板１)上に酸化膜５を
形成し、さらにその上にポリシリコン６を形成し、フォ
トリソグラフィ技術を用いてポリシリコン６をパタ−ニ
ングし、ｎ+層４とｐ+層32を形成し、その上に酸化膜７
及びリンガラス８を形成する。(Embodiment 1) FIG. 1 shows an embodiment of the present invention.
2 is a cross-sectional view of a main part of the semiconductor device of (Example 1), and FIG.
FIG. 3 is a plan view of the semiconductor device according to the first embodiment of the present invention. In manufacturing the semiconductor device according to the first embodiment, as shown in FIG. 1, first, an oxide film 5 is formed on a silicon substrate (n + substrate 1), and then polysilicon 6 is formed thereon. The polysilicon 6 is patterned by using the photolithography technique to form the n + layer 4 and the p + layer 32, and the oxide film 7 is formed thereon.
And phosphor glass 8 are formed.
【００１５】ｎ+層４及びｐ+層32にはソ−ス電極91、シ
リコン基板(ｎ+基板１)にはドレイン電極92、ゲ−ト層
にはゲ−ト電極93が接触しており、このゲ−ト電極形成
と同一工程で、ｐ+層12に接触する電極14とｎ+層13に接
触する電極15とを有する温度検出用ポリシリコンダイオ
−ド10を形成する。A source electrode 91 is in contact with the n + layer 4 and the p + layer 32, a drain electrode 92 is in contact with the silicon substrate (n + substrate 1), and a gate electrode 93 is in contact with the gate layer. In the same step as forming the gate electrode, a temperature detecting polysilicon diode 10 having an electrode 14 in contact with the p + layer 12 and an electrode 15 in contact with the n + layer 13 is formed.
【００１６】図３(Ａ)、(Ｂ)は、上記ダイオ−ド部拡散
層を説明するための図であって、本実施例１のポリシリ
コンダイオ−ド10の拡散層は、同図(Ａ)、(Ｂ)に示すよ
うな閉じた拡散層、並列拡散層を形成する。図４は、本
実施例１のポリシリコンダイオ−ド(ポリシリＤｉ)部の
レイアウトを示す平面図であり、これは、試作時のパタ
−ンを参考としたものであり、縦：500μｍ、横：240μ
ｍよりなる。FIGS. 3 (A) and 3 (B) are views for explaining the above-mentioned diode portion diffusion layer. The diffusion layer of the polysilicon diode 10 of the first embodiment is shown in FIG. A closed diffusion layer and a parallel diffusion layer as shown in A) and (B) are formed. FIG. 4 is a plan view showing the layout of the polysilicon diode (polysilicon Di) portion of the first embodiment, which is based on the pattern at the time of trial production, and the vertical length is 500 μm and the horizontal width is 500 μm. : 240μ
m.
【００１７】図５は、本実施例１の等価回路図(５電極)
であり、本実施例１では、この図に示すように、ソ−ス
電極91、ドレイン電極92、ゲ−ト電極93、アノ−ド電極
及びカソ−ド電極である電極14、同15の５電極が独立に
有する構造のものである。FIG. 5 is an equivalent circuit diagram of the first embodiment (five electrodes).
In the first embodiment, as shown in this figure, the source electrode 91, the drain electrode 92, the gate electrode 93, the electrodes 14 and 15 which are the anode electrode and the cathode electrode, and 5 The structure has independent electrodes.
【００１８】次に、この実施例１の半導体装置の動作を
説明すると、この温度検出用ポリシリコンダイオ−ド10
の低電流における順電圧降下は、温度依存性を有するの
で、半導体素子の温度を検出することができ、早い応答
性でゲ−ト電圧の制御回路へ送ることができる。Next, the operation of the semiconductor device of the first embodiment will be described. This temperature detecting polysilicon diode 10 is used.
Since the forward voltage drop at a low current has a temperature dependency, the temperature of the semiconductor element can be detected and can be sent to the control circuit of the gate voltage with a quick response.
【００１９】（実施例２）図６は、本発明の他の実施例
(実施例２)の半導体装置の平面図であり、図７は、本発
明の実施例２の等価回路図(４電極)である。この実施例
２では、前記実施例１の５電極が独立に有する構造のも
のに代えて、図６及び図７に示すように、ソ−ス電極9
1、ドレイン電極92、ゲ−ト電極93の独立した３電極
と、ソ−ス電極91及びアノ−ド電極14を接続した電極端
子との４電極を有する構造としたものである。(Embodiment 2) FIG. 6 shows another embodiment of the present invention.
FIG. 8 is a plan view of a semiconductor device of (Example 2), and FIG. 7 is an equivalent circuit diagram (4 electrodes) of Example 2 of the present invention. In the second embodiment, instead of the structure having the five electrodes independently of the first embodiment, as shown in FIGS. 6 and 7, a source electrode 9 is used.
The structure has four electrodes, namely, three independent electrodes, a drain electrode 92 and a gate electrode 93, and an electrode terminal to which the source electrode 91 and the anode electrode 14 are connected.
【００２０】本実施例２の半導体装置について、前記し
た図１を参照してさらに説明すると、本実施例２では、
図１に示したｐ+層12に接触する電極14とソ−ス電極91
とを接続させた構造よりなり、また、図１に示すｐ+層1
2及びｎ+層４をポリシリコン６の層に垂直に突き抜ける
ように形成した構造よりなる。The semiconductor device of the second embodiment will be further described with reference to FIG. 1 described above.
The electrode 14 and the source electrode 91 in contact with the p + layer 12 shown in FIG.
And p + layer 1 shown in FIG.
2 and the n + layer 4 are formed so as to vertically penetrate the layer of polysilicon 6.
【００２１】本実施例２では、上記したとおり、ｐ+層1
2に接触する電極14とソ−ス電極91とを接続させたの
で、実施例１における電極を１個少なくすることができ
る。従って、本実施例２によれば、ボンデイングワイヤ
−を打つための面積分ペレット面積を小さくできるとい
う利点がある。また、本実施例２では、前記実施例１の
ｐ+層12及びｎ+層４をポリシリコン６の層に垂直に突き
抜けるように形成したため、アルミスパイクによる特性
変動及び順方向電圧(ＶF)、耐圧(ＶZ)等のバラツキを小
さくできるという利点を有している。In the second embodiment, as described above, the p + layer 1
Since the electrode 14 in contact with 2 and the source electrode 91 are connected, the number of electrodes in the first embodiment can be reduced by one. Therefore, according to the second embodiment, there is an advantage that the pellet area can be reduced by the area for hitting the bonding wire. In the second embodiment, the p + layer 12 and the n + layer 4 of the first embodiment are formed so as to penetrate perpendicularly to the layer of polysilicon 6, so that the characteristic fluctuation due to the aluminum spike and the forward voltage (V F ) The advantage is that variations in withstand voltage (V Z ) can be reduced.
【００２２】ここで、本発明の半導体装置について、具
体的に裏付けデ−タとして、図８(本発明の半導体装置
における温度特性「温度−ＶF」を示すグラフ)を用いて
説明する。この図８のグラフに示すように、一層のポリ
シリコンで温度特性を確認した結果、市販されているダ
イオ−ドとほぼ同一の20ｍＶ／℃の温度係数を得ること
ができた。[0022] Here, the semiconductor device of the present invention, specifically supported de - as data will be described with reference to FIG. 8 (a graph showing temperature characteristics "Temperature -V F" in the semiconductor device of the present invention). As shown in the graph of FIG. 8, as a result of confirming the temperature characteristics with one layer of polysilicon, it was possible to obtain a temperature coefficient of 20 mV / ° C. which is almost the same as that of the commercially available diode.
【００２３】[0023]
【発明の効果】以上説明したように本発明は、半導体素
子上に温度検出用ポリシリコンダイオ−ドを設けること
により、半導体素子の接合部に近い温度を検出できるた
め、接合部の温度上昇を応答性よく正確に検出して素子
の破壊を防止できるという効果が生じる。As described above, according to the present invention, by providing the temperature detecting polysilicon diode on the semiconductor element, it is possible to detect the temperature close to the junction of the semiconductor element, so that the temperature rise of the junction can be prevented. There is an effect that the element can be prevented from being broken down by accurately detecting it with high responsiveness.
【００２４】また、本発明は、一層のポリシリコン層で
半導体素子と温度検出用ポリシリコンダイオ−ドとを形
成したため、製造工程を短縮でき、さらに、温度検出用
ポリシリコンダイオ−ドの抵抗成分をポリシリコン層に
垂直に突き抜けるように形成したため、特性のバラツキ
を小さくできるという効果が生じる。Further, according to the present invention, since the semiconductor element and the temperature detecting polysilicon diode are formed of one polysilicon layer, the manufacturing process can be shortened and the resistance component of the temperature detecting polysilicon diode can be shortened. Is formed so as to penetrate perpendicularly to the polysilicon layer, so that there is an effect that variation in characteristics can be reduced.
【図１】本発明の一実施例(実施例１)の半導体装置の要
部断面図。FIG. 1 is a cross-sectional view of essential parts of a semiconductor device according to an embodiment (Embodiment 1) of the present invention.
【図２】本発明の実施例１の半導体装置の平面図。FIG. 2 is a plan view of the semiconductor device according to the first embodiment of the present invention.
【図３】本発明の実施例１のダイオ−ド部拡散層を示す
図であって、(Ａ)、(Ｂ)はその閉じた拡散層、並列拡散
層の平面図。FIG. 3 is a diagram showing a diode portion diffusion layer of Example 1 of the present invention, in which (A) and (B) are plan views of the closed diffusion layer and the parallel diffusion layer.
【図４】本発明の実施例１のポリコンシリダイオ−ド部
のレイアウトを示す平面図。FIG. 4 is a plan view showing a layout of a polyconsolidated diode portion according to the first embodiment of the present invention.
【図５】本発明の実施例１の等価回路図(５電極)。FIG. 5 is an equivalent circuit diagram (five electrodes) of the first embodiment of the present invention.
【図６】本発明の他の実施例(実施例２)の半導体装置の
平面図。FIG. 6 is a plan view of a semiconductor device according to another embodiment (embodiment 2) of the present invention.
【図７】本発明の実施例２の等価回路図(４電極)。FIG. 7 is an equivalent circuit diagram (four electrodes) of the second embodiment of the present invention.
【図８】本発明の半導体装置における温度特性(温度−
ＶF)を示すグラフ。FIG. 8 is a temperature characteristic of the semiconductor device of the present invention (temperature-
A graph showing V F ).
【図９】従来の半導体装置の要部断面図。FIG. 9 is a cross-sectional view of a main part of a conventional semiconductor device.
１ ｎ+基板 ２ ｎ-層 ３ ｐ+層 ４ ｎ+層 ５ 酸化膜 ６ ポリシリコン ７ 酸化膜 ８ リンガラス １０ ダイオ−ド １１ ポリシリコン １２ ｐ+層 １３ ｎ+層 １４ 電極 １５ 電極 ３１ ｐ-層 ３２ ｐ+層 ９１ ソ−ス電極 ９２ ドレイン電極 ９３ ゲ−ト電極1 n + substrate 2 n - layer 3 p + layer 4 n + layer 5 oxide film 6 polysilicon 7 oxide film 8 phosphorus glass 10 diode - de 11 polysilicon 12 p + layer 13 n + layer 14 electrode 15 electrode 31 p - Layer 32 p + layer 91 source electrode 92 drain electrode 93 gate electrode
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 9055−4Ｍ Ｈ０１Ｌ 29/78 ３２１ Ｋ 9055−4Ｍ ３２１ Ｗ (72)発明者 沢田 雅己 東京都港区芝五丁目７番１号日本電気株式 会社内─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication location 9055-4M H01L 29/78 321 K 9055-4M 321 W (72) Inventor Masami Sawada Minato-ku, Tokyo 5-7-1 Shiba NEC Corporation
Claims (4)
有するＭＯＳ型電界効果トランジスタを含む半導体素子
において、その温度を検出できるポリシリコンダイオ−
ド又は抵抗を同一チップ上にポリシリコン一層で形成し
てなることを特徴とする半導体装置。1. In a semiconductor device including a MOS field effect transistor having a gate electrode mainly composed of polysilicon, a polysilicon diode capable of detecting its temperature.
A semiconductor device having a polysilicon layer formed on the same chip.
ポリシリコンダイオ−ド又は抵抗を同一チップ上に形成
してなり、ゲ−ト電極、ソ−ス電極、ドレイン電極、ア
ノ−ド電極、カソ−ド電極の５電極を独立に有すること
を特徴とする請求項１記載の半導体装置。2. A semiconductor device and a polysilicon diode or resistor capable of detecting the temperature of the semiconductor device are formed on the same chip, and a gate electrode, a source electrode, a drain electrode, an anode electrode, and a cathode are formed. The semiconductor device according to claim 1, wherein the five electrodes of the negative electrode are independently provided.
ポリシリコンダイオ−ド又は抵抗を同一チップ上に形成
してなり、ゲ−ト電極、ドレイン電極、カソ−ド電極の
独立した３電極と、ソ−ス電極とアノ−ド電極とを接続
した電極端子の４電極を有することを特徴とする請求項
１記載の半導体装置。3. The semiconductor element and a polysilicon diode or resistor capable of detecting the temperature thereof are formed on the same chip, and three independent electrodes of a gate electrode, a drain electrode and a cathode electrode are provided, 2. The semiconductor device according to claim 1, further comprising four electrodes, which are electrode terminals connecting the source electrode and the anode electrode.
た温度検出用ポリシリコンダイオ−ドを形成する拡散層
が、ポリシリコン層を垂直に突き抜けているポリシリコ
ン層を有することを特徴とする請求項１、請求項２又は
請求項３記載の半導体装置。4. A diffusion layer forming a temperature detecting polysilicon diode formed on the same chip as the semiconductor element has a polysilicon layer which vertically penetrates through the polysilicon layer. The semiconductor device according to claim 1, claim 2, or claim 3.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5326146A JPH07153920A (en) | 1993-11-30 | 1993-11-30 | Semiconductor device |
| KR1019940031862A KR950015755A (en) | 1993-11-30 | 1994-11-29 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5326146A JPH07153920A (en) | 1993-11-30 | 1993-11-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07153920A true JPH07153920A (en) | 1995-06-16 |
Family
ID=18184569
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5326146A Pending JPH07153920A (en) | 1993-11-30 | 1993-11-30 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH07153920A (en) |
| KR (1) | KR950015755A (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005203446A (en) * | 2004-01-13 | 2005-07-28 | Toyota Industries Corp | Semiconductor device with temperature detecting function |
| JP2006093252A (en) * | 2004-09-22 | 2006-04-06 | Sanken Electric Co Ltd | Semiconductor device |
| DE102008045722A1 (en) | 2007-12-25 | 2009-07-09 | Mitsubishi Electric Corp. | Temperature Acquisition System |
| JP2014082519A (en) * | 2013-12-27 | 2014-05-08 | Fuji Electric Co Ltd | Semiconductor device and manufacturing method of the same |
| JPWO2014024595A1 (en) * | 2012-08-09 | 2016-07-25 | 富士電機株式会社 | Semiconductor device and manufacturing method thereof |
| US9543294B2 (en) | 2015-02-09 | 2017-01-10 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device |
| US9548294B2 (en) | 2012-08-09 | 2017-01-17 | Fuji Electric Co., Ltd. | Semiconductor device with temperature-detecting diode |
| JP2017037997A (en) * | 2015-08-11 | 2017-02-16 | 富士電機株式会社 | Semiconductor element and semiconductor element manufacturing method |
| JPWO2015029159A1 (en) * | 2013-08-28 | 2017-03-02 | 三菱電機株式会社 | Semiconductor device |
| US9780012B2 (en) | 2013-12-12 | 2017-10-03 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
| JP2017183581A (en) * | 2016-03-31 | 2017-10-05 | ルネサスエレクトロニクス株式会社 | Semiconductor device and semiconductor apparatus |
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| JP2018120930A (en) * | 2017-01-24 | 2018-08-02 | トヨタ自動車株式会社 | Semiconductor device |
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|---|---|---|---|---|
| JP2005203446A (en) * | 2004-01-13 | 2005-07-28 | Toyota Industries Corp | Semiconductor device with temperature detecting function |
| JP2006093252A (en) * | 2004-09-22 | 2006-04-06 | Sanken Electric Co Ltd | Semiconductor device |
| JP4599963B2 (en) * | 2004-09-22 | 2010-12-15 | サンケン電気株式会社 | Semiconductor device |
| DE102008045722A1 (en) | 2007-12-25 | 2009-07-09 | Mitsubishi Electric Corp. | Temperature Acquisition System |
| DE102008045722B4 (en) * | 2007-12-25 | 2011-12-01 | Mitsubishi Electric Corp. | Temperature Acquisition System |
| US8602645B2 (en) | 2007-12-25 | 2013-12-10 | Mitsubishi Electric Corporation | Temperature detection system |
| US10396065B2 (en) | 2012-08-09 | 2019-08-27 | Fuji Electric Co., Ltd. | Semiconductor device having a temperature-detecting diode |
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| US9461030B2 (en) | 2012-08-09 | 2016-10-04 | Fuji Electric Co., Ltd. | Semiconductor device and method for producing the same |
| US9548294B2 (en) | 2012-08-09 | 2017-01-17 | Fuji Electric Co., Ltd. | Semiconductor device with temperature-detecting diode |
| JPWO2015029159A1 (en) * | 2013-08-28 | 2017-03-02 | 三菱電機株式会社 | Semiconductor device |
| US9716052B2 (en) | 2013-08-28 | 2017-07-25 | Mitsubishi Electric Corporation | Semiconductor device comprising a conductive film joining a diode and switching element |
| US9780012B2 (en) | 2013-12-12 | 2017-10-03 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
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| US9543294B2 (en) | 2015-02-09 | 2017-01-10 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device |
| US11257812B2 (en) | 2015-02-13 | 2022-02-22 | Rohm Co., Ltd. | Semiconductor device and semiconductor module |
| US11495595B2 (en) | 2015-02-13 | 2022-11-08 | Rohm Co., Ltd. | Semiconductor device and semiconductor module |
| US11670633B2 (en) | 2015-02-13 | 2023-06-06 | Rohm Co., Ltd. | Semiconductor device and semiconductor module |
| US11916069B2 (en) | 2015-02-13 | 2024-02-27 | Rohm Co., Ltd. | Semiconductor device and semiconductor module |
| JP2017037997A (en) * | 2015-08-11 | 2017-02-16 | 富士電機株式会社 | Semiconductor element and semiconductor element manufacturing method |
| JP2017183581A (en) * | 2016-03-31 | 2017-10-05 | ルネサスエレクトロニクス株式会社 | Semiconductor device and semiconductor apparatus |
| JPWO2017208734A1 (en) * | 2016-06-03 | 2018-09-27 | 富士電機株式会社 | Semiconductor device |
| WO2017208734A1 (en) * | 2016-06-03 | 2017-12-07 | 富士電機株式会社 | Semiconductor device |
| US10504785B2 (en) | 2016-06-03 | 2019-12-10 | Fuji Electric Co., Ltd. | Semiconductor device |
| JP2018120930A (en) * | 2017-01-24 | 2018-08-02 | トヨタ自動車株式会社 | Semiconductor device |
| JP2021002683A (en) * | 2020-10-02 | 2021-01-07 | ローム株式会社 | Semiconductor device and semiconductor module |
| JP2022033226A (en) * | 2020-10-02 | 2022-02-28 | ローム株式会社 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR950015755A (en) | 1995-06-17 |
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