JPH07153758A - Semiconductor device and manufacturing method - Google Patents

Abstract

PURPOSE:To provide a highly integrated semiconductor device, by reducing a marginal alignment space for forming a wiring. CONSTITUTION:A first polymer resin film 7 is formed on a source/drain diffusion layer 3. The first polymer resin film 7 is made conductive by casting a laser beam thereto to form a first (contact) electrode 10. After a second polymer resin film 8 is formed, a laser beam is cast to form a wiring 11. At this time, an upper part of the first polymer resin film 7 becomes conductive so that a contact area between the conductor 11 and the electrode 10 is enlarged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art Electrodes and wirings of semiconductor devices are mainly made of Cu.
It is mainly formed of Al alloy containing Si or Si. Below M
An OS transistor will be described as an example with reference to FIG.

After the impurities are introduced into the Si substrate 1 to form the well 2, the field oxide film 4 and the gate oxide film 5 are formed. Next, a gate electrode 6 made of polysilicon is formed on the entire surface, and then impurities are ion-implanted to form a low-concentration diffusion layer to be the source / drain 3. Next, after forming a side wall made of an insulating film on the side surface of the gate electrode 6, impurities are ion-implanted again to form a high-concentration diffusion layer to complete the source / drain 3 having the LDD structure. Next, an oxide film 20 is formed on the entire surface and then patterned to form contact holes 21 on the source / drain 3. Next, an Al alloy film is formed on the entire surface and then patterned to form an Al wiring 22 which also serves as a contact electrode.

When forming an upper layer wiring, an interlayer insulating film made of PSG or the like is formed on the Al wiring 22, a through hole is formed on the Al wiring 22, and then an Al alloy film is formed and then patterned. As a result, an upper layer wiring connected to the lower layer Al wiring 22 is formed. In the case of forming wiring of three layers or more, the above steps are repeated.

When a multilayer wiring is formed by using the Al alloy film and the interlayer insulating film made of PSG or the like as described above, the step becomes large and disconnection or the like easily occurs, so that the reliability is lowered.
For this reason, a conductive polymer resin film 23 is provided on the Al wiring 22 in FIG. 3 to make it flat, and laser light irradiation is selectively performed to make the polymer resin film conductive and connect the upper wiring to the Al wiring 22. The forming method is disclosed in, for example, JP-A-58-12.
No. 392 publication.

[0006]

However, among the above-mentioned conventional methods of forming electrodes and wirings, in the method of using an Al alloy film, in addition to disconnection due to the formation of steps, a photolithography process for forming contact holes and electrodes. If the misalignment occurs, the connection between the diffusion layer and the contact electrode becomes insufficient and the contact resistance increases. The increase in contact resistance is the same in the case of connection between wirings. For this reason, there is a problem in that the alignment margin must be increased and the degree of integration cannot be increased.

When the conductive polymer resin film is used for forming the wiring, the step difference is eliminated as compared with the case where the Al alloy film is used, but the contact electrode is formed of the Al alloy and, moreover, because of the connection between the wirings. Since a large margin is required for the conduction by the light irradiation, the same problem as in the case of using the Al alloy film described above occurs.

An object of the present invention is to provide a semiconductor device and a method of manufacturing the same in which the alignment margin in wiring formation is reduced to increase the degree of freedom in design and the degree of integration is improved.

[0009]

A semiconductor device according to a first aspect of the present invention comprises a diffusion layer formed on the surface of a semiconductor substrate, a contact electrode made of a polymer resin film formed on the diffusion layer, and the contact. And a wiring made of a polymer resin film connected to the electrodes.

In the method of manufacturing a semiconductor device of the second invention, a step of introducing an impurity into the surface of a semiconductor substrate to form a diffusion layer and a first polymer resin film which becomes conductive by light irradiation are formed on the entire surface. A step of irradiating the contact electrode formation region of the first polymer resin film with light to form a contact electrode connected to the diffusion layer, and a wiring after forming a second polymer resin film on the entire surface And irradiating the formation region with light to form a wiring that is conductive to the upper layer of the first polymer resin film and is connected to the contact electrode.

The polymer resin which becomes conductive by irradiation with light is mainly composed of polyimide, polyacrylonitrile, phenol resin, etc. having a π-electron structure in the side chain, to which a sensitizer, a crosslinking agent, etc. are added. That is, the exposed portion exhibits conductivity and the non-exposed portion maintains the insulating property upon irradiation with X-rays or laser light.

[0012]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a sectional view of a semiconductor chip for explaining an embodiment of the present invention. The manufacturing steps will be described below in order.

After the well 2, the field oxide film 4, the gate oxide film 5 and the gate electrode 6 made of polysilicon are formed on the Si substrate 1 by the same process as in the conventional method, impurities are ion-implanted to form the source / drain 3. A concentration diffusion layer is formed. Next, after forming a side wall made of an oxide film on the side surface of the gate electrode, impurities are ion-implanted again to form a high-concentration diffusion layer to complete the source / drain 3 having the LDD structure.

Next, the first surface is made conductive by light irradiation.
About 0.6μ of polymer resin film 7 of
It is formed to a thickness of m. Next, the first polymer resin film 7 is made electrically conductive by selectively irradiating it with a laser beam to form a first electrode 10 for contact connecting to the source / drain 3.

Then, a second polymer resin film 8 is formed on the entire surface by about 0.
After being formed to a thickness of 4 μm, it is irradiated with laser light to be made conductive, and the wiring 11 connected to the first electrode 10 is formed.
At this time, the diameter and focus of the laser beam are adjusted to make the upper layer of the first polymer resin film 7 conductive.

If necessary, a third polymer resin film 9 is formed below, and is made conductive by laser light irradiation to form a second electrode 12 for a through hole. These operations are repeated when forming a multilayer wiring.

As described above, in this embodiment, when the wiring 11 is formed by making the second polymer resin film 8 conductive, the upper layer of the lower first polymer resin film 7 is also made conductive.
The contact area between the first electrode 10 and the wiring 11 increases, and the connection becomes more complete.

For example, the wiring design rule is 1.4 μm,
When the cross section of the contact hole is 1.2 μm × 1.2 μm and the misalignment limit is 0.2 μm, as shown in FIG.
Is 0.6 μm (half of the contact hole), there is insufficient contact between the first electrode 10 and the wiring 11A made of the second polymer resin film and the connection resistance is high in the conventional method. The product becomes defective. On the other hand, according to the present embodiment, the wiring 11 is composed of the wiring 11B and the wiring 11A which are electrically conductive up to the upper layer portion of the first polymer resin film 7. Therefore, the first electrode 10 The contact area with and the connection resistance does not increase. This also applies to the case where the lower layer wiring and the upper layer wiring are connected. That is, the limit of misalignment is changed from 0.2 μm to 0.6 μm, the design rules are relaxed, the degree of freedom in layout is expanded, and a semiconductor device with a higher degree of integration can be obtained.

According to this embodiment, the yield decrease (about 10%) due to the misalignment can be reduced, and the chip size can be reduced by about 5%.

[0020]

As described above, according to the present invention, the alignment margin for wiring formation can be reduced, so that the semiconductor device and the method of manufacturing the semiconductor device can be obtained in which the degree of freedom of layout and the degree of integration at the time of design are improved. There is an effect.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor chip for explaining an embodiment of the present invention.

FIG. 2 is an enlarged cross-sectional view of an electrode portion for explaining the effect of the embodiment.

FIG. 3 is a sectional view of a semiconductor chip for explaining a conventional semiconductor device.

[Explanation of symbols]

 1 Si substrate 2 well 3 source / drain 4 field oxide film 5 gate oxide film 6 gate electrode 7 first polymer resin film 8 second polymer resin film 9 third polymer resin film 10 first electrode 11 Wiring 12 Second electrode 20 Oxide film 21 Contact hole 22 Al wiring 23 Conductive polymer resin film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 29/78 21/336 H01L 21/90 A 8826-4M 29/46 Z 7514-4M 29/78 301 Y

Claims (3)

[Claims] 1. A diffusion layer formed on the surface of a semiconductor substrate, a contact electrode made of a polymer resin film formed on the diffusion layer, and a wiring made of a polymer resin film connected to the contact electrode. A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein the polymer resin film is a resin film which becomes conductive when irradiated with light. 3. A step of forming a diffusion layer by introducing impurities into the surface of a semiconductor substrate, a step of forming a first polymer resin film which becomes conductive by light irradiation, and a step of forming the first polymer resin. The step of irradiating the contact electrode forming region of the film with light to form a contact electrode connected to the diffusion layer, and the step of irradiating the wiring forming region with light after irradiating the second polymer resin film on the entire surface. 1. A method of manufacturing a semiconductor device, comprising the step of forming a wiring that is electrically conductive up to the upper layer portion of the polymer resin film of 1 to connect to the contact electrode.