JPH07153298A - Fail data processing device - Google Patents

Abstract

PURPOSE:To shorten a processing time of fail data by connecting a fail memory to a semiconductor memory means and reading memory information of this memory means in a processor and processing. CONSTITUTION:A fail analyzing section 31 comprises semiconductor memory sections 311-314 and processors 411-414 arranged corresponding to the above. The memory sections 311-314 are not especially restricted, but is made a RAM, and arranged corresponding to a fail memory. The memory section 311-314 are connected to a fail memory section through a proper interface cable and the like. Owing to that, a disk and the like are not require to lie between them in transferring a fail data from a fail memory section to the memory section 311-314. The memory section 311-314 are connected to a processor bus of the corresponding processors 411-414, and memory access of the corresponding memory sections 311-314 can be performed by the processors 411-414.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory evaluation technique by fail bit map analysis, and further to an information processing device for fail bit map analysis.

[0002]

2. Description of the Related Art In semiconductor memory evaluation, failure analysis using a fail bit map is one of the most important techniques. The cells of the semiconductor memory are regularly arranged in a matrix, and each memory cell has a one-to-one correspondence with an address input from the outside. In a normal evaluation, the information written at a certain address is read and It is determined whether the output data and the expected value match. The fail bit map displays such a determination result at the position corresponding to each memory cell, and is a powerful analysis means for visually indicating a failure analysis.

In a conventional memory inspection using a fail memory, first write fail data to the fail memory, and then read a defect determination result of the semiconductor memory from the fail memory at a workstation or the like to be a target of a defect relief algorithm. It is possible to perform superimposing processing up to the following scale, rearrange the analysis means so that it corresponds to the physical arrangement of the memory cells that make up the semiconductor memory, and observe the distribution state of defective bits macroscopically. Therefore, processing such as contraction of multiple bits is performed.

As an example of a document describing a failure analysis method using a fail bit map, "Pro.
c. IEEE'90 ICMTS Vol3 Marc
h 1990 P175 ”.

[0005]

However, in the above-mentioned prior art, when processing a large amount of fail data, the fail data is stored in a hard disk or the like and is read out and processed by a processor.
Due to the increase in the amount of data accompanying the increase in capacity of semiconductor memory,
It tends to take a long time until the analysis result is obtained.
When the present inventor examined it, most of the time required for the data processing is occupied by the transfer time of the fail data, which is the main factor for reducing the time reduction until the result of the failure analysis processing is obtained. Was found.

An object of the present invention is to shorten the processing time of fail data.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, semiconductor memory means coupled to a fail memory for holding fail data, for taking in the fail data stored in the fail memory, and storage information of the semiconductor memory means are read to store the fail data. A fail data processing device is configured to include a plurality of processors capable of parallel processing.

[0010]

According to the above-mentioned means, the fail memory is coupled to the semiconductor memory means, and the information stored in the semiconductor memory means is read and processed by the processor. In the transfer of the fail data and the transfer of the fail data from the semiconductor storage means to the processor, it is not necessary to interpose a storage medium such as a hard disk, which achieves the reduction of the fail data transfer time. The parallel processing of the fail data by the plurality of processors achieves the reduction of the fail data processing time.

[0011]

1 shows a memory inspection device to which an information processing device according to the present invention is applied.

As shown in FIG. 1, this memory inspection apparatus has a probing test, a DC characteristic test (DC test), and an AC characteristic test (A) of a memory to be inspected (DUT) 12.
A measuring device 15 for performing (C test), a comparison circuit 13 for comparing the inspection data Di for writing to the inspection target memory 12 with the data Do read from the memory 12, and the output of the comparison circuit 13 is stored. Fail memory unit 40 for controlling the controller 1 for controlling the operation of each unit
0, a condition setting unit 20 for setting various conditions related to fail data collection for this controller 10,
With respect to the memory 12 to be inspected, its operating power supply Vc
c, a power supply unit 14 for supplying a high voltage Vpp for writing as needed, a fail analysis unit 31 for analyzing fail data stored in the fail memory unit 40, and for displaying the analysis result. The display unit 32 of is included.

Since the inspection conditions differ depending on the type and storage capacity of the inspection target memory 12, the condition setting unit 20 can set appropriate inspection conditions according to the type and storage capacity of the inspection target memory 12. It has become.
Although not particularly limited, such condition setting unit 20 includes
Keyboard etc. are applied.

The controller 1 is not particularly limited.
For 0, a control signal CNT for controlling the operation of each unit by executing a predetermined program, an address signal Ai (n), and a processor for generating inspection data Di are applied. A read / write signal R / W * (* indicates low active) is generated as one of the operation timing signals generated by such a controller 10, and the read / write signal R / W * is generated. When is low level, the inspection data Di is written to the inspection target memory 12. The inspection data Di is also transmitted to the comparison circuit 13 for the fail test. In addition, the controller 10 causes the memory address signal Ai
(N) is generated, which is the inspection target memory 12,
The data is transmitted to the fail memory unit 40.

The data written in the memory 12 to be inspected is read / write signal R / W by the controller 10.
When * is set to high level, it is read and transmitted to the comparison circuit 13. Then, in the comparison circuit 13, the write data Di to be written into the memory 12 to be inspected and the data Do actually read from the memory 12 are compared on a bit-by-bit basis. The logic output Dfi of the comparison circuit 13 is set to low level, and if they do not match, it is set to high level.
The result of such comparison is taken into the fail memory unit 40 in real time.

The fail memory unit 40 is not particularly limited, but the fail memory 42 and this fail memory 42
And a memory control unit 41 having a control function for writing and reading data to and from. This fail memory 4
2 is not particularly limited, but a plurality of fail memories FM
1, FM2 ... FMn are included. Address control of the plurality of fail memories FM1, FM2 ... FMn is performed by a fail memory address signal Aj output from the memory control unit 41.

Here, according to the conventional method, the comparison circuit 13
The result of the comparison is written in the fail memory 42, and in the subsequent failure analysis processing, the storage content of the fail memory 42 is taken into a hard disk or the like as a data file and then processed by a workstation or the like. The physical state of the data is changed to a target state by reduction or the like. However, in that case, it takes time to write and read the information to and from the hard disk due to the increase in the amount of fail data accompanying the increase in the capacity of the memory to be inspected. .

Therefore, in this embodiment, in order to shorten the information transfer time, the failure analysis time, and the inspection cost, the semiconductor memory means coupled to the fail memory and the semiconductor memory means. There is provided a fail analysis unit 31 including a plurality of processors capable of reading the stored information of and processing the fail data in parallel.

FIG. 2 schematically shows the structure of the fail analysis unit 31.

As shown in FIG. 2, the fail analysis unit 31 is not particularly limited, but four semiconductor storage units 311 to 314 serving as semiconductor storage means and four semiconductor storage units arranged corresponding thereto. Processors 411-414. Although not particularly limited, the semiconductor storage units 311 to 314 are RAMs (random access memories) and are arranged corresponding to the fail memories FM1 to FMn. The semiconductor storage units 311 to 314 may be physically separate memories, or what is physically one memory is divided into four storage areas by system address mapping. However, in order to speed up the processing, dynamic RA
It is better to apply a static RAM that can operate at a higher speed than M. The above four semiconductor memory units 311 to 31
4 is connected to the fail memory unit 40 via an appropriate interface cable or the like. Therefore, from the fail memory unit 40 to the semiconductor storage units 311 to 311
The fail data transfer to 314 can be performed at high speed without interposing a disk or the like. In the present embodiment, although not particularly limited, a fail map 420 of each chip of the memory to be inspected is written in each of the four semiconductor memory units 311 to 314. That is, the same fail data is written in the four semiconductor memory units 311 to 314.

The semiconductor storage units 311 to 314 are coupled to the processor buses of the corresponding processors 411 to 414, respectively, and the processors 411 to 414 enable the memory access of the corresponding semiconductor storage units 311 to 314. It Therefore, the semiconductor storage unit 311
~ 314 from the corresponding processors 411-4
Data transfer to 14 (data reading) is performed at high speed. Of course, from this semiconductor storage unit 311 to 314,
Also in the data transfer to the corresponding processors 411 to 414, the interposition of a disk or the like is unnecessary.

FIG. 3 shows the flow of processing by the apparatus of this embodiment.

According to the flow of FIG. 3, the inspection target memory 12
Is a wafer state or a chip state, the probing test is performed by the measuring device 15 (step S3).
1). This test is made possible by mechanically contacting the probe with the bonding pad of the chip and measuring the electrical characteristics. What is judged to be non-defective in this test is sent to the next process. Next, a DC test, A
The C test is performed (step S32). In the DC test, the external terminal of the memory 12 to be inspected and the current passing through this external terminal are measured as a direct current. In the AC test, the measuring device 15 measures the propagation delay time between the input and output terminals of the memory 12 to be inspected, the transition time of the output waveform, the setup time, the hold time, the minimum clock pulse width, the maximum clock frequency, and the like. . After such a test is completed, pass / fail determination and fail address acquisition are performed (step S33). In this embodiment, a plurality of processors 411 to 414 are provided,
As a result, a plurality of types of processing for fail data can be executed in parallel. Although not particularly limited, the processing for fail data in the apparatus of this embodiment is roughly classified into data processing such as contraction (step S34) and classification of defective modes (step S36).

In the above-mentioned reduction processing, since the distribution state of defective bits can be observed macroscopically, the fail data is reduced by calculating the logical sum of the data in units of a plurality of adjacent bits (step S34). For example, if the logical sum of the data is obtained in units of adjacent 4 bits, 4 bits can be reduced, and as a result, the amount of information is reduced to 1/4. Then, such a contraction result is displayed or printed out (step S35).

Although not particularly limited, when the reduction processing is performed in the processor 411, the failure mode analysis can be performed in the other processors 412 to 414.

In the failure mode classification, the failure state is classified into a specific pattern (step S36), which is possible by detecting the specific pattern of the defective portion from one fail map 420. The detection result is displayed or printed out (step S37). In this embodiment, since the number of semiconductor memory units and processors is four, the processor 41 is used as described above.
When the reduction processing is performed in 1, the failure mode analysis is performed by the other three processors. In that case, as shown in FIG. 4, if the defective portion has a vertical line shape, it is a word line defect, and if the defective portion has a horizontal line shape, a bit line defect, If the defective portion is dot-like, it is determined to be a bit defect.
In addition, when more processors are provided, it is possible to recognize a mat defect or the like in a case where the defective part is gathered in an area having a defect. Such a defect analysis process is relatively easily realized by pattern matching based on a reference pattern set in consideration of past defect pattern information and the configuration of the inspection target memory.

According to the above embodiment, the following operational effects can be obtained.

(1) The fail memory 42 is coupled to the semiconductor storage units 311 to 314, and the semiconductor storage units 311 to 311 are connected.
The storage information of 314 is read and processed by the processors 411 to 414 to transfer the fail data from the fail memory 42 to the semiconductor storage unit, and the fail data from the semiconductor storage units 311 to 314 to the processors 411 to 414. Since the transfer does not require the intervention of a storage medium such as a hard disk, high-speed transfer of fail data is possible.

(2) The fail data processing time can be shortened by performing parallel processing of the fail data by the plurality of processors 411 to 414, as compared with the case where different fail data processing is executed by one processor over time. You can Further, since most of the time required for data processing is occupied by the transfer time of fail data, the fail data processing result is obtained by the high-speed transfer which is the effect of (1) and the parallel processing by the plurality of processors. It is possible to greatly reduce the overall processing time until the above is obtained.

(3) Due to the effects of the above (1) and (2), the time required for fail data processing is shortened, so that the inspection cost can be reduced.

FIG. 5 shows another embodiment.

In the above embodiment, four semiconductor memory units 311 are used.
Although the same data is transferred to each of ˜314, different data are transferred in the embodiment shown in FIG. That is, the fail map 420 obtained in the fail memory unit 42 is divided into four as shown by broken lines L1 and L2, and the divided maps are transferred to the semiconductor storage units 311 to 314, respectively. Processor 4
In 11 to 414, the pieces divided as described above are to be processed. The specific content of this processing is not particularly limited, but is similar to the reduction processing or the failure mode classification as in the above embodiment.

The invention made by the present inventor has been specifically described based on the embodiments, but the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above embodiment, the semiconductor memory unit 3
The number of 11 to 314 and the number of processors 411 to 414 are both four, but the number is not limited to this, and can be two or three, or five or more. Further, in the above-described embodiment, the contraction process and the failure mode classification are given as examples of the fail data process. However, the process is not limited to this, and a plurality of processors can execute other processes in parallel. .

In the above description, the case where the invention made by the present inventor is mainly applied to the memory inspection apparatus which is the field of application which is the background of the invention has been described, but the present invention is not limited to this and is applied to an LSI test apparatus or the like. It can be widely applied.

The present invention can be applied on condition that at least fail data is handled.

[0037]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the fail memory is coupled to the semiconductor memory means, and the stored information in the semiconductor memory means is read and processed by the processor, whereby the fail data is transferred from the fail memory to the semiconductor memory means and the semiconductor memory is stored. In the transfer of fail data from the means to the processor, it is not necessary to interpose a storage medium such as a hard disk, and therefore high speed transfer of fail data is possible. Then, the fail data processing time can be shortened by performing the parallel processing of the fail data by the plurality of processors.

[Brief description of drawings]

FIG. 1 is a block diagram of a configuration example of a memory inspection device that is an embodiment of the present invention.

FIG. 2 is a block diagram of a configuration example of a fail analysis unit included in the memory inspection device.

FIG. 3 is a flowchart of main processing in the memory inspection device.

FIG. 4 is an explanatory diagram of defective mode classification in the memory inspection device.

FIG. 5 is an explanatory diagram of a fail analysis unit and a processing target there according to another embodiment.

[Explanation of symbols]

 10 controller 12 inspection target memory 13 comparison circuit 14 power supply unit 15 measuring instrument 20 condition setting unit 31 fail analysis unit 32 display unit 40 fail memory unit 41 memory control unit 42 fail memory 311 to 314 semiconductor storage unit 411 to 414 processor 420 fail map

Claims (3)

[Claims] 1. A processing method for processing the fail data, comprising: a fail memory for holding fail data obtained by comparing write data to the test object memory and read data from the test object memory. In the fail data processing device, the semiconductor memory means coupled to the fail memory for fetching the fail data stored in the fail memory, and the stored information of the semiconductor memory means can be read to process the fail data in parallel. A fail data processing device comprising a plurality of processors. 2. The fail data processing device according to claim 1, wherein when one processor compresses the fail data, another processor performs a failure mode classification process. 3. The fail data processing device according to claim 2, wherein the failure modes in the failure mode classification processing include a word line failure and a bit line failure of the inspection target memory.