JPH07142940A - Mosfet power amplifier - Google Patents

Abstract

PURPOSE:To reduce the invalid current of a power output stage, to reduce cross-over distortion and to efficiently drive a MOSFET power amplifier by providing offset stages before and behind a power output stage and providing amplifier stages amplifying input signals before and behind the offset stages. CONSTITUTION:The positive side offset (level shift) stage 6 for PMOSFET Q1 and the negative side offset (level shift) stage 7 for NMOSFET Q2 are provided for the gate voltage bias of PMOSFET Q1 and NMOSFET Q2 in the power output stage 5. A positive side differential amplifier stage 8 is provided in the prestage of the positive side offset stage 6 and a negative side differential amplifier stage 9 in the prestage of the negative side offset stage 7. Voltage inputted to an input terminal 1 is impressed on the inverted input means of the differential amplifying stages 8 and 9. In such a case, the non- inverted input-sides of the differential amplifying stages 8 and 9 are connected to an output terminal 2, and they function as a voltage follower.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOSFET power amplifier for amplifying an audio signal in portable electric equipment such as portable audio products, portable personal computers, portable multimedia equipment and mobile phones.

[0002]

2. Description of the Related Art Power amplification of a voice signal of a portable electric device has conventionally been realized by a bipolar transistor circuit, but with the decrease of the power supply voltage to be used,
The collector-emitter saturation voltage (Vce) inherent in the bipolar transistor lowers the utilization efficiency of the output voltage, resulting in insufficient output power or a problem of reduced power efficiency. Came.

Therefore, a booster circuit has been added to boost the power supply voltage to operate the power amplifying section, but the improvement in power efficiency has not progressed.

On the other hand, attempts have been made to construct a power amplifier using FET elements. However, although it is applied to a field where quality requirements are not strict, it has not been put to practical use in the field of hi-fi unless it can be operated at a sufficiently high voltage.

This is because the FET is inferior to the bipolar transistor in the ability to drive the current, and if it is attempted to drive the electric power as much as the bipolar transistor, the reactive power (through current) is consumed more than that. Is inevitable.

By the way, in recent years, a MOSFET power amplifier as shown in FIG. 4 has been put into practical use in which a method of controlling a bias current according to an output amplitude is put into practical use to increase the current driving capability only when the amplitude is large and to improve the power efficiency. Proposed (IE
EE J.SOLID STATE CIRCUITS, Vol.SC-17, no.6, pp929-98
2, Dec.1982). The circuit of FIG. 5 is called a quasi-source follower power amplifier. In the figure, 1 is an input terminal, 2 is an output terminal, 3 is a positive amplification stage, and 4 is a negative amplification stage. 5 is a power output stage of CMOS push-pull configuration,
Output PMOSFET Q1 and output NMOSFET Q2
Consists of.

Further, in such a quasi-source follower power amplifier, in order to reduce power consumption when there is no signal input,
As shown in FIG. 5, a method of providing an input offset to the amplification stages 3 and 4 has also been proposed. V1 and V2 are input offset voltages (IEEE J.SOLID STATE CIRCUITS, V
ol.SC-20, no.6, pp1200-1205, Dec.1982).

[0008]

In the quasi-source follower power amplifier as described above, the reactive current (through current) is reduced in the gates of the MOSFETs Q1 and Q2 of the power output stage 5 when there is no signal input, and It must be controlled stably so that crossover distortion is also reduced.

That is, if there is an offset in the amplification stages 3 and 4 and the output voltage thereof shifts from a predetermined voltage, an excessive reactive current flows in the MOSFETs Q1 and Q2 of the power output stage 5, or conversely deeply. There are problems such as reverse bias and large crossover distortion.

Further, an offset is provided on the input side in FIG.
In the quasi-source follower power amplifier shown in (1), since the offset voltage is amplified by the amplification stages 3 and 4, symmetry (identity) is required for the amplification stages 3 and 4, but this is difficult.
In the power output stage 5 including the OSFETs Q1 and Q2, the above-mentioned reverse bias is likely to be larger, and the crossover distortion is more likely to be significant.

On the contrary, in order to reduce the amount of reverse bias, it is necessary to set the offset voltage to a very small value, but it is greatly affected by variations in manufacturing.

It is an object of the present invention to solve the above problems by performing stable offset, to realize a small reactive current and low crossover distortion in the power output stage, and to enable efficient driving of the MOSFET power amplifier. Is to provide.

[0013]

SUMMARY OF THE INVENTION An object of the present invention is to provide a push-pull type MOSF whose power output stage has a CMOS structure.
In the ET power amplifier, an offset stage is provided in front of the power output stage, an amplification stage for amplifying an input signal is provided in front of the offset stage, and the gate bias voltage of the MOSFET of the power output stage is set in the offset stage. This is achieved by a MOSFET power amplifier characterized in that

In a push-pull type MOSFET power amplifier having a CMOS power output stage, a gate bias of the MOSFET of the power output stage is provided in a feedback circuit from the power output stage to an amplification stage for amplifying an input signal. It will also be achieved by a MOSFET power amplifier characterized by the provision of a resistor network for setting the voltage.

[0015]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a circuit diagram of the power amplifier of the first embodiment. In this embodiment, the PMOSFET Q1 and NM of the power output stage 5 are
For gate voltage bias of OSFETQ2, PMO
A positive offset (level shift) stage 6 for SFET Q1 and a negative offset (level shift) stage 7 for NMOSFET Q2 are provided. The positive side differential amplification stage 8 is provided in front of the positive side offset stage 6 and the negative side offset stage 7 is provided.
The negative side differential amplification stage 9 was provided in the preceding stage, and the voltage input to the input terminal 1 was applied to the inverting input terminals of both the differential amplification stages 7 and 8. The non-inverting input sides of the two differential amplifier stages 8 and 9 are connected to the output terminal 2 and each function as a voltage follower.

The positive side offset stage 6 has a PMOSFET Q3 which receives the output of the positive side differential amplifier stage 8 and N which is a constant voltage bias.
It is composed of a circuit in which the MOSFET Q4 is CMOS-connected, and the negative side offset stage 7 is a constant voltage bias PMOSF.
NMOSF that receives the output of ETQ5 and the negative differential amplifier stage 9
It is composed of a circuit in which the ETQ6 is CMOS-connected. Vs
1 is a bias voltage.

The positive side differential amplifier stage 8 includes NMOSFETs Q7 and Q8 which are differentially connected and a PMOSFET Q which is current mirror connected as an active load of the differential connection circuit.
9, Q10, NMOSFET functioning as an operating current source
It is composed of Q11. Vs2 is a bias voltage.

Further, the negative-side differential amplifier stage 9 includes PMOSFETs Q12 and Q13 which are differentially connected, and an NMOSFE which is current-mirror connected as an active load of the differential connection circuit.
TQ14, Q15, PMOS functioning as operating current source
It is composed of a FET Q16.

Now, when a voltage is input to the input terminal 1, the difference voltage between the voltage of the output terminal 2 which is fed back to the non-inverting input side of both the differential amplification stages 8 and 9 is the differential amplification stage 8 or the difference. The MOSFET Q of the power output stage 5 is amplified in the dynamic amplifier 9 so that the voltage of the output terminal 2 becomes equal to the voltage of the input terminal 1.
1, Q2 is controlled.

Therefore, when there is no signal input to the input terminal 1, the voltage at the input terminal 1 is half the power supply voltage Vdd (V
dd / 2), and the voltage appears at the output terminal 2.

When there is no signal, the gate voltage of the power output stage 5 is the threshold voltage (Vt) of the MOSFETs Q1 and Q2.
A smaller value than h) is desirable for reducing the reactive current. There is a contradictory relationship between reducing the reactive current and reducing the crossover distortion, but both can be satisfied by setting the offset optimally.

Therefore, in this embodiment, the offset stage 6,
In 7, the gate voltage to be output to the power output stage 5 is shifted by several V according to the Vth of the MOSFETs Q1 and Q2 of the power output stage 5.

To this end, in the offset stage 6, the size ratio of the MOSFETs Q3 and Q4 (channel width W / channel length L) is set, and in the offset stage 7, the size ratio of the MOSFETs Q5 and Q6 is set appropriately. .

Now, for example, the PMOSF of the power output stage 5
Assuming that the threshold value (Vth) of ETQ1 is 650 mV, the gate voltage (Vgs) when there is no signal is 1 at this time.
If the output voltage of the offset stage 6 is set to 50 mV and the cutoff is performed at that time, a margin of 500 mV can be provided therein.

Therefore, the input voltage range in which the drain of the PMOSFET Q1 is in a floating state is 500
mV / G (where G is the total gain of the amplification stage 6 and the differential amplification stage 8) and can be set to several mV or less, so that the crossover distortion can be kept small.

On the other hand, in the method of applying the offset voltage to the input side of the amplification stages 3 and 4 as in the circuit of FIG. 5, the voltage that can be intentionally generated is at least several tens mV.
This is at best, and when this is voltage-amplified and used for shifting the gate voltage of the power output stage, stable control is extremely difficult considering that manufacturing errors are also amplified. For example, even when the gains of the amplification stages 3 and 4 are set low and the input offset voltage is set to a relatively large value, the input offset voltage directly reduces the input voltage range, resulting in a narrow operating voltage range.

As described above, in the power amplifier of the first embodiment shown in FIG. 1, it is possible to prevent an increase of the through current which is ineffective in the power output stage 5. Therefore, not only the idling current when there is no signal can be suppressed to such a small value that the crossover distortion does not increase, but also the feedback that increases the current consumption in other circuit parts is not required during operation. , Efficient offset is possible.
Further, since an intentional offset voltage is not generated on the input side, the input voltage range can be set wide without being affected by the offset, and a large amplitude operation can be performed.

FIG. 2 is a diagram showing a power amplifier of the second embodiment. The same components as those of the power amplifier of the first embodiment shown in FIG. 1 are designated by the same reference numerals. Here, one system of differential amplification stage 10 is used. This differential amplification stage 10
Is composed of PMOSFETs Q17 and Q18 which are differentially connected, NMOSFETs Q19 and Q20 which are current-mirror connected as an active load of the differential connection circuit, and PMOSFET Q21 which functions as an operating current source. Further, the positive-side offset stage 11 has the same configuration as the negative-side offset stage 7, and the PMOSFET Q is biased at a constant voltage.
22, NMOSFET Q for receiving the output of the differential amplification stage 10
It consists of 23.

In the power amplifier of the second embodiment, since the input side is composed of one system of differential amplification stages, the cost is higher than that of the case of using the two systems of differential amplification stages described in FIG. In addition to being advantageous, it is possible to reduce the influence of a random offset error that occurs in two or more circuits.

FIG. 3 is a diagram showing a power amplifier of the third embodiment. Here, in the circuit of FIG. 4 described above, an offset is set by a resistor network on the feedback side of the amplification stages 3 and 4 and the power output stage 5.

This offset is caused by resistors R1 to R3 connected in series between the power source and ground, feedback resistors R4 and R5 connected between the common connection point of the resistors R1 and R2 and the output terminal 2, and a resistor R.
2 and R3 are connected in common and a feedback resistor R6 and R7 connected between the output terminal 2 and resistors R4 and R5.
Is connected to the non-inverting input terminal of the amplification stage 3 by a resistor R6.
The common connection point of R7 and R7 is connected to the non-inverting input terminal of the amplification stage 4. Here, as the resistors R1 and R3, for example, 10
100 to 200Ω can be used as KΩ and R2, 100KΩ as R4 and R6, and 5KΩ as R5 and R7.

In the third embodiment of FIG. 3, a potential difference of [R2Vdd / (R1 + R2 + R3)] can be provided across the resistor R2. Thereby, the relative offset amount (difference in offset amount) between the amplification stages 3 and 4 can be set. The offset amount and gain of the positive amplification stage 3 are set by the ratio of the resistors R4 and R5, and the gate voltage bias value of the PMOSFET Q1 is determined by this. Further, the offset amount and the gain of the negative side amplification stage 4 are set by the ratio of the resistors R6 and R7.
The gate voltage bias value of MOSFET Q2 is determined.

As described above, since the voltage division by the resistance network is used to generate the offset voltage, the reactive voltage is small and the offset voltage with which crossover distortion is small is finely stabilized to a relatively small value. The setting can be made flexibly, and the load on the arrangement on the substrate at that time can be reduced. The position of taking out the resistor can be performed in the wiring process close to the final process in the semiconductor manufacturing process, and trimming can be performed to complement the manufacturing variation of transistors and the like. Furthermore, the offset amount can be adjusted without changing the circuit shape, and master slice is also possible.

[0034]

As described above, according to the present invention, it is possible to generate an offset voltage that satisfies both the reactive current and the crossover distortion that are in a trade-off relationship.
At this time, since the offset stage is provided immediately before the power output stage, it is possible to prevent the generated offset voltage from adversely affecting the operating voltage range. Further, this offset can be generated by voltage division by a resistance network, and it becomes possible to set a fine and stable value in a stable and flexible manner, and at that time, the load imposed on the arrangement on the substrate is reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a power amplifier according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a power amplifier according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a power amplifier according to a third embodiment of the present invention.

FIG. 4 is a block diagram of a conventional power amplifier.

FIG. 5 is a block diagram of another conventional power amplifier.

[Explanation of symbols]

1: input terminal, 2: output terminal, 3: positive amplification stage, 4: negative amplification stage, 5: power output stage, 6: positive offset stage,
7: Negative side offset stage, 8: Positive side differential input stage, 9: Negative side differential input stage, 10: 1 system differential input stage.

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H03K 17/16 L 9184-5J 17/687

Claims (3)

[Claims] 1. A push-pull MOSFET power amplifier having a power output stage of a CMOS structure, wherein an offset stage is provided in front of the power output stage, and an amplification stage for amplifying an input signal is provided in front of the offset stage. In the offset stage, the gate bias voltage of the MOSFET of the power output stage is set.
OSFET power amplifier. 2. The offset stage is a P of the power output stage.
Positive offset stage for MOSFET side and NMOSFE
The negative offset stage for the T side is provided separately, and the amplification stage is provided as a differential input stage common to the positive offset stage and the negative offset stage, or the positive side for the positive offset stage. The MOSFET power amplifier according to claim 1, wherein a differential input stage and a negative differential input stage for the negative offset stage are provided separately. 3. A push-pull MOSFET power amplifier having a CMOS power output stage, wherein a gate bias of the MOSFET of the power output stage is provided in a feedback circuit from the power output stage to an amplification stage for amplifying an input signal. A MOSFET power amplifier comprising a resistor network for setting a voltage.