JPH07141412A - Method for judging malfunction of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To quickly and correctly predict whether or not a semiconductor integrated circuit performs malfunction after preparing a pattern layout. CONSTITUTION:Based on pattern layout information 1, an equivalent circuit composed of a clock line and a clock line driver is constituted, a clock skew value 5 is obtained by executing circuit simulation 4 based on in and the flip- flop of conditions for most easily causing the malfunction is retrieved 8 based on the clock skew value 5 and circuit connection information 6. Then, by executing the circuit simulation 9 again after connecting the flip-flop to the equivalent circuit, whether or not the flip-flop performs the malfunction is judged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for determining malfunction of a semiconductor integrated circuit. In recent years, with the increase in scale of semiconductor integrated circuits, malfunction of circuits caused by time lag between clocks supplied to flip-flops has become a problem. An object of the present invention is to provide a method for determining whether or not a semiconductor integrated circuit malfunctions after creating a pattern layout.

[0002]

2. Description of the Related Art Some large-scale semiconductor integrated circuits of recent years include several hundred to several thousand flip-flops, as represented by a data processing LSI for performing data compression and the like. In this type of large-scale semiconductor integrated circuit, in order to reduce the wiring area, a two-layer aluminum wiring technique is applied to integrate clock lines that supply clock signals to these flip-flops. However, on the other hand, a malfunction of a circuit called a clock skew caused by a time lag between clocks has become a problem.

The malfunction of the circuit due to the clock skew will be specifically described below with reference to FIGS. 7 to 9. Now, in the circuit shown in FIG. 7, DFF1 and DFF2
There should be no deviation of the clock CLK supplied to the. However, when the circuit shown in the figure is formed into an LSI, as shown in FIG. 8, there is a parasitic resistance R and a parasitic capacitance C of the wiring, which causes a time lag between the clocks CLK1 and CLK2. This time shift is called clock skew.

Next, the problem of malfunction due to clock skew will be described with reference to the timing chart shown in FIG. (1) When there is no clock skew (normal operation) The change of the input (IN1) of DFF1 is output O at time t1.
1 change. The change of O1 is D at time t2.
It is taken in by FF2 and output as output O2 of DFF2 at time t3. (2) When there is a clock skew (malfunction) When the output O1 of the DFF1 reaches the input IN2 of the DFF2 earlier than the time t1 '(it should be taken into the DFF2 at the time t2, originally), It is taken into the DFF2 during the clock skew (t1 to t1 ') and is output as the output O2 at the time t1'. In other words, the signal is missing. This is a malfunction due to clock skew. The above malfunction does not occur if the value of the clock skew is small or the time for transmitting the signal of the DFF1 from O1 to IN2 is larger than the clock skew value.

Conventionally, as a method of checking the above clock skew after pattern layout, there is the following method relating to timing verification. Back Annotation Method This method is a method of calculating the wiring capacitance for each node, returning it to the logic simulator, and executing the logic simulation. However, since cells connected to the same node are treated as signals that arrive at the same time, there is a drawback in that it is impossible to identify a propagation delay time difference such as a clock skew that occurs on the same node. Method of Extracting Required Circuit This method is a method of extracting a necessary circuit from a layout pattern and executing a circuit simulation. However, the great effort to extract the necessary circuits,
There is a drawback that the condition setting of the circuit simulation (input pulse, initial potential setting of each node, etc.) becomes complicated. Furthermore, such a circuit simulation has a long execution time of several hours, and sometimes a solution cannot be obtained due to divergence. Switch Level Simulation Method This method is a method of extracting from the layout pattern at the transistor level and executing a switch level simulation. This method can calculate at high speed because the transistor is replaced with a simple switch, but the condition setting (input pulse, condition of initial potential of each node, etc.) is complicated and the calculation accuracy is higher than that of circuit simulation. It had the drawback of being bad.

[0006]

Most of the causes of the timing malfunction of the present large-scale integrated circuits are due to the clock skew. Therefore, it is only necessary to be able to determine the malfunction due to the clock skew after the pattern layout. However, as described above, when the conventional method is used, there are inconveniences such as an extremely long simulation execution time and complicated condition setting. The present invention was created in view of the problems of the conventional method, and an object thereof is to provide a method for quickly and accurately determining a malfunction of a semiconductor integrated circuit.

[0007]

According to the present invention, there is provided a pattern layout in a method of determining malfunction of a semiconductor integrated circuit including a clock line, a clock driver for driving the clock line, and a plurality of flip-flops connected to the clock line. An equivalent circuit composed of the clock line and the clock driver is constructed based on the information, a clock skew value is obtained by executing a circuit simulation based on the equivalent circuit, and the most malfunction occurs based on the clock skew value and the circuit connection information. It is characterized in that whether or not the flip-flop malfunctions is determined by searching for a flip-flop with an easy condition, connecting the flip-flop to the equivalent circuit, and then executing circuit simulation again.

[0008]

According to the above-mentioned means, the clock skew value is obtained by a relatively simple equivalent circuit composed of the clock line and the clock driver, and the two flip-flops under the most severe conditions found by using the result are set as above. Since the method of arranging in an equivalent circuit and executing the circuit simulation again is adopted, the entire processing time is as short as about 10 minutes (conventionally required several hours) compared to the conventional method, and the calculation accuracy is also high. Is also excellent.

[0009]

EXAMPLE An example of the present invention will be described in detail below. FIG. 1 is a flow chart showing the flow of processing of an embodiment of the present invention. Reference numeral 1 in the drawing is pattern layout information 1, which has pattern layout information of a semiconductor integrated circuit including a clock line, a clock driver for driving the clock line, and a plurality of flip-flops connected to the clock line.

Clock line layout information is extracted from the pattern layout information 1 (2 in the figure). Then, based on the layout information, an equivalent circuit including a clock line and a clock driver is constructed.
In this equivalent circuit, the clock line is replaced with a CR circuit, and the input capacitance of the flip-flop is added. Next, the circuit simulation is executed based on the process parameter information 6 input to the circuit simulator (4 in the figure), and the clock skew value at the clock terminal of each flip-flop is obtained (5 in the figure). This circuit simulation can be executed at high speed because it only solves the CR network.

On the other hand, reference numeral 6 in the figure is circuit connection information having mutual connection information of each flip-flop and connection information of the flip-flop and the clock line. Based on the circuit connection information 6, the flip-flops connected to the clock line are ordered in the order in which the signals propagate (7 in the figure). Then, of the two flip-flops (two flip-flops connected in series) that are in a relationship of directly propagating a signal, the one having the condition in which the malfunction is most likely to occur is searched (8 in the figure). This search is determined by the clock skew value between the two flip-flops and the delay time (CR time constant) between the Q output and the D input. That is, the larger the clock skew value, the more Q output and D
It is determined that the shorter the delay time between inputs, the easier the malfunction occurs. It should be noted that flip-flops that are not directly related to signal propagation are ignored because they are not related to malfunction. Next, the two flip-flops thus searched are connected to the above equivalent circuit, and a circuit simulation is executed (9 in the figure). This circuit simulation is performed at high speed because it solves only the CR network with two flip-flops added.

Then, the result of the circuit simulation is judged (10 in the figure). That is, if the flip-flops operate normally, all other flip-flops can be considered to operate normally, and the process ends (1 in the figure).
1). When the flip-flop malfunctions, the pattern layout is changed (clock driver size, clock line width, etc.) (12 in the figure). Then, returning to the circuit simulation 4 in the figure, the processes shown in 4 to 10 in the figure are repeated until the circuit operates normally.

As described above, according to the present invention, the clock skew value is first obtained at a high speed by an equivalent circuit composed of the clock line replaced by the CR circuit and the clock driver, and the most severe condition found by using the result. Of 2
Since a method of arranging two flip-flops in the equivalent circuit and re-executing the circuit simulation is adopted, the entire processing time is as short as about 10 minutes as compared with the conventional method (it took several hours in the past). ), And the calculation accuracy is also excellent.

A specific example of each of the above processes will be described below. (1) Extraction example of pattern layout information (2 in FIG. 1)
Here, the layout information of the clock line as shown in FIG. 2 is extracted from the pattern layout information 1. The clock line is composed of a trunk line 21 and a plurality of branch lines 22 branched from the trunk line 21, a driving clock driver 23 is connected to one end of the trunk line 21, and a plurality of flip-flops 24 are connected to each branch line 22. ing. Here, the width of the trunk line 21 is made larger than the width of the branch line 22 in order to reduce the propagation delay of the clock.

(2) Configuration Example of Equivalent Circuit of Clock Line Based on the layout information of the clock line shown in FIG. 2, the trunk line 21 and the branch line 22 are replaced with the CR circuit (25), and the clock terminal of the flip-flop 24 is replaced. An equivalent circuit as shown in FIG. 3 is configured by adding an input capacitance. The CR circuit (25) is composed of a 3π type CR circuit (three stages of π type CR circuits connected in series) in consideration of calculation accuracy.

(3) Ordering of flip-flops (see FIG. 1)
7), based on the circuit connection information 6, as shown in FIG. 4, the flip-flops connected to the clock lines are ordered in the order in which the signals propagate. (4) Searching for two flip-flops (FF) that are most likely to malfunction (8 in FIG. 1) Clock skew value between two flip-flops and delay time between Q output and D input (CR time constant) ) And judge from. It is assumed that there is no CR time constant number between the Q output and the D input, but if there is an inverter (INV) between the Q output and the D input as shown in FIG.
Consider the delay time due to this. (4) Configuration of Equivalent Circuit Connecting Two FFs The two flip-flops (FF1, FF2) found by the above search are connected to the equivalent circuit shown in FIG.
An equivalent circuit as shown in FIG. 6 is constructed. A CR circuit based on an actual pattern is inserted between the Q output and the D input. Then, a circuit simulation is executed based on this equivalent circuit, and it is determined whether or not a malfunction occurs by looking at the Q output waveform of the flip-flop FF2.

[0017]

As described above, according to the present invention,
An equivalent circuit with a clock line is constructed from the pattern layout information, a circuit simulation is executed based on the equivalent circuit to obtain a clock skew value, and the two flip-flops under the most severe conditions found by using the result are equivalent to the above. Since the method of arranging the circuit in the circuit and executing the circuit simulation again is adopted, the conventional method required several hours for the whole processing, but according to the present invention, it is shortened to about 10 minutes. The calculation accuracy is also excellent. Accordingly, it is possible to quickly and accurately determine the malfunction of the semiconductor integrated circuit after the pattern layout is created.

[Brief description of drawings]

FIG. 1 is a flowchart showing a flow of processing according to an embodiment of the present invention.

FIG. 2 is a diagram showing layout information of clock lines according to an embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating ordering of flip-flops according to an exemplary embodiment of the present invention.

FIG. 5 is a circuit diagram of a flip-flop according to an exemplary embodiment of the present invention.

FIG. 6 is an equivalent circuit diagram in which two flip-flops according to an embodiment of the present invention are connected.

FIG. 7 is a circuit diagram for explaining a problem of clock skew.

FIG. 8 is a circuit diagram for explaining the problem of clock skew.

FIG. 9 is a timing diagram for explaining the problem of clock skew.

[Explanation of symbols]

 1 Pattern Layout Information 2 Extraction of Pattern Layout Information 3 Process Parameter Information 4 Circuit Simulation 5 Clock Skew Value 6 Circuit Connection Information 7 Flip-Flop Ordering 8 Flip-Flop Search 9 Circuit Simulation 10 Result Judgment 11 Finish 12 Change Pattern Layout Conditions 21 Main line 22 Branch line 23 Clock driver 24 Flip-flop 25 CR circuit 26 Input capacity of flip-flop CLK1, CLK2 clock DFF1, DFF2 D flip-flop

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/82

Claims (1)

[Claims] 1. A method of determining malfunction of a semiconductor integrated circuit including a clock line, a clock driver for driving the clock line, and a plurality of flip-flops connected to the clock line, wherein the clock line and the clock are based on pattern layout information. A clock skew value is obtained by configuring an equivalent circuit including a driver and performing a circuit simulation based on the equivalent circuit, and a condition that is most likely to malfunction is determined based on the clock skew value and connection information of the plurality of flip-flops. Malfunction of a semiconductor integrated circuit characterized by determining whether or not the flip-flop malfunctions by searching for the flip-flop and connecting the flip-flop to the equivalent circuit and then executing circuit simulation again. How to judge the work.