JPH07141148A - Pipeline parallel multiplier - Google Patents

Abstract

PURPOSE:To obtain sufficiently high speed without expanding the size of a circuit by combining pipeline processing and a carry save adder type parallel multiplier. CONSTITUTION:In the carry save adder type parallel multiplier reducing the propagation of carry signals in a self-stage by transmitting a carry signal on each partial product adding stage to the succeeding adder, adding stages are divided at a position where the delay time of a carry or sum critical path in the multiplier is practically equally divided and a latch register 500 for inputting and storing the intermediate calculation result of the divided first half part and using the stored output as an input to the latter half part is inserted between the divided first and latter halves.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a carry save adder type parallel multiplier using a pipeline type.

[0002]

2. Description of the Related Art Generally, as a parallel multiplication circuit, there are a ripple carry system in which the carry of each multiplication unit circuit is sequentially sent horizontally in each stage, and a carry of each multiplication unit circuit is sent to the next stage. A carry save adder method (“CMOS VLSI design”, Baifukan, P224), which speeds up the ripple carry method, is known.

FIG. 4 shows an example of a parallel multiplier of 8 × 8 bit length using the carry save adder method. The multiplication unit circuit is AND circuits (300 to 307, 310 to 31).
7, 320-327, 330-337, 340-34
7, 350-357, 360-367, 370-37
7) or AND circuit and half adder (HA) 400, 40
7, 410, 420, 430, 440, 450 or AN
D circuit and full adders (FA) 401 to 406, 411 to 4
17, 421-427, 431-437, 441-44
7, 451 to 457, and an adder 700 with a carry look-ahead circuit for adding these results. The multiplication number Y is input terminals 200 to 207 and the multiplicand X is input terminal 100 to. 107, and the multiplication result Z is output from the output terminals 600 to 615. And, for example, the carry (carry signal) of FA401 is F
As input to A411, the carry of the multiplication unit circuit is added in the subsequent stages.

On the other hand, pipeline processing has been conventionally known as a means for speeding up processor processing, and one applying pipeline processing to a parallel multiplier is, for example, one applied to a ripple carry system. Four
There is one disclosed in JP-A-205525.

Further, Japanese Patent Application Laid-Open No. 4-10028 discloses that
There is disclosed a pipeline circuit in which an arithmetic circuit for multiplication or the like is an aggregate of a plurality of combinational circuits and the combinational circuits are connected by a latch circuit.

[0006]

However, the above-mentioned conventional technique has not yet achieved a sufficient speedup. That is, since the one disclosed in Japanese Patent Laid-Open No. 4-205525 is an improvement of the ripple carry system multiplier, there is a limit to the speed improvement as compared with the carry save adder system.

Further, Japanese Patent Laid-Open No. 4-10028 discloses that
Although it is described that the pipeline processing is combined with the parallel multiplier, the specifically disclosed multiplying circuit is provided with a latch circuit for each multiplying stage, as shown in FIG. 2 of the publication, for example. Despite the large circuit scale, we couldn't expect the corresponding speedup. Further, the publication only discloses the setting of the number of stages of the latch circuit, and no arrangement has been conventionally known about the arrangement for increasing the maximum efficiency with a small number of stages.

The present invention is intended to solve such a problem, and an object thereof is to combine a carry save adder type parallel multiplier with pipeline processing, and to sufficiently speed up the circuit without enlarging the circuit scale. It is to plan.

[0009]

According to the present invention, by transmitting the carry signal of the adding stage of each partial product to the adder of the next stage,
In a carry save adder type parallel multiplier in which carry signal propagation in the self stage is reduced, the addition stage is divided at a position where the delay time of the carry or sum critical path of the multiplier is substantially divided. , Input the intermediate calculation result of the first half between the divided first half and the second half and hold it,
The pipeline parallel multiplier is characterized in that a latch register having the held output as an input of the latter half is inserted.

[0010]

In the pipeline parallel multiplier of the present invention, since the delay time in the critical path in each divided addition stage, that is, the longest path followed by carry or sum is equally divided, the parallelism in each addition stage is increased. There is little loss time in processing, and calculation is most efficient.

[0011]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an example of a carry save adder type parallel pipeline multiplier of the present invention, and is a circuit diagram of a two-stage pipeline type arithmetic bit length 8 × 8 unsigned multiplier.

As shown in the figure, the pipeline parallel multiplier of the present invention has input terminals 100 to 107 for the multiplicand X, input terminals 200 to 207 for the multiplication number Y, and an AND circuit 300 to a multiplication unit circuit. 307, 310-317, 320
~ 327, 330 to 337, 340 to 347, 350 ~
357, 360 to 367, 370 to 377, half adders (HA) 400, 407, 410, 420, 430, 4
40, 450, 460, full adder (FA) 401-40
6, 411-417, 421-427, 431-43
7, 441-447, 451-457, 461-46
7, latch register 500, multiplication result output terminal 60
0 to 615, and the multiplication unit circuit may be the same as that of the carry save adder system described above. Therefore, an important point in the present invention is the location of the latch register 500.

FIG. 3 shows an example of a general full adder. In the case of the full adder in the figure, the logic that outputs the sum is more complicated than the logic that outputs the carry, and if the delay time of each gate is almost the same, the sum requires a delay time that is twice that of the carry. . Therefore, when the delay time of carry = T and the delay time of sum = 2T and the critical path of the multiplier in FIG. 1 is traced, the multiplicand X7 is FA4.
06 → FA415 → FA424 → FA433 → FA44
The delay time up to this point is 2T × 5 = 10T because all paths are sum output paths. Also, the clinical path from here is FA451 → HA460 → FA461
→ FA462 → FA463 → FA464 → FA465 →
The path is FA466 → FA467 → output terminal 614, and the delay time is 2T + T × 7 + 2T = 11T.
It can be seen that between A422 and FA451, the delay times of the critical paths in the first half and the second half are almost equal.

Therefore, by dividing the first half and the second half so that the delay time of the critical path becomes equal, and providing the latch register 500 between them, a pipeline structure is provided, whereby parallelization of the conventional carry save adder method is performed. The critical path delay of the multiplier can be halved. Further, when the delay times of the critical paths of the respective stages are not exactly the same, the latch register 500 may be provided at the position where the delay time difference is minimized.

Further, as a characteristic of the circuit of this embodiment, the amount of hardware of the circuit in the first half is large, and the output to be passed to the latch register passes through not the data itself of the input terminals 100 to 107 and 200 to 207 but all the combination circuits. Since it is an internal signal, it is not necessary to latch the input signal, and the hardware is easy to configure.

FIG. 2 shows another example of the pipeline parallel multiplier of the present invention, which is different from the first embodiment in that HA460 and F which are the ripple carry save adder units at the final stage of FIG.
Carry look-ahead circuit (CL
The point is that the 8-bit adder 700 with A) is replaced. Generally, the critical path delay in the latter half part is shortened by replacing it with an adder having a look-ahead circuit. Since there is no great difference in the delay time from the ripple carrier part, the latch register 500 is arranged at the same position as in FIG.

In this embodiment, the latch register is provided at one place and the adding stage is divided into two, but it is also possible to divide into three stages and four stages as required. However, even in this case, the delay time of the critical path in each stage needs to be substantially the same.

[0018]

According to the pipeline parallel multiplier of the present invention, the operation speed can be greatly improved by both the carry save adder system and the pipeline system. Therefore, according to the present invention, since the delay time of the critical path is similar to that of other CPU components such as ALU, the CPU using the pipeline parallel multiplier can be driven in a high clock cycle. .

Furthermore, the pipeline parallel multiplier according to the present invention can achieve the above-mentioned speed-up without taking a complicated circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram of a pipelined parallel multiplier of the present invention.

FIG. 2 is a block diagram of a pipelined parallel multiplier of the present invention.

FIG. 3 is a logic diagram of a full adder used in the pipeline parallel multiplier of the present invention.

FIG. 4 is a block diagram of a conventional carry save adder type parallel multiplier.

[Explanation of symbols]

AND circuits 300 to 307, 310 to 317, 320
~ 327, 330 to 337, 340 to 347, 350 ~
357, 360 to 367, 370 to 377 Half adder 400, 407, 410, 420, 43
0, 440, 450, 460 full adders 401 to 406, 411 to 417, 421
~ 427, 431-437, 441-447, 451-
457, 461-467 500 Latch register 700 Carry look-ahead circuit (CLA) adder

Claims (1)

[Claims] 1. A carry-save adder type parallel multiplier in which carry signals in the adder stage of each partial product are transmitted to the adder in the next stage, thereby reducing carry signal propagation in the adder stage. The addition stage at a position where the delay time of the critical path of the carry or thumb is divided substantially equally, and the intermediate calculation result of the first half is input and held between the divided first half and second half. Then, a pipeline parallel multiplier is characterized in that a latch register having the held output as an input of the latter half is inserted.