JPH0713956A - Simd type parallel computer data transfer device - Google Patents

Abstract

PURPOSE:To provide a data transfer device whereby adjacent communication is executed at a higher speed in an SIMD type parallel computer at the time when an inter-board latency exists. CONSTITUTION:Respective element processors are provided with a data holding register with the depth of the same number as latency increase by an inter-board data transfer part, a BRD flag indicating whether or not data held by the respective data holding registers is BRD and a data selecting F/F holding information indicating whether or not BRD reaches the most end of the data holding registers. Moreover, a selector selecting data from the data holding register by the value of the data selecting F/F, a counter capable of counting the number obtained by adding the number of the element processor where data in the board passes through and the number of an inter-board register stage and a communication register, are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication circuit between element processors of a parallel computer.

[0002]

2. Description of the Related Art Since SIMD type parallel machines operate synchronously, data can be easily transferred all at once in the same direction. For example, a process such as shift-transferring a ring-shaped adjacent coupling path to transfer data to several PEs ahead is often performed.

FIG. 3 shows a diagram of a one-dimensional adjacent joint of the element processor. Adjacent communication is transferred by the following operations.
First, in each element processor, data is set in the transfer register. The transfer register is connected to the transfer register of the adjacent element processor in the form of a pipeline register. Next, the data is transferred to the transfer register of the adjacent element processor by the transfer instruction. Since it is SIMD, this data transfer is performed simultaneously in each transfer register. When data is sent to the adjacent element processor, the transfer instruction is repeated once, and when it is sent to the distant element processor, the transfer instruction is repeated a plurality of times. After that, each element processor fetches data from the transfer register. By these operations, data can be transferred to one or more element processors ahead.

Further, in these SIMD type parallel computers, all the element processors must be treated equivalently, so that the connection between the element processors inside the board and the element joining across the boards have the same processor joint part. I'm using one.

[0005]

Normally, in a parallel computer, the operating frequency of the processor is low, so the operating frequency in adjacent communication does not take much time. That is, the hardware speed of adjacent communication is sufficiently high with respect to the operating frequency of the processor. However, in recent years, the operating frequency of the processor has been improved, and various problems arise in the SIMD type parallel computer. As one of the above,
This is a simultaneous shift transfer between PEs. Within the same board, it seems possible to transfer at 200-300 MHz even with the current technological capabilities. However, when the scale of parallelism becomes large and the system is composed of multiple boards, the adjacent communication between the boards is
The load is much heavier than the adjacent communication on the same board, and the imbalance with the transfer speed inside the board comes out.

Therefore, in the adjacent communication part between the boards,
It is conceivable to insert a register and perform transfer by a high-speed buffer such as ECL to reduce the difference in transfer speed. in this case,
Since the register is inserted, the latency of 1 or 2 is added to the latency of the adjacent communication in the board. In this case, when the shift transfer is normally performed, the meaningless value (hereinafter referred to as BRD) initially stored in the register between the boards is inserted between them. In addition, the location where high-speed data transfer within the adjacent communication is possible matches the rate of inter-board transfer, and when there is nothing in between, one stage or two stages are reached for each separation between boards. A delay occurs, and particularly in long-distance data transfer by continuous shift operation, the transfer time becomes double or triple.

Therefore, the present invention has been made in view of such circumstances, and an object of the present invention is to reduce the rate of adjacent communication operation even if the data transfer portion between boards is low speed. The object is to realize a data transfer device capable of transferring data.

[0008]

In order to solve the above problems, according to the present invention, each element processor has a pipeline-like register (hereinafter referred to as a pipeline-like register) having the same depth as the increase in latency due to a data transfer portion between boards. Data holding register), a BRD flag indicating whether or not the data held in each data holding register is BRD, and an F / F that holds information indicating whether or not the BRD has reached the end of the data holding register. F (hereinafter referred to as “data selection F / F”), a selector for selecting data from the data holding register according to the value of the data selection F / F, and the number of element processors through which the data on the board passes and the register between the boards It is composed of a counter capable of counting the total number of stages and a communication register.

Furthermore, when the time required for communication between the element processors in the boards is p and the time required for transfer between the boards is t at the joint between the boards, the output register on the sender side and the receiver side The input register set is t / p set,
In the sending procedure, a clock generation circuit that generates clocks that are shifted by t / p p times in a cycle t, and a data selection circuit that selects the data to be taken out from the input register by receiving the output of the clock generation circuit on the receiving side Composed of.

Further, when the number of element processors on one board is a, the transfer latency between boards is b, and the data transfer destination is n adjacent element processors, n transfer instructions are issued.
It is operated by a compiler that ejects + b × (1 + n mod a) adjacent communication instructions.

Further, the inter-board transfer register, the communication register, and the data holding means include means for identifying whether or not the data is in the inter-board transfer register at the start of the transfer process, and the board by the identifying means. Whether the data in the inter-transfer register has reached the end of the data holding means, and whether the data in the communication register or the data in the last stage of the data holding means is recognized by the status holding means that holds the arrival. Has a selection means for selecting.

Also, a state setting instruction having a function of setting the identifying means of each inter-board transfer register and resetting a part of the identifying means of the communication register and the data holding means and the state holding means is output from the compiler. In the case where n> a, the transfer process is normally performed by replacing a part of the transfer instruction sequence with the state setting instruction when the state setting instruction also serves as a transfer instruction. The data selection means is software controlled by a controllable instruction sequence.

Further, the counting means capable of counting the total number of the element processors through which the data on the board passes and the number of register stages between the boards is counted by the counting means when the counting means returns to zero or to a set value. In the case of n> a, the control section controls the data selection means by hardware by resetting the state holding means and a part of the identification means of the data holding means.

Further, in the element used for the in-board data transfer and the element used for the inter-board data transfer,
Separate elements are used so that the driving force is such that the communication element inside the board <the communication element between the boards.

[0015]

According to the present invention, the transmitted data is held in the data holding register which is a pipeline register having the same number of depths as the latency between the boards, and the final bit is selected by the F / F value for 1-bit data selection. Data sent to
Select the value of the transfer register or the value of the last stage of the data holding register. The operation of the data selection F / F is to set the data selection F / F when the BRD flag is checked and the data in the final stage of the data holding register is BRD. In addition, a counter that can count only the number of PEs on the transfer path on one board + the transfer latency between the boards is provided to count up each time adjacent communication is executed. PE hung on the transfer path
After counting up the transfer latency between the number of units and the transfer latency between boards, the counter confidence and the data selection F / F, and the BRD flag of the communication register and the data holding register are reset. The data selection F / F and each BRD flag may be reset when the counter reaches a certain set value. Alternatively, instead of using the counter, a reset command may be used to perform a timely reset under software control. The reset instruction also serves as a transfer instruction, so that the transfer performance equivalent to that of hardware control using a counter can be achieved. After the completion of the series of transfer instructions, the data is selected according to the contents of the F / F, either the data at the final stage of the data holding register or the data in the transfer register, and the data is fetched into the PE.

In the inter-board data transfer, low-frequency clocks with different rise times from the clock generation circuit are connected to the output registers, and the registers are sequentially sent every p hours of the PE operation clock. The incoming data is latched and held for the time n until the data reaches the receiving side register. The output of the clock generation circuit is also sent to the input data selection circuit on the receiving side. Seeing the signal, the input data selection circuit selects the data to be transferred to the communication register of the receiving side board from the input register.
That is, a high throughput is realized by using a plurality of sets of input / output registers having a low operating frequency while shifting the phases.

[0017]

EXAMPLE An example of the present invention will be described below.

First, the internal structure of the element processor (hereinafter referred to as PE) will be described. For data transfer between boards,
Although there is latency, it is assumed that the throughput is equivalent to the throughput of adjacent communication on the same board. In this embodiment, the communication mechanism between the boards has one transfer register on the sender board side and one transfer register on the receiver side, and the data transfer between the registers is the same as that of the adjacent communication on the same board. Transfer shall be possible. For example, high-speed transfer is performed between element processors by using a small-amplitude buffer such as GTL, but it is difficult to drive the wiring between boards by GTL, so an ECL buffer is used between boards. At that time, the operation of the circuit between the boards transfers data from the communication register of the sender side PE to the communication register of the sender side board at a certain clock. At the next clock, data is transferred from the communication register of the sender board to the communication register of the receiver board. At the next clock, data is transferred from the communication register of the receiving side board to the communication register of the receiving side PE. In this case, the latency of data transfer between boards is 2. However, since the data transfer between the boards is a pipeline operation, the throughput is the same as the PE communication in the same board.

In this embodiment, it is assumed that 32 PEs are one-dimensionally connected in a ring shape. It is assumed that there are 4 boards, and that 8 PEs are mounted on each board. At this time, as a register for communication, a total of 40 registers including a communication register of each PE and a transfer register between boards are combined in a ring shape (FIG. 4).

For example, when it is not necessary to consider the latency between boards, and when data is to be transferred to the PEs on the right of four,
When data is set in the communication register in each PE and a rightward transfer instruction is performed four times, normally all PEs are sent to the next four as shown in FIG. 5, but there is latency in the transfer between boards. In this case, as shown in FIG. 6, although the data of PE0 to PE3 have reached the communication registers of PE4 to PE7 respectively,
The meaningless data (BRD) stored in the transfer register between boards has arrived at the communication registers E2 and E3. Also, PEs are set in the communication registers of PEs 0 and 1, respectively.
The data of 30 and 31 have arrived, and this data is the data from the PR on the left of the two.

If the number of PEs connected to the communication path on the board is a, the latency between the boards is b, and the number of transfers in a normal case is n, then n + b × (1 + n mod a) times, then all the transfers are performed. Data required for PE can be transferred. In this embodiment, a = 8 and b = 2. In the above example, n =
In case of 4, latency between boards is 2 + 4 + 2 ×
If (1 + 4 mod 8) = 6 and six transfer instructions are issued, four data will reach all PEs. If n = 12, it will arrive with 16 transfer commands.

However, in the case of n = 4, if the transfer instruction is simply executed 6 times, PE0 is executed when the instruction is completed.
Although the communication registers of ~ 3 contain four pieces of correct data next to each other, the communication registers of PE4, 5 contain BRD, and the transfer registers of PE6, 7 contain PE respectively.
Contains 0 and 1 data. This is the value of PE on the left of 6 and is not the data that PEs 6 and 7 should originally receive (FIG. 7).

Therefore, in this patent, a plurality of stages of data holding registers are installed in each PE, the data that has entered the transfer register several clocks before is held, and the transfer instruction ends,
We propose a circuit that performs normal data transfer processing by selecting the data to be read from the transfer register and the data holding register when reading a value from the constant transfer register.

The structure of the transfer unit inside the PE of this embodiment will be described. FIG. 1 shows a block diagram of a transfer unit inside the PE of this embodiment. In the PE, in addition to the communication register, two data holding registers (data holding registers 0, 0,
1) is provided. The data holding register is as shown in FIG.
It is connected in a pipeline to shift data from the communication register. In addition to the holding register, a BRD flag indicating whether the held data is BRD, a selector for selecting the data to be taken out, a 1-bit flip-flop (a data selection F / F for holding a value serving as a selection signal of the selector). ) Consists of. Further, if necessary, a counter for resetting the same selection F / F and BRD flag is provided. The counter is capable of counting only the number of PEs on the board + latency between the boards. In this embodiment, the counter returns to 0 after counting up to 9.

First, consider the case of n <a. This is the case when any PE passes the BRD set only once at most. A set of BRD is a BR of registers between one board.
In the present embodiment, one set of BRDs consists of two consecutive BRDs. FIG. 8 shows the contents of each register at the time when six transfer instructions have been completed. As you can see from the figure, P
E0 to PE3 read the value of the communication register, and PE4 to PE4
7 may read the value of the data holding register 1. This also applies to other boards. Of the 8 PEs in the board, the 4 PEs with the smallest numbers read the data from the communication register, and the 4 PEs with the large numbers read the data from the holding register 1.

For example, when the number of transfers is one, that is, n
= 5 and the number of transfer instructions is 7, the state of FIG. 8 is shifted to the right by 1 as shown in FIG.
In this case, PE0-4 read the value from the communication register, and PE5-7 read the data from the data holding register 1.

Here, regarding the selection signal to be input to the selector, when looking at FIGS. 8 and 9, BRD is the data holding register 1.
Before reaching, the data holding register 1 is selected and BRD
After the data reaches the data holding register 1, the transfer register should be selected. Therefore, the selection signal mechanism is 1
F / F of bit (F / F for data selection) is enough.
The timing of setting the value of / F may be set at the same time when BRD is latched in the holding register 1. To do this, a flag indicating whether the data is BRD (hereinafter referred to as BRD flag) is attached to the data and held in each transfer register and data holding register. Each PE
When the data is set in the communication register, the BRD flag is reset and the BRD flag in the inter-board transfer register is set. The F / F for data selection is set by looking at the BRD flag of the holding register 1 when the set is asynchronous, and by looking at the BRD flag of the holding register 0 when the set is synchronous.

When performing a new transfer process, the data selection F / F is performed at the same time when the data is set in the communication register.
To reset. Although the holding registers 0 and 1 may be any data, it is not good when the BRD flag is set. Therefore, BR is set at the same time as the data is set in the communication register.
Reset the D flag. At the same time, the BRD flag of the transfer register between boards is set.

With these mechanisms, normal operation is achieved when n <a.

Next, consider the case of n ≧ a.

When n = 7, at the time when the transfer instruction is completed, that is, when the transfer instruction is performed 9 times, all PEs should have selected the register to be read as the communication register. When n is increased by 1, the number of transfers is increased by 3. FIG. 10 shows the state of the register of each PE when the transfer instruction is completed when n = 8, that is, when the transfer instruction is performed 12 times. As can be seen from FIG. 10, PE0 must select the communication register and PE1 to PE7 must select the holding register 1. Therefore, it is necessary to reset the data selection F / F somewhere. Further, when the transfer is further performed after the transfer command of 9 times is completed, it is the same as the initial state when the transfer command of 9 times is completed, that is, the state where the data is set in the transfer register. Therefore, if the transfer instruction is further executed when the transfer instruction is completed nine times, it is necessary to reset both the BRD and the flag of the holding register of each PE.

As a method for performing the above set & reset,
It is conceivable to provide a new command. For example, an instruction to set the BRD flag and reset the F / F for data selection is provided, or an instruction to simultaneously perform the same processing + transfer is provided. The compiler inserts a set / reset instruction after executing the transfer instruction 9 times, or replaces the 10th transfer instruction with a set / reset + transfer instruction, and thereby the BRD flag and the F / F for data selection are selected.
Reset. According to this method, even if the number of PEs mounted on one board is changed, it is possible to easily deal with it.

The timing for resetting is P on the board.
When the number of E is a and the latency between boards is b, a + b
It is time to execute a transfer instruction that is an integer multiple of. However, the number of adjacent transfer instructions executed in a series of transfer processing is (a + b) × i + b ≦ number of transfer instructions <(a + b) × (i
+1) i: It becomes an integer. In the above example, the transfer instruction is performed 9 times if it is next to 7PE, and 12 times if it is next to 8PE. That is,
No data is read at the time when the 10th and 11th transfers are completed. Therefore, the data selection F / F is reset from (a + b) × i to (a + b) × i + b.
It may be reset when any of the first transfer instructions is executed. However, it is necessary to pay attention to which BRD flag is reset when deciding which instruction is used for resetting.

From (a + b) × i, (a + b) × i + b
Considering the BRD in the BRD holding register in the data holding register of each −1st PE, at the time of (a + b) × i th, the valid BRD is only in the communication register of PE0, and the BRD in the data holding register is All must be invalid. At the time of (a + b) × i + 1th, a valid BRD appears in the first stage of the data holding register of PE0.
Therefore, if the (a + b) × i + 1th set / reset processing is performed, it is necessary to set the BRD flag of the second and subsequent stages of the data holding register. (A + b)
In the case of xi + 2, the third and subsequent stages of the data holding register are set. At (a + b) × i + b−2nd, it is sufficient to set only the BRD flag at the final stage of the data holding register, and at (a + b) × i + b−1th, it is not necessary to reset the BRD flag.

If it is not desired to increase the number of instructions just for the reset processing, it is considered that the number of transfer instructions is counted by hardware and the set / reset operation is automatically performed. Therefore, a counter is provided in each PE in order to perform the set / reset processing by hardware.

A specific configuration in this embodiment will be shown. In this embodiment, since the PE on one board is 8 and the latency between the boards is 2, it suffices to have a counter capable of counting up to 9. After counting up to 9, it returns to 0. Since the transfer instruction when returning to 0 is an integral multiple of 10, the data selection F / F and the BRD flag of the data holding register may be reset at this time.

As a specific example, the BRD exists in the data holding register 1 of the PR6 and the data holding registers 0 and 1 of the PE7 when the ninth transfer instruction is completed. During the tenth transfer instruction processing, the data selection F / F may be reset and the BRD flag of the data holding register of the PE 7 may be set at the same time. To reset the data selection flag during the 11th transfer instruction processing, reset B
It is efficient because there is no RD flag.

By using the above circuit, it becomes possible to transfer n> a.

In the above embodiment, the rightward transfer direction is taken as an example, but the reverse transfer can also be processed by the same circuit.

Consider the flexibility of the circuit described in the above embodiment. Specifically, it corresponds to the change in the number of PEs in one board and the change in transfer latency between boards.

First, the change in the number of PEs in one board will be considered. When the number of PEs changes, it is necessary to change the number of counters and the data selection F /
This is the reset timing of F. This is where it is necessary to deal with the case where the transfer latency between boards changes.

In order to be able to freely change the count number of the counter and the reset timing of the data selection F / F, the following configuration is used. With a counter with reset that can count to a number with some margin,
A count number holding register that holds the maximum value of the count number, a counter reset circuit that generates a reset signal to the counter from the value of the count number holding register and the value of the counter, and the timing to reset the data selection F / F It is composed of a register for holding and a data selection F / F reset signal generation circuit for generating a reset signal to the data selection F / F from the value of the register and the counter. Figure 11
The block diagram is shown in. If the above two registers are treated as one of the status registers of the processor, extra instructions will not be added.

When the reset timing is controlled by software, the counter and counter control circuit are not necessary.

Next, consideration will be given to dealing with changes in the data transfer latency between boards. For the counter and the reset timing of the data selection F / F, refer to P on the above 1 board.
It can be dealt with with the same configuration as the response to the change in the E number. Another problem is the number of stages of the data holding register.
The number of stages of the data holding register is equal to the number of inter-board data transfer latencies. Therefore, if the latency changes, the number of stages must change accordingly.

Therefore, in order to cope with the above-mentioned change in latency, a data holding register having the same number of stages as the expected maximum latency, a latency holding register holding a latency value, and a value of the latency holding register are used. , A holding data selector that selects one data from each output of the data holding register, and the data selected by the data selection F / F is either the data selected by the holding data selector or the data in the transfer register. Or configure to select. FIG. 12 shows a block diagram.

According to the value stored in the latency number holding register, one data and BRD flag are selected from a plurality of data holding registers. The selected data holding register is the lowermost register in that latency, the value of the register is used as selection data with the data of the transfer register, and the BRD flag is sent to the data selection F / F as a set signal.

When performing control by software, from the above example,
You can omit the counter. FIG. 14 shows a control software generation flow chart for performing control by software.

Next, an embodiment of the data transfer mechanism between boards will be described. FIG. 2 shows an embodiment of the present invention. In the embodiment of the transfer circuit inside the PE, the data transfer rate between the boards is the same as the transfer rate between the PEs on the board. Therefore, in FIG. 2, the sender side is composed of only one set of the output register 0 and the receiver side input register 0.
In the present embodiment, consider a case where the data transfer rate between boards takes three times the transfer rate of PEs on the board. The transfer rate between PEs on the board is 5 ns, and the transfer rate between boards is 15 ns
Suppose this.

Output registers 0, 1, 2 are provided on the sender side board.
3 registers are provided, and the register that stores the data coming from PE on the sender side is
It is selected by the output register selection circuit every ns and data is set. Input registers 0, 1, and 2 are connected to the output registers on the receiving side board in a one-to-one correspondence, and transfer between the registers is performed in 15 ns of 66.67 MHz operation. In the clock generation circuit, the phase shift is 3
A type of 66.67 MHz clock is generated and provided to each output register. Further, the same three clocks are sent to the receiving side board together with the data signal corresponding to each output register, and given to the input register. Also, the same 3
The clock signal enters the input data selection circuit of the receiving side board and selects from which input register the data is read out from the three-phase clock. FIG. 13 shows three outputs from the clock generation circuit and contents of three output registers,
The output from the selector on the receiving board is shown.

As described above, the throughput can be increased even when the transfer between the boards takes time.

[0051]

As described above, according to the present invention, if the number of PEs on the communication path on the board is a, the latency between the boards is b, and the transfer number in the normal case is n, then n +
All PEs can be transferred by b × (1 + n mod a) times.
The data required for can be transferred with the same throughput as when a system is constructed with one board.

[Brief description of drawings]

FIG. 1 is a block diagram of a communication unit in a PE in the case of inter-board latency 2.

FIG. 2 is an inter-board data transfer unit when the inter-board transfer time is 3 times slower than the PE dynamic clock.

FIG. 3 shows an example of one-dimensional joining of PEs.

FIG. 4 is a one-dimensional ring combination of four boards 32PE.

FIG. 5 shows an example in which data is sent to the right next to 4PE in a one-dimensional ring-coupling ideal model of 32PE.

FIG. 6 is an example in which data is sent to the right side of 4PE with two latencies between 32PE one-dimensional ring-bonded boards.

FIG. 7 shows an example in which data is sent to the right side of 6PE with two latencies between 1D ring-bonded boards of 32PE.

FIG. 8 is a state diagram of registers when 6PE is transferred to the right in the model of FIG.

FIG. 9 is a state diagram of registers when data is transferred to the 7PE right side in the model of FIG.

FIG. 10 is a state diagram of registers when data is transferred to the right by 12PE in the model of FIG.

FIG. 11 PE with flexible inter-board latency
The block diagram of the counter part of an internal communication part.

FIG. 12 is a block diagram of an intra-PE communication unit that has flexibility with a maximum inter-board latency of 3.

13 is an output timing chart from the clock generation circuit in FIG.

FIG. 14 is a control software generation flow chart for performing control by software.

Claims (2)

[Claims] 1. A latency of 0 in a communication path that crosses between boards.
In a data transfer device equipped with an inter-board transfer register for performing inter-board communication that is not installed in the adjacent communication path of a parallel computer, each element processor has a communication function for performing the adjacent communication. After the register and the data held by the communication register, a pipeline register-like data holding means having a depth equivalent to the latency required for data transfer between boards, and finally after a plurality of data transfer instructions A SIMD type parallel computer data transfer device comprising a communication register and a selecting means for selecting data to be received from a data holding means. Further, when the number of element processors on one board is a, the transfer latency between the boards is b, and the data transfer destination is n adjacent element processors, the transfer instruction is n +
It is operated by a compiler that ejects b × (1 + n mod a) adjacent communication instructions. Further, each inter-board transfer register, communication register, and data holding means, means for identifying whether or not the data is in the inter-board transfer register at the start of transfer processing, and the inter-board transfer register by the identifying means. Whether the data of the communication register reaches the end of the data holding means, and the state holding means for holding the arrival of the data selects the data of the communication register or the last data of the data holding means. Has a means of choice. Further, a state setting instruction having a function of setting the identifying means of each inter-board transfer register and resetting a part of the identifying means of the communication register and the data holding means and the state holding means is a transfer instruction by the output of the compiler. When inserting into a column or when the state setting instruction also serves as a transfer instruction, by replacing a part of the transfer instruction sequence with the state setting instruction, the transfer process can be normally controlled even when n> a. The instruction sequence controls the data selecting means by software. Also, when the counting means that can count the total number of element processors through which the data on the board passes and the number of register stages between boards, when the counting means returns to zero or reaches a set value In addition, by resetting the state holding means and a part of the identification means of the data holding means, even if n> a, a control unit for controlling the data selecting means by hardware is provided. 2. A latency of 0 in a communication path that crosses boards.
In the data transfer device provided in the adjacent communication path of the parallel computer having the inter-board transfer register for performing inter-board communication, the time required for communication between the element processors in the board is p. ,
When the transfer time between boards is t, the set of output register on the sender side and input register on the receiver side is t /
p sets, a generator for generating t / p clocks with a time difference of t / p in the cycle t on the sender side, and a receiver for selecting data to be taken out from the input register upon receiving the output of the clock generator. SIMD characterized in that the throughput is p in the transfer between t boards of the transfer rate by operating the input / output register t / p set of the operation time by shifting the input / output register t / p set by p hours.
Parallel computer data transfer device. Furthermore, separate elements are used for the elements used for the in-board data transfer and the elements used for the inter-board data transfer such that the driving force is such that the communication element inside the board <the communication element between the boards.