JPH0713870A - Data analyzing device - Google Patents

Abstract

PURPOSE:To provide a data analyzing device which can detect the operation state of a digital circuit at a high speed without increasing a digital arithmetic throughput. CONSTITUTION:A CPU 2 outputs an access signal S2a to a cache memory 4 and a memory controller 8 digitally counts the frequency of access to a page present in the cache memory 4 of the CPU 2 on the basis of the page that the access signal S2a indicates. A digital count signal S8a is converted by a D/A converting circuit 10 into an analog signal S10, and an analog analyzing circuit 14 detects the page having the highest access frequency on an analog basis and determines this detected page as a page to be saved in an external memory 6 from the cache memory 4. Then the memory controller 8 saves the determined page in the external memory 6 from the cache memory 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data analysis device which speeds up and simplifies data analysis in a digital circuit.

[0002]

2. Description of the Related Art In a digital circuit, for example, arithmetic processing is performed using predetermined digital data that dynamically changes during operation of the digital circuit, and the digital circuit operates according to the operating state of the digital circuit detected based on the processing result. Processing may be performed. For example, in a computer, when performing storage management by the paging method, the CP of each page
The number of times of access from U is counted, the magnitude relation of the count result is determined, and the page saved from the cache memory to the external memory may be determined based on the determined magnitude relation. In such an electronic computer, in the CPU or the memory controller,
Based on the count result, digital type arithmetic processing is performed, and the magnitude relation of the number of accesses from the CPU of each page is determined.

Further, a plurality of processors are connected to a shared memory through corresponding cache memories,
Even in a multiprocessor system in which a predetermined process is distributed to and executed by these multiple processors, the history of data stored in the cache memory corresponding to each processor is determined when determining the process to be distributed to each processor. Predetermined arithmetic processing is performed using the indicated digital data.

[0004]

However, as described above, when performing digital-type arithmetic processing for analyzing the operating state of a digital circuit, if the information amount of digital data to be arithmetically processed increases, Problems such as an increase in analysis time and an increase in memory capacity for storing digital data occur as the amount increases. There is also a problem that an expensive CPU is occupied for a long time for analyzing the operating state of a digital circuit.

In view of the above-mentioned problems of the prior art, the present invention provides a data analysis apparatus capable of solving problems such as a long calculation time and an increase in stored data that occur when analyzing the operating state of a digital circuit. The purpose is to do. Another object of the present invention is to reduce the load on the CPU associated with the processing for solving the operating state of the digital circuit.

[0006]

In order to solve the above-mentioned problems of the prior art and achieve the above-mentioned object, the data analysis apparatus of the present invention indicates a plurality of types of operations to indicate the occurrence or termination of each operation. A digital circuit that outputs a pulse-shaped signal, and a signal creating unit that performs a predetermined calculation according to the pulse-shaped signal output from the digital circuit and creates an analog signal according to the output of the pulse-shaped signal And processing the analog signal created by the signal creating means,
And an analysis unit that analyzes the operating state of the digital circuit based on the occurrence frequency of the plurality of operations. Using the data analysis device of the present invention, determining the page to be saved from the main memory to the external memory in the electronic computer that performs paging storage management, or
By determining the processing distribution in the multiprocessor system in which the predetermined processing is distributed to a plurality of arithmetic means, it is possible to shorten the above determination time and efficiently use the storage area of the storage means.

[0007]

In the data analyzing apparatus of the present invention, a pulse-like signal is output to the signal generating means when, for example, a predetermined operation occurs in the operation of the digital circuit. The pulse-shaped signal output from the digital circuit is subjected to a predetermined calculation and converted by the signal creating means to become an analog signal. The analog signal created by the signal creating means is subjected to signal processing by the analyzing means, and based on the frequency of occurrence of a predetermined operation in the digital circuit indicated by the analog signal,
The operating state of the digital circuit is analyzed.

[0008]

EXAMPLE A first example will be described. In this example,
In a digital circuit in which a CPU is connected to an external memory via a cache memory and paging method storage management is performed, digital data indicating the number of accesses from the CPU to each page is converted into an analog amount and converted. A case where a page to be saved in the external memory is determined based on the analog amount will be exemplified. FIG. 1 is a block diagram of a digital circuit and a data analysis device of this embodiment. As shown in FIG. 1, the digital circuit of this embodiment is
It comprises a CPU 2 as an arithmetic means, a cache memory 4 as a first storage means, an external memory 6 as a second storage means, and a memory controller 8. In addition, the data analysis device 1 of the present embodiment uses D as a signal creating means.
The A / A conversion circuit 10, the filter circuit 12, the analog analysis circuit 14, and the page number detection circuit 16 are included. In this embodiment, the analog analysis circuit 14, the page number detection circuit 16 and the memory controller 8 have a role as analysis means.

FIG. 2 is a flow chart showing the outline of the processing in the data analysis apparatus 1. Step S1: The memory controller 8 counts the number of accesses (references) of each page in digital form based on the address signal S2a as a pulse-shaped signal to the cache memory 4 of the CPU 2. Step S2: The D / A conversion circuit 10 converts the access count counted in digital form in step S1 into an analog amount. Step S3: The analog analysis circuit 14, the page number detection circuit 16 and the memory controller 8 perform the step S2.
Analog analysis is performed on the analog amount indicating the number of times of access of each page converted in step 1, and the page to be saved is determined. Step S4: The memory controller 8 performs step S3
The page determined in step 1 is saved from the cache memory 4 to the external memory 6, and the page required for the processing of the CPU 2 is transferred from the external memory 6 to the cache memory 4.

The operation of the digital circuit will be described below. For example, when a predetermined storage data is accessed during execution of a process according to a program created in advance, the CPU 2 outputs an address signal S2a specifying the storage data to be accessed to the cache memory 4 and the memory controller. Output to 8. This address signal S
2a includes, for example, a page number and an address within the page for specifying stored data to be accessed.

When the page indicated by the address signal S2a exists in the cache memory 4, the page transfer process by the memory controller 8 is not performed, and the address within the page indicated by the address signal S2a is accessed by the CPU 2 to obtain the processed data. 4a is read, or the processing result 2b is written.

On the other hand, when the page indicated by the address signal S2a does not exist in the cache memory 4, the memory controller 8 outputs the instruction signals S8b and S8c to the cache memory 4 and the external memory 6, and as described later, the cache is used. Of the pages existing in the memory 4, the page 4b that is accessed less frequently by the CPU 2 is saved in the external memory 6, and the page 6a indicated by the address signal S2a is transferred to the cache memory 4. afterwards,
The transferred page is accessed by the CPU 2, the processing data 4a is read, or the processing result 2b is written.

The page transfer process in the memory controller 8 will be described below. Memory controller 8
Has an address counter S2 from the CPU 2 having a number of counters corresponding to the number of pages existing in the cache memory 4.
The number of accesses from the CPU 2 is counted for each page based on a. The count result of the counter is output to the D / A conversion circuit 10 as a digital count signal S8a.

FIG. 3 is a diagram for explaining the count signal S8a output from the memory controller 8 to the D / A conversion circuit 10. In FIG. 3, pages with page numbers “1” to “20” are stored in the cache memory 4. For example, the page number “4” is a CP within a predetermined time.
It indicates that the number of accesses from U2 is "8".

The memory controller 8 outputs the digital data to the D / A conversion circuit 10 when the page indicated by the address signal S2a input from the CPU 2 does not exist in the cache memory 4, and the cache data is cached as described later. A page number signal S16 indicating a page to be saved from the memory 4 to the external memory 6 is input from the page number detection circuit 16. When the page number signal S16 is input, the memory controller 8 outputs the instruction signals S8b and S8c to the cache memory 4 and the external memory 6, and outputs the page indicated by the page number signal S16 to the cache memory 4
To the external memory 6.

After that, the memory controller 8 outputs the instruction signals S8a and S8c to the cache memory 4 and the external memory 6, and places the page indicated by the address signal S2a in the area of the cache memory 4 corresponding to the saved page. Transfer from the external memory 6.

The D / A conversion circuit 10, the filter circuit 12, the analog analysis circuit 14, and the page number detection circuit 16 will be described below. The D / A conversion circuit 10 receives the digital count signal S8 from the memory controller 8.
a is input, the count signal S8a is analog-converted, and the analog-converted count signal S10 is output to the filter circuit 12.

The filter circuit 12 filters the analog-converted count signal S10 to remove high-frequency components, and outputs the filtered count signal S12 as shown in FIG. 4 to the analog analysis circuit 14. . In FIG. 4, the time on the horizontal axis corresponds to the page number,
The voltage on the vertical axis corresponds to the number of accesses of the CPU 2 to each page, and Vmax indicates the maximum voltage.

The analog analysis circuit 14 is a filter circuit 1.
The count signal S12 shown in FIG. 2 to FIG. 4 is input, and the time from when the count signal S12 is first input to when the peak voltage is input is detected using a time counter.
For example, in FIG. 3, the counter of the analog analysis circuit 14 detects the time tmax when the count signal S10 is first input, that is, from the time “0” until the maximum voltage Vmax is input. Analog analysis circuit 14
Outputs the time tmax detected by the counter to the page number detection circuit 16 as a signal S14. The page number detection circuit 16 converts the time tmax input from the analog analysis circuit 14 into a page number based on the following equation (1).

Page number = tmax × (20 / T) (1)

Here, "T" indicates the time from the time "0" until the signal relating to the page of page number 20 is input as shown in FIG. The page number detection circuit 16 outputs to the memory controller 8 a page number signal S16 indicating the page number converted based on the above equation (1).
As described above, the memory controller 8 transfers the page indicated by the page number signal S16 from the cache memory 4 to the external memory 6.

As described above, according to the data analysis apparatus 1 of this embodiment, when the page to be saved from the cache memory 4 to the external memory 6 is determined like the computer described as the prior art, the digital data is saved. The page to be saved can be determined by performing the analog analysis using the analog data without performing the arithmetic processing using. As a result, it is possible to reduce the amount of calculation in digital form in the digital circuit. Further, when the amount of data to be analyzed is large, such as when the number of pages existing in the cache memory 4 is large, the analysis time can be shortened as compared with the case where digital analysis is performed. Also, CP
The processing load is not imposed on the U2, and the expensive CPU2 can be efficiently used.

In addition to the above-described embodiments, the present invention detects, for example, how much a frequency band corresponding to a specific address is generated by comparing the address itself output to the cache memory by the CPU with the frequency. The frequency / spectrum analysis may be performed to detect an address with a high access frequency, and the page to be saved in the external memory 6 may be determined.

The second embodiment will be described. In the present embodiment, in a multiprocessor system having a plurality of CPUs and a cache memory corresponding to each CPU, and performing a predetermined process in a distributed manner among the plurality of CPUs, the number of access times from each CPU to each cache memory Is measured with an analog amount, and based on the measured analog amount, multiple CPs are
An example of determining the distribution of processing for U will be described.

FIG. 4 is a block diagram of the digital circuit of this embodiment. As shown in FIG. 4, the multiprocessor system 21 of the present embodiment has CPUs 22 to 2 as arithmetic means.
8, cache memories 32 to 38 as storage means, a shared memory 52, and a processing distribution circuit 60. The data analysis device 31 of the present embodiment is composed of capacitors 42 to 48 as signal generation means and an analog analysis circuit 56 as analysis means.

FIG. 6 is a flow chart showing an outline of processing in the multiprocessor system 21 and the data analysis device 31. Step S1: The capacitors 42 to 48 are the CPU 22 to
28 accumulates charges according to the number of times of access to the cache memories 32 to 38, and has a voltage according to the number of times of access. Step S2: The analog analysis circuit 56 uses the capacitor 4
2 to 48 are input, and the CPUs 22 to 28 corresponding to the capacitors 42 to 48 having the maximum voltage are determined as the CPUs to which the processing is preferentially assigned. Step S3: The processing distribution circuit 60 preferentially allocates the processing to the CPU determined in step S2.

The operations of the multiprocessor system 21 and the data analysis device 31 will be described below. In the multiprocessor system 21, predetermined processing is distributed to the CPUs 22 to 28 by the processing distribution circuit 60, and the distributed processing is executed in the CPUs 22 to 28, respectively.

The CPUs 22 to 28 are connected to the cache memory 3
The data related to the processing in the CPUs 22 to 28 is connected to the shared memory 52 via the shared memories 5 to 38 in response to the access signals S22a to S28a.
2 is transferred to and stored in the cache memories 32 to 38.

In the data analysis device 31, the condenser 42
To 48 input the access signals S22a to S28a output from the CPUs 22 to 28, and access signal S2.
Charges according to the number of inputs of 2a to S28a are accumulated, and a storage voltage according to the number of inputs is stored.

The analog analysis circuit 56 includes a capacitor 42
~ 48 to accumulated voltage signals S42 to S4 corresponding to the accumulated voltage
8 is input, the stored voltages of the capacitors 42 to 48 are compared, and a signal S56 indicating the magnitude relationship of the stored voltages of the capacitors 42 to 48 is output to the processing distribution circuit 60.

The processing distribution circuit 60 comprises the analog analysis circuit 5
The signal S56 is input from 6 and the processing is distributed to the CPUs 22 to 28 based on the signal S56. The distribution of the above processing in the processing distribution circuit 60 is performed by, for example, the CPU 2 corresponding to the cache memories 32 to 38 having high accumulated voltages.
The processing is preferentially distributed to 2 to 28. That is, the CPU
Since there is a high possibility that the cache memories 32-38 that have been accessed many times by the CPUs 22-28 already store the data related to the processing being executed by the CPUs 22-28, the cache memories 32-38 are frequently accessed. Processing is preferentially distributed to the CPUs 22 to 28 that are
The processing time in steps 28 to 28 is shortened.

As described above, in the multiprocessor system 21 of this embodiment, the data analysis device 31 is used to
The number of accesses to the cache memories 32 to 38 of the CPUs 22 to 28 is measured as an accumulated voltage of the capacitors 42 to 48 in an analog amount and analyzed. Therefore, CPU2
The operation states of the cache memories 32 to 38, that is, the storage states are detected and analyzed without burdening the processes of the CPUs 2 to 28, and the processes are distributed to the CPU 2 by the process distribution circuit 60.
2 to 28 can be appropriately dispersed.

The present invention is not limited to the above embodiment,
For example, the data analysis device 1 of the first embodiment described above is
For example, a capacitor as a signal generating means as shown in the second embodiment is provided for each page, and when the address signal S2a is input from the CPU 2, a voltage is accumulated in the capacitor corresponding to the page number indicated by the address signal S2a, Alternatively, the page to be saved from the cache memory 4 to the external memory 6 may be determined based on the magnitude relationship of the accumulated voltage.

In the data analysis device 21 of the second embodiment described above, C is stored in each of the cache memories 32 to 38.
The number of capacitors corresponding to the number of processes executed by the PUs 22 to 28 is provided, and a voltage corresponding to the number of times the CPUs 22 to 28 access the cache memories 32 to 38 is stored in the capacitors for each process. The processing may be distributed to the CPUs 22 to 28 for each process. For example, when a high voltage is stored in the capacitor of the CPU 22 related to the process A, the process distribution circuit 60 allocates the process related to the process A to the CPU 22.

The data analysis device 21 of the second embodiment described above includes the CPUs 22 to 22 of the cache memories 32 to 38.
A counter for counting the number of accesses from 28 may be provided, and the count result may be converted into an analog amount and analyzed by the D / A conversion circuit like the data analysis device 1 of the first embodiment. .

The data analysis apparatus of the present invention is not limited to the storage management of the digital circuit described above, but can be used for detecting the operating state of other digital circuits. Further, the data analysis apparatus of the present invention performs Fourier transform processing on analog data when performing analog analysis, and analyzes the frequency of the converted data using a spectrum analysis method or the like, thereby The operating state may be detected. Furthermore, the data analysis apparatus of the present invention can be used not only for the above-mentioned storage management, but also for communication control between digital circuits, bus arbitration, and the like.

Although the present invention has been described with respect to a data analysis device for performing page management and processing distribution, the data analysis method used in the data analysis device of the present invention can also be used for a data management method for page management and processing distribution. You can

[0038]

As described above, according to the present invention,
It is possible to reduce the calculation amount of the digital format in the digital circuit and reduce the load on the calculation means. Also,
According to the data analysis device of the present invention, it is possible to reduce the storage amount of digital data in a digital circuit and reduce the memory capacity. Further, according to the data analysis apparatus of the present invention, when the amount of data used for detecting the operating state of the digital circuit increases, the data is analyzed in an analog manner, so that the detection time can be shortened. Further, according to the data analysis apparatus of the present invention, an operation using digital data is performed when determining a page to be saved from the first storage means to the second storage means, as in the electronic computer described as the prior art. The page to be saved can be determined by performing analog analysis using analog data without performing processing. As a result, it is possible to reduce the amount of calculation in digital form in the digital circuit. Further, when the amount of data to be analyzed is large, such as when the number of pages existing in the first storage means is large, the analysis time can be shortened as compared with the case where digital analysis is performed. According to the data analysis device of the present invention,
The operation state of the storage unit, that is, the storage state can be detected and analyzed without burdening the calculation unit, and the processing can be appropriately distributed to the plurality of calculation units.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a digital circuit and a data analysis device according to a first embodiment.

FIG. 2 is a diagram for explaining an outline of processing in the data analysis device shown in FIG.

FIG. 3 is a diagram for explaining a digital count signal output from the memory controller shown in FIG. 1 to a D / A conversion circuit.

FIG. 4 is a diagram for explaining an analog count signal output from the filter circuit shown in FIG. 1 to an analog analysis circuit.

FIG. 5 is a configuration diagram of a multiprocessor system and a data analysis device of a second embodiment.

FIG. 6 is a diagram for explaining an outline of processing in the multiprocessor system and the data analysis device shown in FIG.

[Explanation of symbols]

 2, 22, 24, 26, 28 ... CPU 4, 42, 44, 46, 48 ... Cache memory 6 ... External memory 8 ... Memory controller 10 ... D / A conversion circuit 12. ..Filter circuit 14 ... Analog analysis circuit 16 ... Page number detection circuit 42,44,46,48 ... Capacitor 52 ... Shared memory 56 ... Analog analysis circuit 60 ... Processing distribution circuit

Claims (3)

[Claims] 1. A digital circuit that outputs a pulse-shaped signal that indicates the occurrence or termination of a plurality of types of operations, and a predetermined calculation is performed according to the pulse-shaped signal that is output from the digital circuit. Signal creating means for creating an analog signal according to the output of the signal, signal processing of the analog signal created by the signal creating means, and analysis of the operating state of the digital circuit based on the frequency of occurrence of the plurality of operations. A data analysis device, comprising: 2. In the digital circuit, the arithmetic means outputs the pulse-shaped signal to access the first storage means to access the first storage means and the second storage means by using a paging system. An electronic computer for storage management, wherein the analysis means performs signal processing on the analog signal created by the signal creation means, and based on the access frequency performed by the calculation means for each page of the first storage means. hand,
The data analysis apparatus according to claim 1, wherein a page to be saved from the first storage unit to the second storage unit is determined. 3. The digital circuit has a plurality of arithmetic means and storage means corresponding to each of the arithmetic means,
In the multiprocessor system, the predetermined processing is performed by the plurality of arithmetic means in a distributed manner, and the arithmetic means outputs the pulsed signal to the corresponding storage means to access the storage means. The analog signal created by the creating means is subjected to signal processing, and the distribution of the processing to the plurality of operating means is determined based on the access frequency performed by the plurality of operating means to the corresponding storage means. The data analysis device according to claim 1, wherein