JPH0713788B2 - Image display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device for displaying a plurality of drawings and the like in a superimposed manner with priority.

[Background of the Invention]

In a conventional display device having a pixel memory, writing to the pixel memory is always in a rewrite mode, and its contents are rewritten with new data regardless of whether or not there is data in the pixel memory. Therefore, when pixel data such as a plurality of drawings overlapped is input, a pixel of a drawing input later replaces a pixel of an overlapping portion of the previously stored drawing, and the portion becomes invisible. Therefore, it is not possible to input the data of another drawing that overlaps and make the data in the pixel memory as if it exists after the previously stored drawing in the pixel memory. , And the data of the drawing existing on the upper side (front side) is input again, or a processing by a program is required so as not to generate an overlapping pixel with respect to the drawing data of the rear side. Conventionally, there have been problems in re-transferring data for such processing and processing time in speeding up the display.

[Object of the Invention]

An object of the present invention is to display a plurality of drawings in an overlaid display,
An object of the present invention is to provide an image display device capable of displaying a high-priority drawing at a high speed so as to be sequentially positioned in front of a low-priority drawing regardless of the order of inputting drawing data.

[Outline of Invention]

To achieve the above object, the present invention relates to an image display device having an image generation device for generating pixel data to be stored in a pixel memory and a display unit for reading and displaying the pixel data of the pixel memory, The memory stores image information having a plurality of drawing areas as pixel data,
Information indicating the priority between a plurality of drawing areas is stored in a storage position corresponding to a pixel of the pixel memory, and a plurality of planes having a plurality of planes capable of determining the order of priority are provided and the drawing areas between the drawing areas are Priority storage memory capable of rewriting the priority of drawing display when drawings overlap based on a signal representing priority, read signal from the priority storage memory, and pixel data to be written from the image generating device Based on the result of the comparing means, comparing means for comparing the signal indicating the priority corresponding to the above in pixel units, and whether or not the pixel data from the image generating device to be written in the pixel memory is written in the pixel memory. Write control means for controlling An image display device.

As described above, according to the configuration described above, it is possible to create pixel data for overlapping display in the priority order of the drawings without changing the previously stored pixel data of the drawings with high priority.

Example of Invention

First, a supplementary description will be given of contents that are not the embodiment of the present invention with reference to FIGS. 1 and 2. FIG. 1 (a) is an example in which one drawing A is displayed on the screen of the display device.
Next, as shown in FIG. 1 (b), a case will be described in which overwriting display is performed so that FIG.

FIG. 2 is a diagram showing a device configuration for supplementary explanation of contents that are not the embodiment of the present invention. In FIG. 2, the memory 25 for storing the light mask and the pixel memory
The gates 23 and 24 for controlling the writing of 26 and the writing memory selection register 22 for selecting 25 and 26 are the portions for controlling the overwriting of the A and B diagrams. The graphic image display device 21 is
Figure and image information are expanded to pixel data. 26 stores the pixel data D in accordance with the write address A and the write pulse W generated at 21. The image converter 27 has a pixel memory 26.
The contents of are scanned, read in order, converted into video signals, and displayed on the CRT monitor 29. The graphic image generator 21 is
In addition to generating the above data, information for selecting the 25th and 26th memories is further set in the register 22 to generate write mask data DM to the 25th memories. Here, the write mask data can be generated at the same time as the pixel data is generated, or can be generated separately. Further, in 25 of FIG. 2, the area of the light mask has a rectangular shape corresponding to the area of the drawing, but it is also possible to set 21 to form an area of any shape. . Whether or not the memory 25 can be written is controlled by the output of the AND gate 23, and is determined by AND (logical product) of the memory selection register 22 and the write pulse generated in 21. Whether the memory 26 can be written or not is read out by reading the contents of the memory 25 with the read pulse R generated at 21, and the result is latched once in the register 28.
Further, the gate 24 determines the negation of the contents of the register 28 and the AND of the write pulse of the memory selection register 22 and 21. That is, in the memory of 25, in the area where the write mask is written, the output of the gate 24 becomes “0”,
Writing of subsequent pixels is not performed.

As a result, in order to obtain the result as shown in FIG. 1, the data of FIG. A is first stored, and then the write mask data is stored in the memory of 25 at the position corresponding to the existing area of FIG. Here, the existence area of FIG. A is the entire definition area of the drawing regardless of the presence or absence of display data. At this time, when FIG. A is a picture image which covers the entire drawing, writing to the memories 25 and 26 may be performed simultaneously. Next, when the writing of FIG. B is performed, the writing of the pixel into the area where the FIG. A exists is suppressed by the write mask data.
Overwrite pixels are created at 26 such that the figure is behind it. Therefore, rewriting of Fig. A and B by program
When it takes a long time to perform the mask processing of the pixels in the figure, the processing time is significantly shortened.

In the above example, the drawings with the highest priority are stored first. However, when the drawings with the lowest priority are stored in order, it is necessary to erase 25 memories in advance. At this time, it is not necessary to write the write mask data thereafter, which is the same as the conventional one.

Next, in the case of randomly transferring and storing the constituent elements of FIGS. A and B, 22 is controlled, and when storing the constituent elements of FIG. A, 25 does not act, and the constituent elements of FIG. B are stored. At this time, 25 should work effectively.

Embodiments of the present invention will be specifically described below with reference to FIGS. 3 and 4. FIG. 3 (a) is an example in which the two drawings of FIGS. A and B are superimposed and displayed on the screen of the display device. Next, a case will be described in which a diagram C is inserted between the diagrams A and B as shown in FIG. FIG. 4 shows the configuration of a device that realizes this. Where 41,42,43,44,46,47
Respectively correspond to 21, 22, 23, 24, 26 and 27 in FIG.

In this embodiment, based on the address A of the pixel output from the drawing pixel generator 41, pixel data is added to the pixel data from the figure pixel generator 41 as the attribute value DM (priority order of the drawing, for example, drawing priority) for each drawing (drawing area). “4” is given for the A diagram, “1” is given for the B diagram, and “2” is given for the C diagram), and the priority of the higher priority obtained from the comparator 9 for each memory pixel is the newly added priority. It is written in the storage memory 45. 45 can set the priority of 3 bits and 3 planes). This gives 0-8 of 0-7
The priority of street drawings can be stored. The write control for the pixel memory 46 and the priority storage memory 45 is performed as follows.

First, the previous priority at the address of the pixel to be written is 45 due to the read pulse R generated at 41.
Read out from the memory of FIG. 1, once latched in the register 48, and then transferred through the data line DP to the newly added comparator 49. This content is compared with the priority DM of the pixel which is about to be written by the comparator 49, and the result is gated.
Input to 43,44 to control writing to the memory of 45,46.
Comparator 49, when DM is equal to or greater than the content of DP,
Outputs "1", otherwise outputs "0". As a result, the output of the gates 43 and 44 becomes "0" for the region where the priority of the previously stored drawing is higher, and the memory 4
The contents of 5,46 remain unchanged.

To obtain the display result of FIG. 3, the following may be done. First, FIGS. A and B are stored, and then the priority of each drawing is written in the memory 45 over the entire area where the drawing exists. At this time, when the display data of each drawing is an image image that covers the entire drawing, it is possible to simultaneously write to two memories 45 and 46. However, when the display data is a line drawing, it is necessary to store the priority in the memory 45 even where there are no lines in the same drawing. Therefore, writing to the memory 46 and the memory 45 is performed independently. That is,
Writing to the priority storage memory 45 is performed as follows. That is, first, a signal "1" is selected and applied from the plane selection register 42 to the AND gate 43, and the "1" signal of the write pulse W output from the graphic image generating device 41 and DM are DP (image region). When there is no, it is equal to or greater than "0)" and AN with the "1" signal output from the comparator 49
D is taken by the AND circuit 43 and the write signal W of "1" is applied, and the address A of the pixel output from the graphic pixel generating device 41 on the priority storage memory 45 causes the graphic image generating device in the area A in FIG. "4" is written as the priority DM generated from 41, and "1" is written as the priority DM generated from the graphic image generation device 41 in the B area.
Is written. Next, since the figure C is sandwiched between the figure A and the figure B, the address DM of the pixel output from the figure pixel generator 41 is used as the priority DM generated from the figure image generator 41 for the area C of the figure. When the "1" signal of the write signal W output from the graphic image generator 41 and DM are equal to or larger than DP, that is, "2" is set and output, that is, the "49" is output from the comparator 49 in a region other than the A region. AND with 1 "signal
Is applied by the AND circuit 43 and the write signal W of "1" is applied, and "2" is written as the priority DM in the C memory area other than the A memory area on the priority storage memory 45.

Next, writing to the pixel memory 46 is performed as follows. That is, first, a signal "1" is selected from the plane selection register 42 and applied to the AND gate 44, and applied.
The priority (priority) stored in the priority storage memory 45 is read by the read pulse R generated from 41, and the comparator 49 causes the graphic image generating device 41 to generate “4” for the A area and B for the B area. "1"
AND circuit 44 takes the AND of the "1" signal output by comparing the priority DM and the read DP with the "1" signal of the write pulse W output from the graphic image generating device 41. A write signal W of 1 "is applied to the pixel memory
The pixel data D generated from the graphic image generating device 41 is written in the A area by the address A of the pixel output from the graphic pixel generating apparatus 41 on the 46, and the graphic image generating device 41 is written in the B area. Pixel data D generated from is written. Next, the C figure area generated from the graphic image generator 41 from the comparator 49 is compared with the priority DM of "2" and the read DP, and is output in the C figure area other than the A figure area. The pixel data D generated from the graphic image generating device 41 is written in the C area other than the A area on the pixel memory 46 by the signal. If the C drawing is a line drawing, it is necessary to write the pixel data D after erasing the C drawing area other than the A drawing area. As a result, the C diagram is written in the pixel memory 46 with the priority given in the middle of the A diagram and the B diagram. And video conversion 47
By scanning the contents of the pixel memory 46 in order and converting them into a video signal, the CRT monitor performs overwriting display such that the C diagram exists between the A diagram and the B diagram, and the A diagram is redisplayed. Alternatively, when the mask processing of the diagram C by the program takes time, the processing time is shortened in this embodiment.

〔The invention's effect〕

According to the present invention, when a plurality of drawings or drawing areas are displayed in an overlapping manner, a drawing or drawing area with a high priority is not rewritten by a drawing or drawing area with a low priority displayed later. It is possible to obtain the effect that it is possible to execute at high speed which process is to be preferentially displayed.

[Brief description of drawings]

FIG. 1 is a display example of a screen showing control of overwriting display of two drawings, FIG. 2 is a configuration example of a device for supplementary explanation of contents according to the present invention, and FIG. 4 is a display example of a screen showing control of overwriting display of the drawing of FIG. 4, and FIG. 4 is a configuration example of an apparatus showing an embodiment of the present invention. 21, 41 …… Graphic image generator, 22, 42 …… Memory selection register, 25 …… Write mask storage memory, 45 …… Priority storage memory, 26, 46 …… Pixel memory, 28, 48…
... Registers that latch memory read data, 27, 47 ...
… Video converter, 23,24,43,44 …… AND gate.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Shigeo Tsujioka 1-280 Higashi Koikekubo, Kokubunji City, Tokyo Inside Hitachi Central Research Laboratory (72) Innovator Motonobu Tonomura 1-280 Higashi Koikekubo, Kokubunji City, Tokyo Central Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-50-141223 (JP, A)

Claims (1)

[Claims] 1. An image display device having an image generation device for generating pixel data to be stored in a pixel memory and a display means for reading and displaying the pixel data of the pixel memory, wherein the pixel memory has a plurality of drawing areas. Image information having is stored as pixel data, information indicating the priority among a plurality of drawing areas is stored in a storage position corresponding to a pixel of the pixel memory, and a plurality of planes capable of determining the priority order are set. A priority storing memory which has the priority of the drawing display when the drawings overlap each other based on the signal indicating the priority between the drawing areas from the image generating device, and a read signal from the priority storing memory Corresponding to the pixel data to be written from the image generator Comparing means for comparing the signal indicating the priority in pixel units, and controlling whether or not to write the pixel data from the image generating device to be written in the pixel memory to the pixel memory based on the result of the comparing means. An image display device comprising a writing control means.