JPH07128414A - Battery test device, and electric power device having the test device built in - Google Patents
Battery test device, and electric power device having the test device built inInfo
- Publication number
- JPH07128414A JPH07128414A JP5294100A JP29410093A JPH07128414A JP H07128414 A JPH07128414 A JP H07128414A JP 5294100 A JP5294100 A JP 5294100A JP 29410093 A JP29410093 A JP 29410093A JP H07128414 A JPH07128414 A JP H07128414A
- Authority
- JP
- Japan
- Prior art keywords
- battery
- power
- test device
- circuit
- ram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
- G01R31/382—Arrangements for monitoring battery or accumulator variables, e.g. SoC
- G01R31/3842—Arrangements for monitoring battery or accumulator variables, e.g. SoC combining voltage and current measurements
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electric Status Of Batteries (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、バッテリ残容量判定又
は劣化判定を行うバッテリ試験装置、および同試験装置
を内蔵した電力装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a battery test device for making a battery remaining capacity judgment or a deterioration judgment, and a power device incorporating the same.
【０００２】[0002]
【従来の技術】図４は、従来のバッテリ試験装置に於け
る検出方法の一例を示すブロック図である。図４におい
て、１はバッテリ電流検出回路、２，８は高速広帯域オ
ペアンプ、３，９は高速のサンプルホールド回路、４，
１０は高速のＡＤ変換器、５はデータ処理回路、６，１
１はデータ蓄積専用ＲＡＭ、７はバッテリ電圧検出回
路、１２はマイクロプロセッサである。2. Description of the Related Art FIG. 4 is a block diagram showing an example of a detection method in a conventional battery test apparatus. 4, 1 is a battery current detection circuit, 2 and 8 are high speed wide band operational amplifiers, 3 and 9 are high speed sample and hold circuits, 4 and
10 is a high-speed AD converter, 5 is a data processing circuit, 6, 1
Reference numeral 1 is a RAM dedicated to data storage, 7 is a battery voltage detection circuit, and 12 is a microprocessor.
【０００３】所定の期間に、バッテリの充放電電流Ｉ
BATTは、バッテリ電流検出回路１に於てシャント抵抗あ
るいはホール素子等の検出方法で電流電圧変換され、該
電圧は、高速広帯域オペアンプ２に於て、高速に、かつ
後段の回路が処理できる範囲の適当な電圧値まで増幅さ
れる。増幅された該電圧は、高速のサンプルホールド回
路３により、例えば１０ＭＨｚサンプリングのような高
速動作でサンプリング（１００ｎｓサンプリング）さ
れ、かつホールドされる。ホールドされたデータは、高
速のＡＤ変換器４によりディジタル変換され、データ処
理回路５の選択回路によりデータ蓄積専用ＲＡＭ６に逐
次保管される。During a predetermined period, the charge / discharge current I of the battery
BATT is current-voltage converted in the battery current detection circuit 1 by a detection method such as a shunt resistance or a Hall element, and the voltage is within a range that can be processed by the high-speed wide-band operational amplifier 2 at a high speed and in the subsequent circuit. It is amplified to an appropriate voltage value. The amplified voltage is sampled (100 ns sampling) and held by the high-speed sample-hold circuit 3 at a high-speed operation such as 10 MHz sampling. The held data is digitally converted by the high-speed AD converter 4, and sequentially stored in the data storage RAM 6 by the selection circuit of the data processing circuit 5.
【０００４】この間は、例えば５０μｓ間内に５００デ
ータの収集で、１データ当たりの検出から保管までのト
ータル処理時間は１００ｎｓと極めて高速に行う。一
方、バッテリの端子電圧ＶBATTは、前記バッテリの充放
電電流検出と同様の所定の期間に、バッテリ電圧検出回
路７において直接若しくは抵抗分圧回路等の検出方法で
高速広帯域オペアンプ８に送られ、バッテリの充放電電
流の検出方法と同様に、高速広帯域オペアンプ８に於
て、高速に、かつ後段の回路が処理できる範囲の適当な
電圧値まで増幅される。増幅された該電圧は、高速のサ
ンプルホールド回路９により、例えば１０ＭＨｚサンプ
リングのような高速動作でサンプリングされ、かつホー
ルドされる。ホールドされたデータは、高速のＡＤ変換
器１０によりディジタル変換され、データ処理回路５の
選択回路によりデータ蓄積専用ＲＡＭ１１に逐次保管さ
れる。During this period, for example, 500 data are collected within 50 μs, and the total processing time from detection to storage per data is 100 ns, which is extremely fast. On the other hand, the terminal voltage V BATT of the battery is sent to the high-speed wideband operational amplifier 8 directly in the battery voltage detection circuit 7 or by a detection method such as a resistance voltage dividing circuit during a predetermined period similar to the detection of the charging / discharging current of the battery. Similar to the method of detecting the charge / discharge current of the battery, the high-speed wide-band operational amplifier 8 performs high-speed amplification to an appropriate voltage value within the range that can be processed by the subsequent circuit. The amplified voltage is sampled and held by the high-speed sample-hold circuit 9 at a high-speed operation such as 10 MHz sampling. The held data is digitally converted by the high-speed AD converter 10 and sequentially stored in the data storage dedicated RAM 11 by the selection circuit of the data processing circuit 5.
【０００５】以上の方法で検出したＲＡＭ６，１１内の
バッテリ端子電圧及びバッテリ充放電電流のデータを、
所定の期間内の検出が終了した時点で、データ処理回路
５を通してマイクロプロセッサ１２の周辺として位置づ
けられたＲＡＭ（図示せず）に逐次保管又は加算され、
マイクロプロセッサ１２で一括処理される。そして該バ
ッテリ端子電圧及びバッテリ充放電電流の平均値を計算
し、バッテリの内部抵抗を算出することにより、バッテ
リの残容量判定若しくは劣化判定を行うものであった。The data of the battery terminal voltage and the battery charging / discharging current in the RAMs 6 and 11 detected by the above method are
Upon completion of detection within a predetermined period, the data is sequentially stored or added to a RAM (not shown) positioned as a peripheral of the microprocessor 12 through the data processing circuit 5,
Collectively processed by the microprocessor 12. Then, the average value of the battery terminal voltage and the battery charging / discharging current is calculated, and the internal resistance of the battery is calculated to determine the remaining capacity or the deterioration of the battery.
【０００６】[0006]
【発明が解決しようとする課題】しかし、上記の技術は
以下のごとき欠点を有していた。 量子化誤差を減らすために、所定の期間内でのサンプ
リングを多くすると、高速広帯域オペアンプ及び、高速
動作可能なサンプルホールド回路及びＡＤ変換器が必要
になる。 所定の期間内でサンプリングされた、多くのデータを
収集し一括処理するため、データを保管するためのデー
タ蓄積専用ＲＡＭが必要である。 通常の高速サンプリングでは、電流出力回路と電圧出
力回路の各々の系統に高速広帯域オペアンプ、サンプル
ホールド回路及び高速ＡＤ変換器を必要とした。また、
更に高速化することは回路構成が複雑になり一般的でな
い。However, the above technique has the following drawbacks. If sampling is increased within a predetermined period in order to reduce the quantization error, a high-speed wideband operational amplifier, a sample-hold circuit and an AD converter capable of high-speed operation are required. Since a large amount of data sampled within a predetermined period is collected and collectively processed, a data storage dedicated RAM for storing the data is required. In normal high-speed sampling, a high-speed wide-band operational amplifier, a sample hold circuit, and a high-speed AD converter are required for each system of the current output circuit and the voltage output circuit. Also,
Further speeding up is not common because the circuit configuration becomes complicated.
【０００７】以上の要因は全てシステムが大型化して、
しかも高価になりやすく、又多数の高速で動作する個別
部品を使用する事により、部品間の配線からの高周波ノ
イズの送受信が行われ、高周波ノイズに弱い原因にな
る。All of the above factors are caused by the large system.
Moreover, the cost tends to be high, and by using a large number of individual components that operate at high speed, high frequency noise is transmitted and received from the wiring between the components, which is a cause of weakness in high frequency noise.
【０００８】従って、本発明は、上記問題点を解決する
ため、比較的低速のオペアンプやサンプルホールド回路
及びＡＤ変換器でサンプリングやＡＤ変換を行う。サン
プルホールド回路はコンデンサと抵抗からなる積分回路
を用いているので、そのフィルタ効果によりサンプリン
グされたデータを平均化するので、サンプルデータ数を
少なくすることが出来、データ蓄積専用ＲＡＭを削減
し、システムを小型化にし、さらに高周波ノイズに強く
することを目的とするものである。Therefore, according to the present invention, in order to solve the above problems, sampling and AD conversion are performed by a relatively low speed operational amplifier, a sample hold circuit and an AD converter. Since the sample-hold circuit uses an integrator circuit consisting of a capacitor and a resistor, the sampled data is averaged by the filter effect, so the number of sample data can be reduced, and the dedicated RAM for data storage is reduced. The purpose is to reduce the size of the device and to make it more resistant to high frequency noise.
【０００９】[0009]
【課題を解決するための手段】すなわち、本発明は上記
の目的に対応して次の様な手段を有している。本発明の
バッテリ試験装置はバッテリ端子により、バッテリ電圧
とバッテリ充電電流又は放電電流を検出し、前記バッテ
リの内部抵抗を算出し、該バッテリの残容量判定又は劣
化判定を行うバッテリ試験装置に於て、前記バッテリ電
圧検出回路からの出力信号と前記バッテリ電流検出回路
からの出力信号は、１組のアナログマルチプレクサによ
り交互に切替え入力された後、１組の低速のサンプルホ
ールド回路により、前記アナログマルチプレクサからの
出力信号はホールドされた後、１組のＡＤ変換器により
ディジタル信号に変換され、前記ディジタル信号をデー
タ蓄積用ＲＡＭに保管することなく、直接マイクロプロ
セッサの周辺として位置づけられたＲＡＭに保管し、該
ＲＡＭに保管されたディジタルデータを前記マイクロプ
ロセッサで一括処理することにより、前記バッテリ残容
量判定又は劣化判定を行うことを特徴としている。That is, the present invention has the following means corresponding to the above object. A battery testing device of the present invention is a battery testing device for detecting a battery voltage and a battery charging current or a discharging current by a battery terminal, calculating an internal resistance of the battery, and performing a remaining capacity determination or a deterioration determination of the battery. The output signal from the battery voltage detection circuit and the output signal from the battery current detection circuit are alternately switched and input by a set of analog multiplexers, and then input from the analog multiplexer by a set of low-speed sample hold circuits. After being held, the output signal of is converted into a digital signal by a set of AD converters, and the digital signal is directly stored in a RAM positioned as a peripheral of the microprocessor without being stored in the RAM for data storage, The microprocessor stores the digital data stored in the RAM. By batch process, it is characterized by performing the remaining battery capacity determining or degradation determination.
【００１０】さらに本発明の電力装置は交流入力を電源
とし、直流出力を得るＡＣ／ＤＣコンバータ、又は交流
出力を得るＡＣ／ＡＣコンバータが、蓄電池を充電しな
がら負荷に電力を供給し、前記交流入力停電時には前記
蓄電池を電源とし、直流又は交流電力を負荷に供給する
様構成された電力装置が前記バッテリ試験装置を内蔵
し、前記バッテリ試験装置は前記蓄電池の残容量の推定
判定又は劣化状態を観測し、その測定結果を前記電力装
置より外部に送出する機能を備えたことを特徴としてい
る。Further, in the power unit of the present invention, an AC input is used as a power source, and an AC / DC converter for obtaining a DC output or an AC / AC converter for obtaining an AC output supplies electric power to a load while charging a storage battery, At the time of an input power failure, the storage battery is used as a power supply, and a power device configured to supply DC or AC power to a load has the battery test device built therein, and the battery test device indicates an estimated determination of the remaining capacity of the storage battery or a deterioration state. It is characterized by having a function of observing and transmitting the measurement result to the outside from the power device.
【００１１】[0011]
【作用】バッテリ内部抵抗を算出する為のバッテリ電流
検出値とバッテリ電圧検出値を、１組のマルチプレクサ
で交互切替えして取出し、積分回路を有するサンプルホ
ールド回路によって、低速かつ少ない検出データを有効
に取り出し、ＡＤ変換器によりデジタル信号に変換す
る。このデジタル信号は低速である為、データ蓄積用Ｒ
ＡＭに保管する事なく、直接、マイクロプロセッサで処
理し、バッテリ内部抵抗演算を行う事を可能にしたバッ
テリ試験装置である。The battery current detection value and the battery voltage detection value for calculating the battery internal resistance are alternately switched and fetched by one set of multiplexers, and the sample and hold circuit having the integration circuit makes low-speed and small detection data effective. It is taken out and converted into a digital signal by an AD converter. Since this digital signal is slow, R for data storage
It is a battery test device that can be directly processed by the microprocessor and stored in the AM, and can be used to calculate the internal resistance of the battery.
【００１２】又、上記作用を行う、バッテリ試験装置を
電力装置に内蔵して、電力装置内に収納され、停電時バ
ックアップ電源としてのバッテリ内部抵抗を観測し、こ
の測定データを電力装置より外部に送出する様に構成さ
れ、電力装置の信頼性向上を計っている。Further, the battery test device for performing the above-mentioned operation is incorporated in the power device, and is housed in the power device to observe the internal resistance of the battery as a backup power source at the time of power failure, and to output this measurement data to the outside of the power device. It is configured to send out, and the reliability of the power device is improved.
【００１３】[0013]
【実施例】図１は本発明のバッテリ試験装置の実施例で
あって、１はバッテリ電流検出回路、１３，１４はオペ
アンプ、１５はアナログマルチプレクサ、１６は低速の
サンプルホールド回路、１７はＡＤ変換器、７はバッテ
リ電圧検出回路、１２はマイクロプロセッサである。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of a battery testing apparatus of the present invention, in which 1 is a battery current detection circuit, 13 and 14 are operational amplifiers, 15 is an analog multiplexer, 16 is a low speed sample hold circuit, and 17 is AD conversion. , 7 is a battery voltage detection circuit, and 12 is a microprocessor.
【００１４】次にその動作を説明する。所定の期間内
で、バッテリの充放電電流ＩBATTは、バッテリ電流検出
回路１においてシャント抵抗若しくはホール素子等の検
出方法で電流電圧変換され、オペアンプ１３に於て、後
段の回路が処理できる範囲の適当な電圧値まで増幅され
る。Next, the operation will be described. Within a predetermined period, the battery charge / discharge current I BATT is converted into a current voltage by a detection method such as a shunt resistor or a Hall element in the battery current detection circuit 1, and the operational amplifier 13 has a range within which the circuit in the subsequent stage can process. It is amplified to an appropriate voltage value.
【００１５】一方、バッテリの端子電圧ＶBATTは、所定
の期間内で、バッテリ電圧検出回路７において直接若し
くは抵抗分圧回路等の検出方法でオペアンプ１４に送ら
れ、バッテリの充放電電流の検出方法と同様に、後段の
回路が処理できる範囲の適当な電圧値まで増幅される。On the other hand, the terminal voltage V BATT of the battery is sent to the operational amplifier 14 directly in the battery voltage detection circuit 7 or by a detection method such as a resistance voltage dividing circuit within a predetermined period to detect the charging / discharging current of the battery. Similarly, the voltage is amplified to an appropriate voltage value within the range that can be processed by the subsequent circuit.
【００１６】次に、バッテリ電流の増幅された電圧値と
バッテリ電圧の増幅された電圧値は、一組のアナログマ
ルチプレクサ１５に入力され、該バッテリ電流とバッテ
リ電圧が低速のサンプルホールド回路１６にて、交互に
サンプリングされ、かつホールドされる。ホールドされ
たデータは、ＡＤ変換器１７によりディジタル変換さ
れ、従来と同様マイクロプロセッサ１２の周辺として位
置づけられたＲＡＭ（図示せず）に逐次保管又は加算さ
れ、マイクロプロセッサ１２を介して処理される。Next, the amplified voltage value of the battery current and the amplified voltage value of the battery voltage are input to a pair of analog multiplexers 15, and the sample and hold circuit 16 having the low battery current and battery voltage. , Alternately sampled and held. The held data is digitally converted by the AD converter 17, sequentially stored or added in a RAM (not shown) positioned as a peripheral of the microprocessor 12 as in the conventional case, and processed through the microprocessor 12.
【００１７】この間は例えば試験用バッテリの充放電電
流の上昇又は降下時間の１００μｓを除いて、４００μ
ｓの時間内で２８データの収集で、１データ当たり検出
から保管まで１４μｓと低速である。また、サンプリン
グデータ数が少ないため、収集したデータのためのデー
タ蓄積専用ＲＡＭは必要とせず、サンプルホールド回路
１６はコンデンサと抵抗からなる積分回路により低速に
動作するから、その効果として高周波のノイズに対して
頑強になる。During this period, for example, 400 μ is excluded, except for 100 μs which is the rise / fall time of the charge / discharge current of the test battery.
28 data are collected within a time period of s, which is a low speed of 14 μs from detection to storage per data. Further, since the number of sampling data is small, a dedicated data storage RAM for collected data is not required, and the sample hold circuit 16 operates at a low speed by the integrating circuit including a capacitor and a resistance, and as a result, it is possible to reduce high frequency noise. It becomes tough against it.
【００１８】又、従来回路では高速サンプリングを行っ
ており、サンプリングを高速化する為には、システムの
大型化をまねいた。しかし、本発明の回路はサンプルホ
ールド回路の積分回路により、サンプリングデータを平
均化する事が出来るため、サンプリングの低速化が可能
であるので、電流検出信号と電圧検出信号は、アナログ
マルチプレクサにより交互に切替え処理が可能なので、
１系統のサンプルホールド回路及びＡＤ変換器で構成す
ることができる。Further, in the conventional circuit, high-speed sampling is performed, and in order to speed up the sampling, the size of the system is increased. However, in the circuit of the present invention, the sampling data can be averaged by the integration circuit of the sample hold circuit, so that the sampling speed can be reduced. Therefore, the current detection signal and the voltage detection signal are alternately switched by the analog multiplexer. Since switching processing is possible,
It can be composed of one system of sample and hold circuit and AD converter.
【００１９】尚、検出からデータ処理までの一連の動作
は、市販のシングルチップマイコン１８に置き換えると
システムが簡素化される。しかしこれらのシングルチッ
プマイコンは最大１０ビットが一般的である。従って、
測定精度を上げるためには図２のようにマイクロプロセ
ッサ１２を別チップとし、他の部分をＡＤ変換チップ１
９とすれば、最大１６ビットが可能となり測定精度を上
げることができる。If a series of operations from detection to data processing is replaced with a commercially available single chip microcomputer 18, the system will be simplified. However, these single-chip microcomputers generally have a maximum of 10 bits. Therefore,
In order to improve the measurement accuracy, the microprocessor 12 is provided as a separate chip as shown in FIG.
If it is set to 9, 16 bits at maximum are possible, and the measurement accuracy can be improved.
【００２０】図３は本発明のバッテリ試験装置を内蔵し
た電力装置の一実施例である。図において、２０は交流
入力であり、ＡＣ／ＤＣコンバータ２１、蓄電池２２に
前記バッテリ試験装置２３を組込んだものが電力装置２
４である。尚２５は負荷である。FIG. 3 shows an embodiment of a power device incorporating the battery testing device of the present invention. In the figure, reference numeral 20 is an AC input, and an AC / DC converter 21, a storage battery 22, and the battery test device 23 incorporated therein are the power devices 2
It is 4. In addition, 25 is a load.
【００２１】交流入力２０を受電し、ＡＣ／ＤＣコンバ
ータ２１より負荷２５に電力を供給しながら蓄電池２２
を充電し、交流入力２０が停電時には蓄電池２２より負
荷２５に電力を供給する電力装置にバッテリ試験装置２
３を組み込んだものである。A storage battery 22 receives an AC input 20 and supplies power to a load 25 from an AC / DC converter 21.
The battery test device 2 to the power device that charges the battery and supplies power to the load 25 from the storage battery 22 when the AC input 20 fails.
3 is incorporated.
【００２２】バッテリ試験装置２３は、例えば各電池毎
に配線を設けておき、蓄電池２２の単セル毎の残容量又
は劣化状態を定期的に測定し、結果を外部に転送した
り、あるいはタイマーを内蔵し、周期毎に測定を自動的
に行う等して、監視強化を図り、装置全体の信頼性を向
上させると共に、蓄電池劣化による電力装置のトラブル
を未然に防ぐことができる。The battery testing device 23 is provided with wiring for each battery, for example, to periodically measure the remaining capacity or the deterioration state of each single cell of the storage battery 22, and transfer the result to the outside, or use a timer. It is possible to improve the reliability of the entire device by incorporating it and automatically performing measurements every cycle to improve the reliability of the entire device and prevent troubles of the power device due to deterioration of the storage battery.
【００２３】[0023]
【発明の効果】本発明によれば、汎用のオペアンプ、低
速のサンプルホールド回路及びＡＤ変換器を使用し、さ
らにデータ蓄積専用ＲＡＭを必要としない為、バッテリ
試験装置は低価格になり、システムが小型化される。
又、サンプルホールド回路はコンデンサと抵抗の積分回
路により低速動作するから、高周波ノイズに対して頑強
になり、耐ノイズ性が改善されることが期待される。ま
た、このバッテリ試験装置を電力装置に組み込むことに
より、監視強化が図られるため電力装置全体の信頼性を
向上させることができる。According to the present invention, a general-purpose operational amplifier, a low-speed sample-hold circuit, and an AD converter are used, and a RAM dedicated for data storage is not required. Therefore, the battery test apparatus is low in cost and the system is Be miniaturized.
Further, since the sample-hold circuit operates at a low speed by the integrating circuit of the capacitor and the resistor, it is expected to be robust against high frequency noise and improve the noise resistance. Further, by incorporating this battery test device into the power device, the monitoring can be strengthened, so that the reliability of the entire power device can be improved.
【図１】本発明のバッテリ試験装置に於ける実施例を示
すブロック図。FIG. 1 is a block diagram showing an embodiment of a battery testing device of the present invention.
【図２】本発明のバッテリ試験装置に於ける他の実施例
を示すブロック図。FIG. 2 is a block diagram showing another embodiment of the battery testing device of the present invention.
【図３】本発明の電力装置システム図。FIG. 3 is a power device system diagram of the present invention.
【図４】従来のバッテリ試験装置に於ける検出方法の一
例を示すブロック図。FIG. 4 is a block diagram showing an example of a detection method in a conventional battery test device.
１ バッテリ電流検出回路 ２ 高速広帯域オペアンプ ３ 高速のサンプルホールド回路 ４ 高速のＡＤ変換器 ５ データ処理回路 ６ データ蓄積専用ＲＡＭ ７ バッテリ電圧検出回路 ８ 高速広帯域オペアンプ ９ 高速のサンプルホールド回路 １０ 高速のＡＤ変換器 １１ データ蓄積専用ＲＡＭ １２ マイクロプロセッサ １３ オペアンプ １４ オペアンプ １５ アナログマルチプレクサ １６ 低速のサンプルホールド回路 １７ ＡＤ変換器 １８ シングルチップマイコン １９ ＡＤ変換チップ ２０ 交流入力 ２１ ＡＣ／ＤＣコンバータ ２２ 蓄電池 ２３ バッテリ試験装置 ２４ 電力装置 ２５ 負荷 1 Battery Current Detection Circuit 2 High Speed Wideband Operational Amplifier 3 High Speed Sample and Hold Circuit 4 High Speed AD Converter 5 Data Processing Circuit 6 Data Storage Dedicated RAM 7 Battery Voltage Detection Circuit 8 High Speed Wideband Operational Amplifier 9 High Speed Sample and Hold Circuit 10 High Speed AD Conversion Device 11 RAM for exclusive use of data storage 12 Microprocessor 13 Operational amplifier 14 Operational amplifier 15 Analog multiplexer 16 Low-speed sample hold circuit 17 AD converter 18 Single chip microcomputer 19 AD conversion chip 20 AC input 21 AC / DC converter 22 Storage battery 23 Battery test device 24 Electric power Device 25 load
───────────────────────────────────────────────────── フロントページの続き (71)出願人 000004282 日本電池株式会社 京都府京都市南区吉祥院西ノ庄猪之馬場町 １番地 (72)発明者 小津 清嗣 埼玉県飯能市南町10番13号 新電元工業株 式会社工場内 (72)発明者 小林 公禎 埼玉県飯能市南町10番13号 新電元工業株 式会社工場内 (72)発明者 佐々木 正博 埼玉県飯能市南町10番13号 新電元工業株 式会社工場内 (72)発明者 高野 和夫 東京都千代田区内幸町一丁目１番６号 日 本電信電話株式会社内 (72)発明者 尾形 努 東京都千代田区内幸町一丁目１番６号 日 本電信電話株式会社内 (72)発明者 河野 勝 東京都千代田区内幸町一丁目１番６号 日 本電信電話株式会社内 (72)発明者 稲垣 伸夫 東京都武蔵野市緑町三丁目９番11号 株式 会社アフティ内 (72)発明者 山野 佳哉 京都府京都市南区吉祥院西ノ庄猪之馬場町 １番地 日本電池株式会社内 (72)発明者 多田 幸生 京都府京都市南区吉祥院西ノ庄猪之馬場町 １番地 日本電池株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (71) Applicant 000004282 Nippon Battery Co., Ltd. 1 No. 1 Nishinosho Inono Babacho, Kichijoin, Minami-ku, Kyoto Prefecture, Kyoto Prefecture (72) Inventor Kiyotsugu Otsu 10-13 Minamimachi, Hanno City, Saitama Prefecture New Dengen Kogyo Co., Ltd. Inside the factory (72) Inventor Koei Kobayashi 10-13 Minamimachi, Hanno City, Saitama Prefecture Inside Shindengen Kogyo Co., Ltd. (72) Inventor Masahiro Sasaki 10-13 Minami-cho, Hanno City, Saitama Prefecture Shindengen Kogyo Co., Ltd. Inside the factory (72) Inventor Kazuo Takano 1-1-6 Uchisaiwai-cho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation (72) Inventor Tsutomu Ogata 1-1-1 Uchisai-cho, Chiyoda-ku, Tokyo No. 6 Nihon Telegraph and Telephone Corporation (72) Inventor Masaru Kono 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation (72) Inventor Nobuo Inagaki Musashino, Tokyo 3-9-11 Midori-cho, Aichi, Incorporated (72) Inventor, Yoshiya Yamano, Yoshiya Yamano, Kyoto Prefecture Minami-ku, Kyoto-shi, Nishinosho Nishinosho, Nobabacho, Nihon Battery Co., Ltd. (72) Inventor, Yukio Tada, Kyoto, Kyoto Nihon Battery Co., Ltd. No. 1 Inobabamachi, Nishinosho, Kichijoin, Minami-ku, Yokohama
Claims (2)
ッテリ充電電流又は放電電流を検出し、前記バッテリの
内部抵抗を算出し、該バッテリの残容量判定又は劣化判
定を行うバッテリ試験装置に於いて、前記バッテリ電圧
検出回路からの出力信号と前記バッテリ電流検出回路か
らの出力信号は、１組のアナログマルチプレクサにより
交互に切替え入力された後、１組の低速のサンプルホー
ルド回路により、前記アナログマルチプレクサからの出
力信号はホールドされた後、１組のＡＤ変換器によりデ
ィジタル信号に変換され、直接マイクロプロセッサの周
辺として位置づけられたＲＡＭに保管し、該ＲＡＭに保
管されたディジタルデータを前記マイクロプロセッサで
一括処理することにより、前記バッテリ残容量判定又は
劣化判定を行うことを特徴とするバッテリ試験装置。1. A battery test apparatus for detecting a battery voltage and a battery charging current or a discharging current by a battery terminal, calculating an internal resistance of the battery, and determining a remaining capacity or a deterioration of the battery. The output signal from the battery voltage detection circuit and the output signal from the battery current detection circuit are alternately switched and input by a set of analog multiplexers, and then output from the analog multiplexer by a set of low-speed sample hold circuits. After the signal is held, it is converted into a digital signal by a set of AD converters and stored directly in a RAM positioned as a peripheral of the microprocessor, and the digital data stored in the RAM is collectively processed by the microprocessor. The battery remaining capacity or deterioration is determined by A battery testing device characterized by.
Ｃ／ＤＣコンバータ、又は交流出力を得るＡＣ／ＡＣコ
ンバータが、蓄電池を充電しながら負荷に電力を供給
し、前記交流入力停電時には前記蓄電池を電源とし、直
流又は交流電力を負荷に供給する様構成された電力装置
に於いて、特許請求の範囲第一項記載のバッテリ試験装
置を内蔵し、該バッテリ試験装置は前記蓄電池の残容量
の判定又は劣化状態を観測し、測定結果を前記電力装置
より外部に送出する機能を備えたことを特徴とする電力
装置。2. A for obtaining a DC output by using an AC input as a power source
A configuration in which a C / DC converter or an AC / AC converter that obtains an AC output supplies power to a load while charging a storage battery, and uses the storage battery as a power source during the AC input power failure and supplies DC or AC power to the load. In the power device, the battery test device according to claim 1 is built in, the battery test device observes the determination or deterioration state of the remaining capacity of the storage battery, and the measurement result is output from the power device. A power device having a function of transmitting the power to the outside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5294100A JPH07128414A (en) | 1993-10-29 | 1993-10-29 | Battery test device, and electric power device having the test device built in |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5294100A JPH07128414A (en) | 1993-10-29 | 1993-10-29 | Battery test device, and electric power device having the test device built in |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07128414A true JPH07128414A (en) | 1995-05-19 |
Family
ID=17803291
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5294100A Pending JPH07128414A (en) | 1993-10-29 | 1993-10-29 | Battery test device, and electric power device having the test device built in |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07128414A (en) |
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-
1993
- 1993-10-29 JP JP5294100A patent/JPH07128414A/en active Pending
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