JPH07122086A - Semiconductor nonvolatile memory - Google Patents

Abstract

PURPOSE:To prevent the occurrence of drain disturb caused by the injection of drain avalanche hot holes by setting a nonselective word line to a minus voltage and adequately reducing the floating gate potential during a writing. CONSTITUTION:As an example, when a memory cell transistor MT22 is selected in order to write data, a selective bit line BLDN is biased to 7V and a selective word line WLM is biased to 12V. Then, set the biased to 7V and source line BLSN-1, N, N+1 and nonselective bit line BLDN-1, N+1 to 0V and set a nonslective word line WLN-1, N, N+1 to -1V, for example. Since the threshold value voltage of a floating gate FG is on the order of 1 to 2 volts when it has no charge and is in a data '0' condition, the floating gate potential is reduced, the flow of a current is prevented by slightly making a nonselective word line WLM-1, M+1 negative.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile memory, for example, a semiconductor nonvolatile memory device such as a flash EEPROM.

[0002]

2. Description of the Related Art Conventionally, in a nonvolatile memory in which data is written by injecting electrons into a floating gate, for example, an ultraviolet erasable EPROM, a flash EEPROM, etc., when writing data,
Selected word line is 10V to 20V, unselected word line is 0V
V, 5V to 8V for selected bit line, 0V for unselected bit line
Is set to.

FIG. 3 shows a NOR type flash EEPROM.
Memory cell array circuit diagram and data writing
It is a figure which shows the bias conditions in. In FIG. 3, B
LS_N-1, BLS_N, BLS_{N + 1}, BLD_N-1, BLD
_N, BLD_{N + 1}Is the bit line, WL_M-1, WL_M, WL
_{M + 1}Is the word line, MT₁₁~ MT ₃₃Is the memory cell transition
And CG are control gates of each memory cell, FG
Indicates the floating gate of each memory cell
ing.

In this memory cell array, the control gates CG of the memory cell transistors MT _{11 to} MT ₁₃ are connected to the word line WL _M-1 and the memory cell transistor M.
The control gate CG of T _{21 to} MT ₂₃ is the word line WL.
_{To M} , the control gates CG of the memory cell transistors MT _{31 to} MT ₃₃ are connected to the word line WL _{M + 1} . In addition, the memory cell transistors MT ₁₁ and MT
₂₁ , the source / drain of MT ₃₁ is the bit line BLS _N-1 ,
BLD _N-1 has memory cell transistors MT ₁₂ , M
Sources / drains of T ₂₂ and MT ₃₂ are bit lines BLS _N ,
BLD _N has memory cell transistors MT ₁₃ , MT ₂₃ ,
Source / drain of MT ₃₃ are bit lines BLS _{N + 1} , BL
D _{N + 1} respectively.

In such a structure, at the time of writing data, for example, as shown in FIG. 3, the Nth bit line B
Select LD _N , select the Mth word line WL _M ,
When writing data to the memory cell transistor MT ₂₂ , the selected word line WL _M , the non-selected word line WL _M-1 ,
WL _{M + 1} , selected bit line BLD _N , and non-selected bit lines BLS _N-1 , BLS _N , BLS _{N + 1} , BLD _N-1 , B
LD _{N + 1} is biased to levels as shown in FIGS. 3 and 4, respectively. That is, the selected word line WL _M is 12 V, the unselected word lines WL _M−1 and WL _{M + 1} are 0 V, the selected bit line BLD _N is 7 V, and the unselected bit line BL.
S _N-1 , BLS _N , BLS _{N + 1} , BLD _N-1 , BLD
_{N + 1} is set to 0V, respectively.

[0006]

By the way, when writing data to the memory cell transistor MT ₂₂ described above, the memory cell transistor MT on the same bit line is used.
Drain disturb is applied to ₁₂ and MT ₃₂ . The drain disturb will be described in detail below.

FIG. 5 is a correlation diagram between the current injected into the floating gate of the memory cell transistor on the selected bit line and the floating gate potential. In the figure, the vertical axis represents the injection current into the floating gate and the horizontal axis represents the floating gate potential.

The floating gate potential V _f is expressed by the following equation. V _f = αC · V _C + αD · V _D + θ _F / CT (1) where αC is the coupling ratio (0.6 to 0.7) of the control gate CG, and αD is the drain coupling ratio (0. 1), θ _F is floating gate F
The charge amount in G, CT is the total floating gate capacitance, V _C is the control gate voltage, and V _D is the drain voltage (7V).

In FIG. 5, the selected memory cell transistor MT ₂₂ in the above-described example is a region indicated by REA ₄ in the figure, and the channel hot electron injection region AREA _CHE.
become.

The memory cell transistors MT ₁₂ and MT ₃₂ of the selected bit line BLD _N have the following two types of drain disturb possibilities. That is, FIG.
, Drain disturb due to electron withdrawal by Fowler-Nordheim (FN) tunnel current in the area indicated by AREA ₁ , and drain avalanche hot hole (AHH) in the area indicated by AREA ₃ in FIG.
Drain disturb by injection. In order to prevent the drain disturb in these two modes, the floating gate potential V _f is transited to a region indicated by AREA ₂ in FIG.
It is necessary to reduce _f to (-4 to -3V) to 0.5V.

Normally, in the "1" data cell having the threshold voltage V _{th1 of 3} to 5 V or more, the charge amount θ _F in the floating gate FG is θ _F <0 from the above formula (1). , The area AREA ₁ is susceptible to drain disturb due to electron withdrawal by the FN tunnel current. On the other hand, the “0” data cell having the threshold voltage V _th1 of 1 to 2 V is determined by the floating gate F from the above-mentioned formula (1).
Since the charge amount θ _{F in} G is approximately 0, the area AREA ₃
Drain avalanche hot hole (AHH) injection easily causes drain disturbance.

Of these drain disturbs,
For the drain disturb of the "1" data cell, measures such as relaxing the electric field by the drain structure are taken.
Regarding the drain disturb of the "0" data cell,
The current situation is that effective measures have not been taken yet.

Here, in the case of a "0" data cell, the floating gate potential V _f is as follows when the charge amount θ _F in the floating gate FG is set to 0 according to the above equation (1). V _f = αD · V _D ≈0.7 V (2) This indicates that in some cases, the drain Abarache hot hole injection in the area AREA ₃ is performed, and the memory cell transistor is in the depletion state.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor nonvolatile memory device capable of preventing drain disturb during data writing.

[0015]

In order to achieve the above object, according to the present invention, in a semiconductor nonvolatile memory device for writing data by accumulating charges in a charge accumulating portion formed in a channel vicinity region, The non-selected word line at the time of writing is set to a negative voltage.

Further, in the present invention, the negative voltage on the non-selected word line is set to a value within the range of 0> to ≧ −2V.

[0017]

According to the present invention, when writing data, for example, the selected word line is set to 12V, and the non-selected word line is set to a negative voltage, preferably a value within the range of 0> to ≥-2V, for example, -1V. The selected bit line is set to 7V and the non-selected bit line is set to 0V. As a result, the floating gate potential can be appropriately lowered, and the drain disturb associated with the drain avalanche hot hole injection can be prevented.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows a NOR flash E according to the present invention.
FIG. 4 is a circuit diagram of a memory cell array of an EPROM and a diagram showing bias conditions at the time of writing data, and the same components as those of FIG. 3 showing a conventional example are denoted by the same reference numerals.
That is, BLS _N-1 , BLS _N , BLS _{N + 1} , BLD
_N-1 , BLD _N , BLD _{N + 1} are bit lines, WL _M-1 , W
L _M, WL _{M + 1} word lines, MT ₁₁ to MT ₃₃ are respectively the memory cell transistor, CG is a control gate of each memory cell, FG is a floating gate of each memory cell.

In this memory cell array, the control gates CG of the memory cell transistors MT _{11 to} MT ₁₃ are connected to the word line WL _M-1 , and the control gates CG of the memory cell transistors MT _{21 to} MT ₂₃ are the same as in FIG.
Are connected to the word line WL _M with memory cell transistors MT ₃₁ ...
The control gate CG of MT ₃₃ is connected to the word line WL _{M + 1} . The source / drain of the memory cell transistors MT ₁₁ , MT ₂₁ , MT ₃₁ are bit lines BLS _N-1 , BLD _N-1 , and the source / drain of the memory cell transistors MT ₁₂ , MT ₂₂ , MT ₃₂ are bit line BLS. _The memory cell transistor M is connected to _N and BLD _N.
Source / drain of T ₁₃ , MT ₂₃ , and MT ₃₃ are bit lines B
They are connected to LS _{N + 1} and BLD _{N + 1} , respectively.

In such a structure, at the time of writing data, for example, as shown in FIG. 1, the Nth bit line B
Select LD _N , select the Mth word line WL _M ,
When writing data to the memory cell transistor MT ₂₂ , the selected word line WL _M , the non-selected word line WL _M-1 ,
WL _{M + 1} , selected bit line BLD _N , and non-selected bit lines BLS _N-1 , BLS _N , BLS _{N + 1} , BLD _N-1 , B
LD _{N + 1} is biased to levels as shown in FIGS. 1 and 2, respectively. That is, the selected word line WL _M is 12 V, the unselected word lines WL _M−1 , WL _{M + 1} are −1 V,
Selected bit line BLD _N is 7V, and unselected bit line B
LS _N-1 , BLS _N , BLS _{N + 1} , BLD _N-1 , BLD
_{N + 1} is set to 0V, respectively.

In this memory cell, data "0",
The threshold voltages V _th0 and V _th1 in the “1” state are
It usually looks like this: That is, the threshold voltage V _th0 in the case of data “0” in which there is no charge in the floating gate FG is about 1 to 2V. On the other hand, the threshold voltage V _th1 in the case of the data “1” in which the negative charge exists in the floating gate FG is 3 to 5 V or more.

As described above, in this embodiment, the non-selected word line is not 0V at the time of data writing,
It is biased to a slight negative potential of about -1V. As described above, the floating gate potential V _f of the “0” data cell is set to the amount of electric charge θ in the floating gate FG according to the above-described formula (1) by slightly biasing the unselected word line to −1 V. _{If F} is 0,
It looks like this: V _f = αC · V _C + αD · V _D ≈−0.6 + 0.7V≈0.1V (3) That is, the non-selected word line is slightly biased to −1V, or a negative bias is applied, so that “0” data is obtained. The floating gate potential V _f of the cell is lowered to reduce the area AREA in FIG.
_It is possible to avoid ₃ and set it in the area AREA ₂ .

If the negative bias of the non-selected word line is set to about -1 V at most, the floating gate potential V _f of the "1" data cell is too low and the area AREA ₁ in FIG. 5 is not entered. It is possible to avoid the drain disturb due to the electron withdrawal due to the normal FN tunnel current. Therefore, the potential of the non-selected word line at the time of writing is preferably set to about --2V.

As described above, according to this embodiment,
In NOR type EEPROM, when writing data,
Since the non-selected word line is set to the negative voltage, it is possible to prevent the drain disturb caused by the drain avalanche hot hole injection.

[0025]

As described above, according to the present invention,
It is possible to prevent drain disturb during data writing.

[Brief description of drawings]

FIG. 1 is a NOR flash EEPROM according to the present invention.
FIG. 3 is a circuit diagram of the memory cell array and a diagram showing bias conditions at the time of writing data.

FIG. 2 is a diagram showing a bias condition at the time of writing to the memory cell array of the NOR flash EEPROM of FIG.

FIG. 3 is a circuit diagram of a memory cell array of a NOR flash EEPROM and a diagram showing a bias condition at the time of writing data.

FIG. 4 is a diagram showing bias conditions at the time of writing to the memory cell array of the NOR flash EEPROM of FIG.

FIG. 5 is a correlation diagram between a current injected into a floating gate of a memory cell transistor on a selected bit line and a floating gate potential.

[Explanation of symbols]

BLS _N-1 , BLS _N , BLS _{N + 1} , BLD _N-1 , BL
D _N, BLD _{N + 1} ... bit lines _{WL M-1, WL M,} WL M + 1 ... word line _{MT 11 ~MT 13, MT 21 ~MT} 23, MT 31 ~MT 33 ... memory cell transistors

Claims (2)

[Claims] 1. A semiconductor nonvolatile memory device for writing data by accumulating charges in a charge accumulating portion formed in a channel vicinity region, wherein a non-selected word line is set to a negative voltage during data writing. A semiconductor non-volatile memory device characterized by: 2. The semiconductor nonvolatile memory device according to claim 1, wherein the negative voltage on the non-selected word line is set to a value within the range of 0> to ≧ −2V.